CN110957270B - 半导体器件和制造方法 - Google Patents

半导体器件和制造方法 Download PDF

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CN110957270B
CN110957270B CN201910333651.5A CN201910333651A CN110957270B CN 110957270 B CN110957270 B CN 110957270B CN 201910333651 A CN201910333651 A CN 201910333651A CN 110957270 B CN110957270 B CN 110957270B
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CN110957270A (zh
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吴仲强
蔡昕翰
李威缙
李家庆
钟鸿钦
洪正隆
李达元
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本公开涉及半导体器件和制造方法。提供了具有不同阈值电压的半导体器件和制造半导体器件的方法。在实施例中，各个半导体器件的阈值电压是通过在替换栅极工艺内在每个单独栅极堆叠内移除和放置不同材料来调谐的，其中，移除和放置有助于保持针对填充材料的整个工艺窗口足够大以允许完整填充。

Description

半导体器件和制造方法
技术领域
本发明涉及半导体器件和制造方法。
背景技术
半导体器件被用于各种电子应用中，例如，个人计算机、手机、数码相机和其他电子设备。半导体器件通常通过以下方式来制造：在半导体衬底上方按顺序沉积绝缘或电介质层、导电层和半导体材料层，并且使用光刻来图案化各种材料层以在其上形成电路组件和元件。
半导体工业通过不断减小最小特征尺寸来持续改善各种电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度，这允许更多组件被集成到给定区域中。然而，随着最小特征尺寸的减小，出现了应当被解决的其他问题。
发明内容
根据本公开的一个实施例，提供了一种制造半导体器件的方法，所述方法包括：在第一区域、第二区域、第三区域和第四区域上方沉积栅极电介质；在所述第一区域、所述第二区域、所述第三区域和所述第四区域上方沉积第一金属材料；在所述第一区域、所述第二区域、所述第三区域和所述第四区域上方沉积第一功函数层；从所述第三区域中移除所述第一功函数层；在移除所述第一功函数层之后，在所述第一区域、所述第二区域、所述第三区域和所述第四区域上方沉积第二功函数层，所述第二功函数层与所述第一功函数层不同；从所述第一区域和所述第二区域中移除所述第二功函数层；从所述第一区域中移除所述第一功函数层；以及在移除所述第一功函数层之后，在所述第一区域、所述第二区域、所述第三区域和所述第四区域上方沉积填充材料。
根据本公开的另一实施例，提供了一种制造半导体器件的方法，所述方法包括：在第一区域和第二区域上方沉积第一多个栅极材料；通过从所述第一区域中移除所述第一多个栅极材料的第一栅极材料，来调谐由所述第一多个栅极材料形成的晶体管中的第一晶体管的第一阈值电压；以及通过在所述第一区域和所述第二区域上方形成第二栅极材料并且从所述第二区域中移除所述第二栅极材料，来调谐由所述第一多个栅极材料形成的晶体管中的第二晶体管的第二阈值电压，所述第一栅极材料与所述第二栅极材料不同，所述第一晶体管是第一PMOS晶体管，并且所述第二晶体管是第二PMOS晶体管。
根据本公开的又一实施例，提供了一种半导体器件，包括：位于第一半导体鳍上方的第一栅极堆叠，所述第一栅极堆叠包括第一金属材料；位于第二半导体鳍上方的第二栅极堆叠，所述第二栅极堆叠包括所述第一金属材料和与所述第一金属材料不同的第一p金属材料；位于第三半导体鳍上方的第三栅极堆叠，所述第三栅极堆叠包括所述第一金属材料和与所述第一金属材料不同的第二p金属材料；位于第四半导体鳍上方的第四栅极堆叠，所述第四栅极堆叠包括所述第一金属材料、所述第一p金属材料和所述第二p金属材料；并且其中，所述第一栅极堆叠、所述第二栅极堆叠、所述第三栅极堆叠和所述第四栅极堆叠中的每一个包括n金属材料，所述第一栅极堆叠中的n金属材料与所述第一金属材料物理接触，所述第二栅堆叠中的n金属材料与所述第一p金属材料物理接触，所述第三栅堆叠中的n金属材料与所述第二p金属材料物理接触，并且所述第四栅极堆叠中的n金属材料与所述第二p金属材料物理接触。
附图说明
在结合附图阅读下面的具体实施方式时，可以从下面的具体实施方式中最佳地理解本公开的各个方面。应当注意，根据行业的标准做法，各种特征不是按比例绘制的。事实上，为了讨论的清楚起见，各种特征的尺寸可能被任意增大或减小。
图1示出了根据一些实施例的半导体鳍的形成的透视图。
图2示出了根据一些实施例的源极/漏极区域的形成。
图3示出了根据一些实施例的栅极堆叠的材料的形成。
图4示出了根据一些实施例的第一阻挡层的移除工艺。
图5示出了根据一些实施例的第二阻挡层的沉积。
图6示出了根据一些实施例的第二阻挡层的移除工艺。
图7示出了根据一些实施例的第一阻挡层的另一移除工艺。
图8示出了根据一些实施例的填充材料的沉积。
图9示出了根据一些实施例的覆盖的形成。
具体实施方式
下面的公开内容提供了用于实现本发明的不同特征的许多不同的实施例或示例。下文描述了组件和布置的具体示例以简化本公开。当然，这些仅仅是示例而不意图是限制性的。例如，在下面的说明中，在第二特征上方或之上形成第一特征可以包括以直接接触的方式形成第一特征和第二特征的实施例，并且还可以包括可以在第一特征和第二特征之间形成附加特征以使得第一特征和第二特征可以不直接接触的实施例。此外，本公开在各个示例中可能重复参考标号和/或字母。这种重复是为了简单性和清楚性的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
此外，本文中可能使用了空间相关术语(例如“下方”、“之下”、“低于”、“以上”、“上部”等)，以易于描述图中所示的一个要素或特征相对于另一个(一些)要素或特征的关系。这些空间相关术语意在涵盖器件在使用或工作中除了图中所示朝向之外的不同朝向。装置可能以其他方式定向(旋转了90度或处于其他朝向)，并且本文中所用的空间相关描述符同样可能被相应地解释。
现在将针对包括finFET器件(其具有针对5nm或3nm技术节点的多个阈值电压)的特定示例来描述实施例。然而，实施例不限于本文提供的示例，并且可以在多种实施例中实现这些想法。
现在参考图1，示出了半导体器件100(例如，finFET器件)的透视图。在一个实施例中，半导体器件100包括衬底101和第一沟槽103。衬底101可以是硅衬底，尽管也可以使用其他衬底，例如，绝缘体上半导体(SOI)、应变SOI、和绝缘体上硅锗。衬底101可以是p型半导体，尽管在其他实施例中，其可以是n型半导体。
第一沟槽103可以作为最终形成第一隔离区域105的初始步骤被形成。第一沟槽103可以使用掩模层(图1中未单独示出)以及适当的蚀刻工艺来形成。例如，掩模层可以是包括通过例如化学气相沉积(CVD)的工艺形成的氮化硅的硬掩模，尽管可以使用其他材料(例如，氧化物、氮氧化物、碳化硅、它们的组合等)以及其他工艺(例如，等离子体增强化学气相沉积(PECVD)、低压化学气相沉积(LPCVD)、或甚至氧化物形成之后进行氮化)。一旦被形成，就可以通过适当的光刻工艺来图案化掩模层，从而暴露衬底101的将被移除以形成第一沟槽103的那些部分。
然而，如本领域技术人员将认识到的，上述用于形成掩模层的工艺和材料不是能够用于保护衬底101的部分同时暴露衬底101的其他部分的唯一方法。可以利用任意适当的工艺(例如，图案化和显影的光致抗蚀剂)，来暴露衬底101的要被移除以形成第一沟槽103的部分。所有这些方法都旨在被包括在本实施例的范围内。
一旦已经形成并且图案化掩模层，就在衬底101中形成第一沟槽103。可以通过例如反应离子蚀刻(RIE)的适当工艺来移除暴露的衬底101，以便在衬底101中形成第一沟槽103，尽管可以使用任意适当的工艺。在实施例中，第一沟槽103可以被形成为具有距衬底101的表面小于约
Figure BDA0002038443020000041
的第一深度(例如，约
Figure BDA0002038443020000042
)。
然而，如本领域普通技术人员将认识到的，上述用于形成第一沟槽103的工艺仅仅是一个潜在工艺，并不意味着是唯一的实施例。而是，可以使用通过其能够形成第一沟槽103的任意适当的工艺，并且可以使用包括任意数量的掩蔽和移除步骤的任意适当的工艺。
除了形成第一沟槽103之外，掩蔽和蚀刻工艺还从衬底101的保持未被移除的那些部分形成鳍107。为方便起见，在附图中已经将鳍107示出为通过虚线与衬底101分离，尽管可以存在或不存在分离的物理指示。如下所述，可以使用这些鳍107来形成多栅极FinFET晶体管的沟道区域。虽然图1仅示出了从衬底101形成的三个鳍107，但是可以使用任意数量的鳍107。
可以形成鳍107，使得它们在衬底101的表面处的宽度在约5nm与约80nm之间，例如，约30nm。此外，鳍107可以彼此间隔开约10nm与约100nm之间的距离，例如，约50nm。通过以这种方式使鳍107间隔开，鳍107可以各自形成单独的沟道区域，同时仍足够接近以共享公共栅极(下面进一步讨论)。
一旦已经形成第一沟槽103和鳍107，就可以用电介质材料来填充第一沟槽103，并且可以在第一沟槽103内凹陷电介质材料以形成第一隔离区105。电介质材料可以是氧化物材料、高密度等离子体(HDP)氧化物等。在可选的第一沟槽103的清洁和直线化(lining)之后，可以使用化学气相沉积(CVD)方法(例如，HARP工艺)、高密度等离子体CVD方法、或本领域已知的其他适当的形成方法来形成电介质材料。
可以通过以下方式来填充第一沟槽103：用电介质材料过填充(overfill)第一沟槽103和衬底101，并且然后通过适当的工艺(例如，化学机械抛光(CMP)、蚀刻、它们的组合等)来移除第一沟槽103和鳍107外部的多余材料。在实施例中，移除工艺也移除位于鳍107上方的任意电介质材料，使得电介质材料的移除将暴露鳍107的表面以用于进一步处理步骤。
一旦已经用电介质材料填充了第一沟槽103，电介质材料然后就可以远离鳍107的表面被凹陷。凹陷可以被执行以暴露鳍107的侧壁的与鳍107的表面相邻的至少一部分。可以使用将鳍107的顶表面浸入蚀刻剂(例如，HF)的湿法蚀刻来使电介质材料凹陷，尽管可以使用其他蚀刻剂(例如，H2)以及其他方法(例如，反应离子蚀刻、使用诸如NH3/NF3之类的蚀刻剂的干法蚀刻、化学氧化物移除、或干化学清洁)。电介质材料可以被凹陷到距离鳍107的表面在约
Figure BDA0002038443020000051
与约
Figure BDA0002038443020000052
之间的距离，例如，约
Figure BDA0002038443020000053
此外，凹陷还可以移除位于鳍107上方的任意剩余电介质材料，以确保暴露鳍107以用于进一步处理。
然而，如本领域普通技术人员将认识到的，上述步骤可以仅是用于填充和凹陷电介质材料的整个工艺流程的一部分。例如，直线化步骤、清洁步骤、退火步骤、间隙填充步骤、它们的组合等也可以被用来利用电介质材料形成和填充第一沟槽103。所有潜在工艺步骤都旨在被包括在本实施例的范围内。
在已经形成第一隔离区域105之后，可以在每个鳍107上方形成虚设栅极电介质109、虚设栅极电介质109上方的虚设栅极电极111、和第一间隔件113。在实施例中，虚设栅极电介质109可以通过热氧化、化学气相沉积、溅射、或本领域已知和用于形成栅极电介质的任意其他方法来形成。取决于栅极电介质形成的技术，鳍107顶部上的虚设栅极电介质109厚度可以与鳍107的侧壁上的栅极电介质厚度不同。
虚设栅极电介质109可以包括诸如二氧化硅或氮氧化硅之类的材料，其厚度范围从约3埃到约100埃，例如，约10埃。虚设栅极电介质109可以由高电介质常数(高k)材料(例如，具有大于约5的相对电介质常数)来形成，例如，氧化镧(La2O3)、氧化铝(Al2O)、氧化铪(HfO2)、氧氮化铪(HfON)、或氧化锆(ZrO2)、或其组合，其等效氧化物厚度为约0.5埃至约100埃，例如，约10埃或更小。此外，二氧化硅、氮氧化硅、和/或高k材料的任意组合也可以用于虚设栅极电介质109。
虚设栅极电极111可以包括导电或非导电材料，并且可以选自包括多晶硅、W、Al、Cu、AlCu、W、Ti、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、Ta、TaN、Co、Ni、它们的组合等的组。虚设栅极电极111可以通过化学气相沉积(CVD)、溅射沉积、或本领域已知和用于沉积导电材料的其他技术来沉积。虚设栅极电极111的厚度可以在约
Figure BDA0002038443020000061
至约
Figure BDA0002038443020000062
Figure BDA0002038443020000063
的范围内。虚设栅极电极111的顶表面可以具有非平面顶表面，并且可以在虚设栅极电极111的图案化或栅极蚀刻之前被平坦化。此时可以将离子引入或不引入虚设栅极电极111。例如，可以通过离子注入技术引入离子。
一旦被形成，虚设栅极电介质109和虚设栅极电极111可以被图案化以在鳍107上方形成一系列堆叠115。堆叠115限定位于虚设栅极电介质109下方的鳍107的每一侧上的多个沟道区域。可以通过使用例如本领域已知的沉积和光刻技术在虚设栅极电极111上沉积和图案化栅极掩模(图1中未单独示出)来形成堆叠115。栅极掩模可以包括常用的掩蔽和牺牲材料，例如(但不限于)，氧化硅、氮氧化硅、SiCON、SiC、SiOC、和/或氮化硅，并且可以沉积至约
Figure BDA0002038443020000071
与约
Figure BDA0002038443020000072
之间的厚度。可以使用干法蚀刻工艺来蚀刻虚设栅极电极111和虚设栅极电介质109，以形成图案化的堆叠115。
一旦堆叠115已经被图案化，就可以形成第一间隔件113。第一间隔件113可以形成在堆叠115的相对侧上。第一间隔件113通常通过在先前形成的结构上毯式沉积间隔层(图1中未单独示出)而形成。间隔层可以包括SiN、氮氧化物、SiC、SiON、SiOCN、SiOC、氧化物等，并且可以通过用于形成这种层的方法形成，例如，化学气相沉积(CVD)、等离子体增强CVD、溅射、和本领域已知的其他方法。间隔层可以包括具有不同蚀刻特性的不同材料、或与第一隔离区域105内的电介质材料相同的材料。第一间隔件113然后可以被图案化(例如，通过一次或多次蚀刻以从结构的水平表面中移除间隔层)，以形成第一间隔件113。
在一个实施例中，第一间隔件113可以被形成为具有在约
Figure BDA0002038443020000073
与约
Figure BDA0002038443020000074
之间的厚度。此外，一旦已经形成第一间隔件113，与一个堆叠115相邻的第一间隔件113可以和与另一堆叠115相邻的第一间隔件113分开约5nm至约200nm之间的距离，例如，约20nm。然而，可以使用任意适当的厚度和距离。
图2示出了鳍107从未受堆叠115和第一间隔件113保护的那些区域的移除、以及源极/漏极区域201的重新生长。鳍107从未受堆叠115和第一间隔件113保护的那些区域的移除可以通过使用堆叠115和第一间隔件113作为硬掩模的反应离子蚀刻(RIE)或通过任意其他适当的移除工艺来执行。可以继续移除，直到鳍107与第一隔离区域105的表面呈平坦化(如图所示)或处于第一隔离区域105的表面下方。
一旦已经移除了鳍107的这些部分，硬掩模(未单独示出)就被放置并且被图案化以覆盖虚设栅极电极111以防止生长，并且源极/漏极区201可以重新生长与每个鳍107接触。在实施例中，源极/漏极区域201可以重新生长，并且在一些实施例中，源极/漏极区域201可以重新生长以形成应力源(stressor)，该应力源将对位于堆叠115下方的鳍107的沟道区域施加应力。在其中鳍107包括硅并且FinFET是p型器件的实施例中，源极/漏极区域201可以通过选择性外延工艺用(具有与沟道区域不同的晶格常数的)诸如硅之类的材料或诸如硅锗之类的材料重新生长。外延生长工艺可以使用前体(例如，硅烷、二氯硅烷、锗烷等)，并且可以持续约5分钟至约120分钟，例如，约30分钟。
在一个实施例中，源极/漏极区域201可以被形成为具有在约
Figure BDA0002038443020000081
和约
Figure BDA0002038443020000082
之间的厚度，以及在第一隔离区域105上方的在约
Figure BDA0002038443020000083
和约
Figure BDA0002038443020000084
之间的高度(例如，大约
Figure BDA0002038443020000085
)。在该实施例中，源极/漏极区域201可以被形成为具有在第一隔离区域105的上表面上方的在约5nm和约250nm之间的高度，例如，约100nm。然而，可以使用任意适当的高度。
一旦形成源极/漏极区域201，就可以通过注入适当的掺杂剂以补充鳍107中的掺杂剂，来将掺杂剂注入源极/漏极区域201。例如，p型掺杂剂(例如，硼、镓、铟等)可以被注入以形成PMOS器件。替代地，n型掺杂剂(例如，磷、砷、锑等)可以被注入以形成NMOS器件。可以使用叠层115和第一间隔件113作为掩模来注入这些掺杂剂。应当注意，本领域普通技术人员将认识到，可以使用许多其他工艺、步骤等来注入掺杂剂。例如，本领域普通技术人员将认识到，可以使用间隔件和衬垫(liner)的各种组合来执行多个注入，以形成具有适用于特定目的的特定形状或特性的源极/漏极区域。可以使用任意这些工艺来注入掺杂剂，并且以上描述并不意味着将本实施例限制于上述步骤。
此外，在此时，移除在形成源极/漏极区域201期间覆盖虚设栅极电极111的硬掩模。在实施例中，可以使用例如对硬掩模的材料具有选择性的湿法蚀刻工艺或干法蚀刻工艺来移除硬掩模。然而，可以使用任意适当的移除工艺。
图2还示出了在堆叠115和源极/漏极区域201上方形成层间电介质(ILD)层203(在图2中以虚线示出，以便更清楚地示出下面的结构)。ILD层203可以包括诸如硼磷硅酸盐玻璃(BPSG)之类的材料，尽管可以使用任意适当的电介质。可以使用诸如PECVD之类的工艺来形成ILD层203，尽管可以替代地使用诸如LPCVD之类的其他工艺。ILD层203可以被形成为约
Figure BDA0002038443020000091
和约
Figure BDA0002038443020000092
之间的厚度。一旦被形成，就可以使用例如平坦化工艺(例如，化学机械抛光工艺)将ILD层203与第一间隔件113平坦化，尽管可以使用任意适当的工艺。
图3示出了图2沿线3-3'的横截面图，以便更好地示出针对第一栅极堆叠902(图3中未示出，但在下面参考图9示出和描述)具有多个层的虚设栅极电极111和虚设栅极电介质109的材料的移除和替换。此外，在图3中，虽然第一栅极堆叠902被示出为在衬底101的第一区域302内，但是还示出了衬底101的第二区域304(针对第二栅极堆叠904)、衬底101的第三区域306(针对第三栅极堆叠906)、以及衬底101的第四区域308(针对第四栅极堆叠908)。在实施例中，第一栅极堆叠902可以是针对具有第一电压阈值Vt1的第一晶体管903(例如，第一NMOS finFET晶体管)的栅极堆叠，而第二栅极堆叠904可以针对具有与第一电压阈值Vt1不同的第二电压阈值Vt2的第二晶体管905(例如，第二NMOSfinFET晶体管)。此外，第三栅极堆叠906可以针对具有第三电压阈值Vt3的第三晶体管907(例如，第一PMOS finFET晶体管)，而第四栅极堆叠908可以针对具有与第三电压阈值Vt3不同的第四电压阈值Vt4的第四晶体管909(例如，第二PMOS finFET晶体管)。然而，可以使用任意适当的装置。
在实施例中，可以使用例如(利用对虚设栅极电极111和虚设栅极电介质109的材料具有选择性的蚀刻剂的)一个或多个湿法蚀刻工艺或干法蚀刻工艺来移除虚设栅极电极111和虚设栅极电介质109。然而，可以使用任意适当的移除工艺。
一旦已经移除了虚设栅极电极111和虚设栅极电介质109，就可以通过沉积一系列层来开始形成第一栅极堆叠902、第二栅极堆叠904、第三栅极堆叠906、和第四栅极堆叠908的工艺。在实施例中，该系列层可以包括界面层301、第一电介质材料303、第一金属材料305、和第一p金属功函数层307。
可选地，可以在形成第一电介质材料303之前形成界面层301。在实施例中，界面层301可以是通过诸如原位蒸汽生成(ISSG)之类的工艺形成的诸如二氧化硅之类的材料。在另一实施例中，界面层301可以是高k材料(例如，HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、LaO、ZrO、Ta2O5、它们的组合等)，具有在约
Figure BDA0002038443020000101
和约
Figure BDA0002038443020000102
之间的第一厚度T1，例如，约
Figure BDA0002038443020000103
然而，可以使用任意适当的材料或形成工艺。
一旦形成界面层301，第一电介质材料303可以被形成为界面层301上方的覆盖层。在实施例中，第一电介质材料303是通过诸如原子层沉积、化学气相沉积等之类的工艺沉积的高k材料(例如，HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、LaO、ZrO、Ta2O5、它们的组合等)。第一电介质材料303可以被沉积为在约
Figure BDA0002038443020000104
至约
Figure BDA0002038443020000105
之间的第二厚度T2，尽管可以使用任意适当的材料和厚度。
第一金属材料305可以被形成为与第一电介质材料303相邻作为阻挡层，并且可以由以下金属材料形成，例如，TaN、Ti、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、Ru、Mo、WN、其他金属氧化物、金属氮化物、金属硅酸盐、过渡金属氧化物、过渡金属氮化物、过渡金属硅酸盐、金属的氮氧化物、金属铝酸盐、硅酸锆、铝酸锆、它们的组合等等。可以使用诸如原子层沉积、化学气相沉积、溅射等之类的沉积工艺将第一金属材料305沉积为在约
Figure BDA0002038443020000106
和约
Figure BDA0002038443020000107
之间的第三厚度T3，尽管可以使用任意适当的沉积工艺或厚度。
第一p金属功函数层307可以被形成为与第一金属材料305相邻，并且在特定实施例中，可以与第一金属材料305类似。例如，第一p金属功函数层307可以由以下金属材料形成，例如，TiN、Ti、TiAlN、TaC、TaCN、TaSiN、TaSi2、NiSi2、Mn、Zr、ZrSi2、TaN、Ru、Al、Mo、MoSi2、WN、其他金属氧化物、金属氮化物、金属硅酸盐、过渡金属氧化物、过渡金属氮化物、过渡金属硅酸盐、金属的氮氧化物、金属铝酸盐、硅酸锆、铝酸锆、它们的组合等等。此外，可以使用诸如原子层沉积、化学气相沉积、溅射等之类的沉积工艺将第一p金属功函数层307沉积为在约
Figure BDA0002038443020000108
和约
Figure BDA0002038443020000109
之间的第四厚度T4，尽管可以使用任意适当的沉积工艺或厚度。
图4示出了从第三区域306移除第一p金属功函数层307但是不从第一区域302、第二区域304、和第四区域308进行移除。在实施例中，可以通过在第一区域302、第二区域304、第三区域306、和第四区域308上方放置第一光致抗蚀剂401来发起移除。一旦就位，然后就可以图案化第一光致抗蚀剂401以暴露第三区域306，而不暴露第一区域302、第二区域304、和第四区域308。可以通过以下方式来执行图案化：将第一光致抗蚀剂401暴露于图案化的能量源以便修改第一光致抗蚀剂401的物理性质，并且然后施加显影剂以便移除第一光致抗蚀剂401的位于第三区域306上方的那部分，同时留下保护第一区域302、第二区域304和第四区域308的第一光致抗蚀剂401。
一旦第一p金属功函数层307已经暴露在第三区域306中，就可以移除第三区域306中的第一p金属功函数层307。在实施例中，可以利用一个或多个蚀刻工艺(例如，对第一p金属功函数层307(例如，氮化钛)具有选择性的并且在不显著移除下面的第一金属材料305(例如，氮化钽)的材料的情况下停止的湿法蚀刻工艺或干法蚀刻工艺)在第三区域306中移除第一p金属功函数层307。然而，可以使用任意适当的移除工艺。
图5示出了一旦已经移除了第一p金属功函数层307，就可以从第一区域302、第二区域304、和第四区域308上方移除第一光致抗蚀剂401。在实施例中，可以使用诸如灰化之类的工艺来移除第一光致抗蚀剂401，其中增加第一光致抗蚀剂401的温度，直到第一光致抗蚀剂401经历热分解并且然后可以被移除。然而，可以使用任意其他适当的工艺来移除第一光致抗蚀剂401。
图5还示出一旦已经移除了第一光致抗蚀剂401，就可以在第一区域302、第二区域304、第三区域306、和第四区域上方沉积第二p金属功函数层501。在实施例中，第二p金属功函数层501可以是以下金属：具有与第一p金属功函数层307的材料(例如，TiN)相比更高或接近的功函数，以及具有对(第一p金属功函数层307的材料的)蚀刻工艺的很大选择性。在其中第二p金属功函数层501是使用具有湿法蚀刻剂(例如，NH4OH或DIO3)的湿法蚀刻工艺进行图案化并且其中第一p金属功函数层307是氮化钛的一个实施例中，第二p金属功函数层501的材料可以具有大于约500的选择性。然而，可以使用任意适当的选择性。
在特定实施例中，第二p金属功函数层501的材料可以是钨基金属，例如，钨、氮化钨(WNx)、碳化钨氮化物(WCxNy)、氧化钨(WOx)、它们的组合等。在另一实施例中，第二p金属功函数层501可以是钼基金属，例如，钼、氮化钼(MoNx)、它们的组合等。在又一实施例中，第二p金属功函数层501可以是诸如金、铂、钯、它们的组合等之类的材料。但是，可以使用任意适当的材料。
在实施例中，可以使用诸如原子层沉积、化学气相沉积、溅射等之类的沉积工艺来沉积第二p金属功函数层501。此外，第二p金属功函数层501可以被沉积为在约
Figure BDA0002038443020000121
和约
Figure BDA0002038443020000122
之间的第五厚度T5，尽管可以使用任意适当的沉积工艺或厚度。
图6示出了一旦第二p金属功函数层501已经被沉积在第一区域302、第二区域304、第三区域306、和第四区域308上方，就从第一区域302和第二区域304中移除第二p金属功函数层501。在实施例中，可以通过在第一区域302、第二区域304、第三区域306、和第四区域308上方放置第二光致抗蚀剂601来发起移除。一旦就位，然后就可以图案化第二光致抗蚀剂601以暴露第一区域302和第二区域304，而不暴露第三区域306和第四区域308。可以通过以下方式来执行图案化：将第二光致抗蚀剂601暴露于图案化的能量源以便修改第二光致抗蚀剂601的物理性质，并且然后施加显影剂以便移除第二光致抗蚀剂601的位于第一区域302和第二区域304上方的那部分，同时留下保护第三区域306和第四区域308的第二光致抗蚀剂601。
一旦第二p金属功函数层501已经暴露在第一区域302和第二区域304中，就可以移除第一区域302和第二区域304中的第二p金属功函数层501。在实施例中，可以利用一个或多个蚀刻工艺(例如，对第二p金属功函数层501的材料具有选择性的并且在不显著移除下面的第一p金属功函数层307的材料的情况下停止的湿法蚀刻工艺或干法蚀刻工艺)在第一区域302和第二区域304中移除第二p金属功函数层501。然而，可以使用任意适当的移除工艺。
图7示出了一旦已经移除了第二p金属功函数层501，就可以从第三区域306和第四区域308上方移除第二光致抗蚀剂601。在实施例中，可以使用诸如灰化之类的工艺来移除第二光致抗蚀剂601，其中增加第二光致抗蚀剂601的温度，直到第二光致抗蚀剂601经历热分解并且然后可以被移除。然而，可以使用任意其他适当的工艺来移除第二光致抗蚀剂601。
图7还示出一旦已经移除了第二光致抗蚀剂601，就可以从第一区域302中移除第一p金属功函数层307。在实施例中，可以通过在第一区域302、第二区域304、第三区域306、和第四区域308上方放置第三光致抗蚀剂701来发起移除。一旦就位，然后就可以图案化第三光致抗蚀剂701以暴露第一区域302，而不暴露第二区域304、第三区域306、和第四区域308。可以通过以下方式来执行图案化：将第三光致抗蚀剂701暴露于图案化的能量源以便修改第三光致抗蚀剂701的物理性质，并且然后施加显影剂以便移除第三光致抗蚀剂701的位于第一区域302上方的那部分，同时留下保护第二区域304、第三区域306、和第四区域308的第三光致抗蚀剂701。
一旦第一p金属功函数层307已经暴露在第一区域302中，就可以移除第一区域302中的第一p金属功函数层307。在实施例中，可以利用一个或多个蚀刻工艺(例如，对第一p金属功函数层307的材料具有选择性的并且在不显著移除下面的第一金属材料305的材料的情况下停止的湿法蚀刻工艺或干法蚀刻工艺)在第一区域302中移除第一p金属功函数层307。然而，可以使用任意适当的移除工艺。
图8示出了第三光致抗蚀剂701的移除以及第一n金属功函数层802、胶层804、和填充材料806的沉积。在实施例中，可以使用诸如灰化之类的工艺来从第二区域304、第三区域306、和第四区域308上方移除第三光致抗蚀剂701，其中增加第三光致抗蚀剂701的温度，直到第三光致抗蚀剂701经历热分解并且然后可以被移除。然而，可以使用任意其他适当的工艺来移除第三光致抗蚀剂701。
一旦已经移除了第三光致抗蚀剂701，就可以沉积第一n金属功函数层802。在实施例中，第一n金属功函数层802可以是以下材料，例如，Ti、Ag、Al、TaAl、TaAlC、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、其他适当的n型功函数材料的材料、或它们的组合。例如，可以利用原子层沉积(ALD)工艺、CVD工艺等将第一n金属功函数层802沉积为在约
Figure BDA0002038443020000141
至约
Figure BDA0002038443020000142
之间的第六厚度T6，例如，约
Figure BDA0002038443020000143
然而，可以使用任意适当的材料和工艺来形成第一n金属功函数层802。
一旦形成第一n金属功函数层802，就可以形成胶层804，以便帮助将上面的填充材料806与下面的第一n金属功函数层802粘附，并且提供成核层以用于填充材料806的形成。在实施例中，胶层804可以是诸如氮化钛之类的材料，或可以是与第一n金属功函数层802类似的材料，并且可以使用诸如ALD之类的类似工艺来形成为在约
Figure BDA0002038443020000144
和约
Figure BDA0002038443020000145
之间的第七厚度T7，例如，约
Figure BDA0002038443020000146
然而，可以使用任意适当的材料和方法。
一旦已经形成胶层804，就使用胶层804沉积填充材料806以填充开口的其余部分。然而，通过利用第二p金属功函数层501而不是简单地沉积第一p金属功函数层307的附加层，可以使用较少的层以获得所需的阈值电压调谐(下面进一步描述)，并且将由随后沉积的填充材料806填充的宽度与其他方式相比保持较大。例如，在第一区域302中，在沉积胶层804之后的开口的其余部分可以具有在约
Figure BDA0002038443020000147
和约
Figure BDA0002038443020000148
之间的第一宽度W1，例如，约
Figure BDA0002038443020000149
类似地，在第二区域304中，在沉积胶层804之后的开口的其余部分可以具有在约
Figure BDA00020384430200001410
和约
Figure BDA00020384430200001411
之间的第二宽度W2，例如，约
Figure BDA00020384430200001412
在第三区域306中，在沉积胶层804之后的开口的其余部分可以具有在约
Figure BDA00020384430200001413
和约
Figure BDA00020384430200001414
之间的第三宽度W3，例如，约
Figure BDA00020384430200001415
最后，在第四区域308中，在沉积胶层804之后的开口的其余部分可以具有在约
Figure BDA00020384430200001416
Figure BDA00020384430200001417
和约
Figure BDA00020384430200001418
之间的第四宽度W4，例如，约
Figure BDA00020384430200001419
此外，因为第一区域302、第二区域304、第三区域306、和第四区域308中的每一个中的不同层数，所以开口可以各自在填充材料806的沉积期间具有不同的高度。例如，在第一区域302中，在沉积胶层804之后的开口的其余部分可以具有在约60nm和约100nm之间的第一高度H1，例如，约80nm。类似地，在第二区域304中，在沉积胶层804之后的开口的其余部分可以具有在约60nm和约100nm之间的第二高度H2，例如，约80nm。在第三区域306中，在沉积胶层804之后的开口的其余部分可以具有在约60nm和约80nm之间的第三高度H3，例如，约100nm。最后，在第四区域308中，在沉积胶层804之后的开口的其余部分可以具有在约60nm和约100nm之间的第四高度H4，例如，约80nm。
在实施例中，填充材料806可以是诸如钨、Al、Cu、AlCu、W、Ti、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、Ta、TaN、Co、Ni、它们的组合等之类的材料，并且可以使用诸如电镀、化学气相沉积、原子层沉积、物理气相沉积、它们的组合等之类的沉积工艺来形成。此外，填充材料806可以被沉积为约
Figure BDA0002038443020000151
和约
Figure BDA0002038443020000152
之间的厚度，例如，约
Figure BDA0002038443020000153
但是，可以使用任意适当的材料。
然而，通过利用本文描述的实施例，每个开口的纵横比(例如，高度与宽度的比率)可以保持足够小以不抑制填充材料806的沉积。具体地，如果纵横比太大，则填充材料806的沉积过程可能使得形成位于填充材料806内的空隙，这将在进一步的制造或操作期间产生不期望的复杂化。然而，通过在各种栅极堆叠的调谐中使用较少的层，可以保持纵横比较低，从而使得形成空隙的可能性及其负面结果降低。
图9示出了在填充材料806已经被沉积以填充并且过填充开口之后，第一区域302、第二区域304、第三区域306、和第四区域308的每个开口内的材料可以被平坦化以形成第一栅极堆叠902、第二栅极堆叠904、第三栅极堆叠906、和第四栅极堆叠908。在实施例中，可以使用例如化学机械抛光工艺来将材料与第一间隔件113平坦化，尽管可以使用诸如研磨或蚀刻之类的任意适当的工艺。
在第一栅极堆叠902、第二栅极堆叠904、第三栅极堆叠906、和第四栅极堆叠908的材料已经被形成并且被平坦化之后，第一栅极堆叠902、第二栅极堆叠904、第三栅极堆叠906、和第四栅极堆叠908的材料可以被凹陷并且用覆盖层901覆盖。在实施例中，第一栅极堆叠902、第二栅极堆叠904、第三栅极堆叠906、和第四栅极堆叠908的材料可以使用例如(利用对第一栅极堆叠902、第二栅极堆叠904、第三栅极堆叠906、和第四栅极堆叠908的材料具有选择性的蚀刻剂的)湿法蚀刻工艺或干法蚀刻工艺来凹陷。在实施例中，第一栅极堆叠902、第二栅极堆叠904、第三栅极堆叠906、和第四栅极堆叠908的材料可以被凹陷约5nm和约150nm之间的距离，例如，约120nm。然而，可以使用任意适当的过程和距离。
一旦第一栅极堆叠902、第二栅极堆叠904、第三栅极堆叠906、和第四栅极堆叠908的材料已经被凹陷，覆盖层901就可以被沉积并且与第一间隔件113平坦化。在实施例中，覆盖层901是使用诸如原子层沉积、化学气相沉积、溅射等之类的沉积工艺来沉积的诸如SiN、SiON、SiCON、SiC、SiOC、它们的组合等之类的材料。覆盖层901可以被沉积为在约
Figure BDA0002038443020000163
Figure BDA0002038443020000161
和约
Figure BDA0002038443020000162
之间的厚度，并且然后使用诸如化学机械抛光之类的平坦化工艺进行平坦化，使得覆盖层901与第一间隔件113是平坦的。
通过利用本文描述的实施例，可以实现具有单独调谐的阈值电压的多个晶体管，而不会减少各种制造工艺窗口。例如，在第一区域302内，第一晶体管903可以用包括界面层301、第一电介质材料303、第一金属材料305、第一n金属功函数层802、胶层804、和填充材料806的栅极堆叠来形成。这样，针对第一NMOS器件，第一晶体管903可以具有在约0.01V和约0.15V之间的第一阈值电压Vt1，例如，约0.1V。
类似地，在第二区域304内，第二晶体管905可以用包括界面层301、第一电介质材料303、第一金属材料305、第一p金属功函数层307、第一n金属功函数层802、胶层804、和填充材料806的栅极堆叠来形成。这样，针对第二NMOS器件，第二晶体管905可以具有在约0.15V和约0.4V之间的第二阈值电压Vt2，例如，约0.25V。
此外，在第三区域306内，第三晶体管907可以用包括界面层301、第一电介质材料303、第一金属材料305、第二p金属功函数层501、第一n金属功函数层802、胶层804、和填充材料806的栅极堆叠来形成。这样，针对第一PMOS器件，第三晶体管907可以具有在约0.15V和约0.4V之间的第三阈值电压Vt3，例如，约0.25V。
最后，在第四区域308内，第四晶体管909可以用包括界面层301、第一电介质材料303、第一金属材料305、第一p金属功函数层307、第二p金属功函数层501、第一n金属功函数层802、胶层804、和填充材料806的栅极堆叠来形成。这样，针对第二PMOS器件，第四晶体管909可以具有在约0.01V和约0.15V之间的第四阈值电压Vt4，例如，约0.1V。
通过利用本文描述的实施例，利用多种不同材料来调谐器件的阈值电压。通过利用多种不同金属，可以避免堆叠多层相同材料(例如，TiN)，并且可以实现与相同材料本身相比的整体厚度减小。这样，可以减小层的总厚度，这增加了间隙填充窗口，从而降低了后续层的成本。这种减小还允许更好的阈值稳定性，因为将形成更少的空隙并且金属栅极可以完全填充开口。这样，可以在更窄的临界尺寸(例如，针对5nm和3nm技术节点)中实现多个阈值电压调谐，而不牺牲N/P图案化和金属栅极间隙填充窗口。
在一个实施例中，一种制造半导体器件的方法包括：在第一区域、第二区域、第三区域和第四区域上方沉积栅极电介质；在第一区域、第二区域、第三区域和第四区域上方沉积第一金属材料；在第一区域、第二区域、第三区域和第四区域上方沉积第一功函数层；从第三区域移除第一功函数层；在移除第一功函数层之后，在第一区域、第二区域、第三区域和第四区域上方沉积第二功函数层，第二功函数层与第一功函数层不同；从第一区域和第二区域移除第二功函数层；从第一区域移除第一功函数层；在移除第一功函数层之后，在第一区域、第二区域、第三区域和第四区域上方沉积填充材料。在实施例中，第一功函数层包括氮化钛。在实施例中，第二功函数层包括钨。在实施例中，第二功函数层包含氧化钨。在实施例中，第二功函数层包括氮化钨。在实施例中，第二功函数层包含钼。在实施例中，第二功函数层包括氮化钼。
在另一实施例中，一种制造半导体器件的方法包括：在第一区域和第二区域上方沉积第一多个栅极材料；通过从第一区域中移除第一多个栅极材料的第一栅极材料，来调谐由第一多个栅极材料形成的晶体管中的第一个晶体管的第一阈值电压；通过在第一区域和第二区域上方形成第二栅极材料并且从第二区域中移除第二栅极材料，来调谐由第一多个栅极材料形成的晶体管中的第二个晶体管的第二阈值电压，第一栅极材料与第二栅极材料不同，第一个晶体管是第一PMOS晶体管，第二个晶体管是第二PMOS晶体管。在实施例中，在第一区域上方沉积第二栅极材料包括：以与阻挡层物理接触的方式来沉积第二栅极材料。在实施例中，在第二区域上方沉积第二栅极材料包括：以与第二区域中的第一栅极材料物理接触的方式来沉积第二栅极材料。在实施例中，阻挡层包括氮化钽。在实施例中，沉积第一多个栅极材料还包括：在半导体鳍上方沉积界面层；以及在界面层上方沉积电介质覆盖层。在实施例中，方法还包括在第二栅极材料上方沉积胶层。在实施例中，方法还包括在胶层上方沉积填充材料。
在又一实施例中，一种半导体器件包括：位于第一半导体鳍上方的第一栅极堆叠，第一栅极堆叠包括第一金属材料；位于第二半导体鳍上方的第二栅极堆叠，第二栅极堆叠包括第一金属材料和与第一金属材料不同的第一p金属材料；位于第三半导体鳍上方的第三栅极堆叠，第三栅极堆叠包括第一金属材料和与第一金属材料不同的第二p金属材料；位于第四半导体鳍上方的第四栅极堆叠，第四栅极堆叠包括第一金属材料、第一p金属材料和第二p金属材料；其中，第一栅极堆叠、第二栅极堆叠、第三栅极堆叠和第四栅极堆叠中的每一个包括n金属材料，第一栅极堆叠中的n金属材料与第一金属材料物理接触，第二栅堆叠中的n金属材料与第一p金属材料物理接触，第三栅堆叠中的n金属材料与第二p金属材料物理接触，第四栅极叠层中的n金属材料与第二p金属材料物理接触。在实施例中，第二p金属材料包括钨基材料。在实施例中，第二p金属材料包括碳氮化钨。在实施例中，第二p金属材料包括钼基材料。在实施例中，第二p金属材料包括氮化钼。在实施例中，第一p金属材料包括氮化钛。
上文概述了一些实施例的特征，以使本领域技术人员可以更好地理解本公开的各个方面。本领域技术人员应当明白，他们可以容易地使用本公开作为基础来设计或修改其他处理和结构，以实施与本文所介绍的实施例相同的目的和/或实现相同的优点。本领域技术人员还应当意识到，这些等同构造并不脱离本公开的精神和范围，并且他们可以在不脱离本公开的精神和范围的情况下进行各种改动、替代和变更。
示例1.一种制造半导体器件的方法，所述方法包括：在第一区域、第二区域、第三区域和第四区域上方沉积栅极电介质；在所述第一区域、所述第二区域、所述第三区域和所述第四区域上方沉积第一金属材料；在所述第一区域、所述第二区域、所述第三区域和所述第四区域上方沉积第一功函数层；从所述第三区域中移除所述第一功函数层；在移除所述第一功函数层之后，在所述第一区域、所述第二区域、所述第三区域和所述第四区域上方沉积第二功函数层，所述第二功函数层与所述第一功函数层不同；从所述第一区域和所述第二区域中移除所述第二功函数层；从所述第一区域中移除所述第一功函数层；以及在移除所述第一功函数层之后，在所述第一区域、所述第二区域、所述第三区域和所述第四区域上方沉积填充材料。
示例2.根据示例1所述的方法，其中，所述第一功函数层包括氮化钛。
示例3.根据示例2所述的方法，其中，所述第二功函数层包括钨。
示例4.根据示例2所述的方法，其中，所述第二功函数层包括氧化钨。
示例5.根据示例2所述的方法，其中，所述第二功函数层包括氮化钨。
示例6.根据示例2所述的方法，其中，所述第二功函数层包括钼。
示例7.根据示例1所述的方法，其中，所述第二功函数层包括氮化钼。
示例8.一种制造半导体器件的方法，所述方法包括：在第一区域和第二区域上方沉积第一多个栅极材料；通过从所述第一区域中移除所述第一多个栅极材料的第一栅极材料，来调谐由所述第一多个栅极材料形成的晶体管中的第一晶体管的第一阈值电压；以及通过在所述第一区域和所述第二区域上方形成第二栅极材料并且从所述第二区域中移除所述第二栅极材料，来调谐由所述第一多个栅极材料形成的晶体管中的第二晶体管的第二阈值电压，所述第一栅极材料与所述第二栅极材料不同，所述第一晶体管是第一PMOS晶体管，并且所述第二晶体管是第二PMOS晶体管。
示例9.根据示例8所述的方法，其中，在所述第一区域上方沉积所述第二栅极材料包括：以与阻挡层物理接触的方式来沉积所述第二栅极材料。
示例10.根据示例9所述的方法，其中，在所述第二区域上方沉积所述第二栅极材料包括：以与所述第二区域中的所述第一栅极材料物理接触的方式来沉积所述第二栅极材料。
示例11.根据示例10所述的方法，其中，所述阻挡层包括氮化钽。
示例12.根据示例8所述的方法，其中，沉积所述第一多个栅极材料还包括：在半导体鳍上方沉积界面层；以及在所述界面层上方沉积电介质覆盖层。
示例13.根据示例8所述的方法，还包括在所述第二栅极材料上方沉积胶层。
示例14.根据示例13所述的方法，还包括在所述胶层上方沉积填充材料。
示例15.一种半导体器件，包括：位于第一半导体鳍上方的第一栅极堆叠，所述第一栅极堆叠包括第一金属材料；位于第二半导体鳍上方的第二栅极堆叠，所述第二栅极堆叠包括所述第一金属材料和与所述第一金属材料不同的第一p金属材料；位于第三半导体鳍上方的第三栅极堆叠，所述第三栅极堆叠包括所述第一金属材料和与所述第一金属材料不同的第二p金属材料；位于第四半导体鳍上方的第四栅极堆叠，所述第四栅极堆叠包括所述第一金属材料、所述第一p金属材料和所述第二p金属材料；并且其中，所述第一栅极堆叠、所述第二栅极堆叠、所述第三栅极堆叠和所述第四栅极堆叠中的每一个包括n金属材料，所述第一栅极堆叠中的n金属材料与所述第一金属材料物理接触，所述第二栅堆叠中的n金属材料与所述第一p金属材料物理接触，所述第三栅堆叠中的n金属材料与所述第二p金属材料物理接触，并且所述第四栅极堆叠中的n金属材料与所述第二p金属材料物理接触。
示例16.根据示例15所述的半导体器件，其中，所述第二p金属材料包括钨基材料。
示例17.根据示例16所述的半导体器件，其中，所述第二p金属材料包括碳氮化钨。
示例18.根据示例15所述的半导体器件，其中，所述第二p金属材料包括钼基材料。
示例19.根据示例18所述的半导体器件，其中，所述第二p金属材料包括氮化钼。
示例20.根据示例15所述的半导体器件，其中，所述第一p金属材料包括氮化钛。

Claims (20)

1.一种制造半导体器件的方法，所述方法包括：
在第一区域、第二区域、第三区域和第四区域上方沉积栅极电介质；
在所述第一区域、所述第二区域、所述第三区域和所述第四区域上方沉积第一金属材料；
在所述第一区域、所述第二区域、所述第三区域和所述第四区域上方沉积第一p功函数层；
从所述第三区域中移除所述第一p功函数层；
在从所述第三区域中移除所述第一p功函数层之后，在所述第一区域、所述第二区域、所述第三区域和所述第四区域上方沉积第二p功函数层，所述第二p功函数层与所述第一p功函数层不同；
从所述第一区域和所述第二区域中移除所述第二p功函数层；
从所述第一区域中移除所述第一p功函数层；
在从所述第一区域中移除所述第一p功函数层之后，在所述第一区域、所述第二区域、所述第三区域和所述第四区域上方沉积n功函数层；以及
在所述第一区域、所述第二区域、所述第三区域和所述第四区域上方沉积填充材料。
2.根据权利要求1所述的制造半导体器件的方法，其中，所述第一p功函数层包括氮化钛。
3.根据权利要求2所述的制造半导体器件的方法，其中，所述第二p功函数层包括钨。
4.根据权利要求2所述的制造半导体器件的方法，其中，所述第二p功函数层包括氧化钨。
5.根据权利要求2所述的制造半导体器件的方法，其中，所述第二p功函数层包括氮化钨。
6.根据权利要求2所述的制造半导体器件的方法，其中，所述第二p功函数层包括钼。
7.根据权利要求1所述的制造半导体器件的方法，其中，所述第二p功函数层包括氮化钼。
8.一种制造半导体器件的方法，所述方法包括：
在第一区域和第二区域上方沉积第一多个栅极材料；
通过从所述第一区域中完全移除所述第一多个栅极材料的第一p栅极材料，来调谐由所述第一多个栅极材料形成的晶体管中的第一晶体管的第一阈值电压；以及
通过在所述第一区域和所述第二区域上方形成第二p栅极材料并且从所述第二区域中完全移除所述第二p栅极材料，来调谐由所述第一多个栅极材料形成的晶体管中的第二晶体管的第二阈值电压，所述第一p栅极材料与所述第二p栅极材料不同，所述第一晶体管是第一PMOS晶体管，并且所述第二晶体管是第二PMOS晶体管。
9.根据权利要求8所述的制造半导体器件的方法，其中，在所述第一区域上方沉积所述第二p栅极材料包括：以与阻挡层物理接触的方式来沉积所述第二p栅极材料。
10.根据权利要求9所述的制造半导体器件的方法，其中，在所述第二区域上方沉积所述第二p栅极材料包括：以与所述第二区域中的所述第一p栅极材料物理接触的方式来沉积所述第二p栅极材料。
11.根据权利要求10所述的制造半导体器件的方法，其中，所述阻挡层包括氮化钽。
12.根据权利要求8所述的制造半导体器件的方法，其中，沉积所述第一多个栅极材料还包括：
在半导体鳍上方沉积界面层；以及
在所述界面层上方沉积电介质覆盖层。
13.根据权利要求8所述的制造半导体器件的方法，还包括在所述第二p栅极材料上方沉积胶层。
14.根据权利要求13所述的制造半导体器件的方法，还包括在所述胶层上方沉积填充材料。
15.一种半导体器件，包括：
位于第一半导体鳍上方的第一栅极堆叠，所述第一栅极堆叠包括第一金属材料；
位于第二半导体鳍上方的第二栅极堆叠，所述第二栅极堆叠包括所述第一金属材料和与所述第一金属材料不同的第一p金属材料；
位于第三半导体鳍上方的第三栅极堆叠，所述第三栅极堆叠包括所述第一金属材料和与所述第一金属材料不同的第二p金属材料，其中所述第二p金属材料具有与所述第一p金属材料的功函数相比更高或接近的功函数；
位于第四半导体鳍上方的第四栅极堆叠，所述第四栅极堆叠包括所述第一金属材料、所述第一p金属材料和所述第二p金属材料；并且
其中，所述第一栅极堆叠、所述第二栅极堆叠、所述第三栅极堆叠和所述第四栅极堆叠中的每一个包括n金属材料，所述第一栅极堆叠中的n金属材料与所述第一金属材料物理接触，所述第二栅极堆叠中的n金属材料与所述第一p金属材料物理接触，所述第三栅极堆叠中的n金属材料与所述第二p金属材料物理接触，并且所述第四栅极堆叠中的n金属材料与所述第二p金属材料物理接触。
16.根据权利要求15所述的半导体器件，其中，所述第二p金属材料包括钨基材料。
17.根据权利要求16所述的半导体器件，其中，所述第二p金属材料包括碳氮化钨。
18.根据权利要求15所述的半导体器件，其中，所述第二p金属材料包括钼基材料。
19.根据权利要求18所述的半导体器件，其中，所述第二p金属材料包括氮化钼。
20.根据权利要求15所述的半导体器件，其中，所述第一p金属材料包括氮化钛。
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