WO2022062494A1 - 开口结构及其形成方法、接触插塞及其形成方法 - Google Patents

开口结构及其形成方法、接触插塞及其形成方法 Download PDF

Info

Publication number
WO2022062494A1
WO2022062494A1 PCT/CN2021/100699 CN2021100699W WO2022062494A1 WO 2022062494 A1 WO2022062494 A1 WO 2022062494A1 CN 2021100699 W CN2021100699 W CN 2021100699W WO 2022062494 A1 WO2022062494 A1 WO 2022062494A1
Authority
WO
WIPO (PCT)
Prior art keywords
hole
etching
layer
central
dielectric layer
Prior art date
Application number
PCT/CN2021/100699
Other languages
English (en)
French (fr)
Inventor
吴秉桓
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/578,509 priority Critical patent/US20220139721A1/en
Publication of WO2022062494A1 publication Critical patent/WO2022062494A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes

Definitions

  • the present application relates to the field of semiconductors, and in particular, to an opening structure and a method for forming the same, a contact plug and a method for forming the same.
  • the formation process of the existing contact plugs generally includes: forming a target metal layer in a substrate, and the target metal layer is connected to the surface of the substrate. flushing; forming a dielectric layer on the substrate and the target metal layer; forming an etched through hole (or contact window) in the dielectric layer exposing the surface of the target metal layer; filling the etched through hole (or contact window) with metal, Contact plugs are formed.
  • the aspect ratio of the etched vias formed in the dielectric layer is also continuously improved, and it has always been a great challenge for the etching process to challenge vias with high aspect ratios.
  • Forming high aspect ratio etched vias often suffers from via offset, poor via contact, or via overetch.
  • the embodiments of the present application provide an opening structure and a method for forming the same, a contact plug and a method for forming the same.
  • the application provides a method for forming an opening structure, comprising:
  • annular spacer on the surface of the target layer, the annular spacer having a central through hole exposing part of the surface of the target layer;
  • the dielectric layer is etched, an etching hole communicated with the central through hole is formed in the dielectric layer, and the etching hole and the central through hole constitute an opening structure.
  • an etching guide structure is also formed in the central through hole, and when the dielectric layer is etched to form an etching hole communicating with the central through hole, the etching rate of the etching guide structure is higher than that of the etching guide structure. The etch rate of the dielectric layer.
  • the etch guide structure is an air gap structure or a sacrificial layer filling the central through hole, and the top of the etch guide structure is lower than the top surface of the annular spacer.
  • the formation process of the air gap structure is: when the dielectric layer is formed by a chemical vapor deposition process, by adjusting the step coverage ratio of the deposition process, the formed dielectric layer closes the opening structure of the central through hole, An air gap structure is formed.
  • the material of the sacrificial layer is different from the material of the dielectric layer, and when the dielectric layer is etched to form an etching hole connected to the central through hole, the etching rate of the sacrificial layer is higher than that of all the materials. The etching rate of the dielectric layer.
  • the material of the annular spacer is different from the material of the dielectric layer, and when the dielectric layer is etched to form an etching hole communicating with the central through hole, the etching rate of the dielectric layer is higher than that of the dielectric layer.
  • the etch rate of the annular spacer is higher than that of the dielectric layer.
  • the forming process of the annular spacer includes: forming a masking material layer on the surface of the substrate and the partial surface of the target layer, and forming a through hole exposing the partial surface of the target layer in the masking material layer ; Form a spacer material layer on the sidewall and bottom surface of the through hole and the surface of the mask material layer; remove the spacer material on the surface of the mask material layer and the bottom surface of the through hole by maskless etching layer, an annular gasket is formed on the sidewall surface of the through hole, and a central through hole is formed in the middle of the annular gasket; the mask material layer is removed.
  • the shape of the annular gasket is an annular shape, an elliptical annular shape or a rectangular annular shape.
  • the inner diameter of the annular spacer is greater than or equal to the diameter of the etching hole.
  • one of the etching holes is communicated with a corresponding central through hole, or one of the etching holes is communicated with a plurality of corresponding central through holes, and a plurality of the etching holes are communicated with a corresponding one of the central through holes.
  • the present application also provides a method for forming a contact plug, comprising:
  • Conductive material is formed in the contact window structure to form contact plugs.
  • the application also provides an opening structure, comprising:
  • a substrate wherein a target layer is formed in the substrate, and the substrate exposes the surface of the target layer
  • annular spacer located on the surface of the target layer, wherein the annular spacer has a central through hole exposing part of the surface of the target layer;
  • An etching hole in the dielectric layer communicated with the central through hole.
  • the material of the annular spacer is different from the material of the dielectric layer.
  • the inner diameter of the annular spacer is greater than or equal to the diameter of the etching hole.
  • the application also provides a contact plug, comprising:
  • a substrate wherein a target layer is formed in the substrate, and the substrate exposes the surface of the target layer
  • annular spacer located on the surface of the target layer, wherein the annular spacer has a central through hole exposing part of the surface of the target layer;
  • the method for forming an opening structure of the present application provides a substrate, a target layer is formed in the substrate, and the substrate exposes the surface of the target layer; an annular gasket is formed on the surface of the target layer, and a middle of the annular gasket is formed. having a central through hole exposing part of the surface of the target layer; forming a dielectric layer covering the substrate, the target layer and the annular spacer; etching the dielectric layer, and forming an etching hole in the dielectric layer that communicates with the central through hole, The etching hole and the central through hole constitute an opening structure.
  • the annular spacer when the etching hole is formed in the dielectric layer, when the etching hole is bent or the position is shifted, the annular spacer can prevent the lateral etching of the bottom of the etching hole, so that the The bottom is guided into the central through hole between the annular spacers, so that the bottom of the etched hole is corrected to the correct position, so that the formed opening structure can normally expose the surface of the target metal layer.
  • the existence of the annular spacer Abnormalities such as leakage caused by metal diffusion caused by the formation of contact plugs in subsequent opening structures can be prevented.
  • the etch guide structure in the subsequent process of etching the dielectric layer to form the etch hole, due to the etch guide structure
  • the etching rate is higher than the etching rate of the dielectric layer, so that the bottom of the through hole is easier to move in the direction of the etching guide structure, so that the bottom of the etching hole is guided into the central through hole, and through the etching
  • the etching guide structure can make the formed opening structure reach the target layer quickly, shorten the etching time for forming the opening structure, simplify the complexity of the etching process of the opening structure, and optimize the etching process of the opening structure , thereby preventing over-etching of the target layer.
  • the etching plasma gas can be correctly guided to The direction of the central through hole is moved, so that the bottom of the etched hole with alignment offset or bending can be guided into the central through hole more accurately and faster through the etching guide structure, so as to achieve the effect of truncating and straightening, thereby The problem that the formed opening structure cannot normally expose the surface of the target layer can be prevented.
  • the forming process of the annular spacer includes: forming a masking material layer on the surface of the substrate and the partial surface of the target layer, and forming a through hole exposing the partial surface of the target layer in the masking material layer; The sidewall and bottom surface of the through hole and the surface of the mask material layer form a spacer material layer; the surface of the mask material layer and the spacer material layer on the bottom surface of the through hole are removed by maskless etching, An annular spacer is formed on the sidewall surface of the through hole.
  • the size and shape of the annular spacer formed in this way are more precise and have a higher sidewall topography.
  • the etching guide structure is an air gap structure, and the air gap structure is composed of air, so when the etching hole is formed by subsequent etching of the dielectric layer, the bottom of the etching hole can be more easily guided to the central through hole. in the hole.
  • the etching guide structure is a sacrificial layer filling the central through hole, and the material of the sacrificial layer is different from the material of the subsequently formed dielectric layer.
  • the sacrificial layer is The etching rate of the layer is higher than the etching rate of the dielectric layer, so when the dielectric layer is subsequently etched to form an etching hole, the bottom of the etching hole can be more easily guided into the central through hole.
  • the annular spacer when an etching hole is formed in the dielectric layer through an annular spacer, the annular spacer can prevent lateral etching of the bottom of the etching hole when the etching hole is bent or shifted in position, The bottom of the etching hole is guided into the central through hole between the annular spacers, so that the bottom of the etching hole is corrected to the correct position, so that the formed opening structure can normally expose the surface of the target metal layer.
  • the existence of the spacer can prevent abnormality such as leakage caused by metal diffusion caused by the formation of contact plugs in the subsequent opening structure.
  • the annular spacer can prevent the side of the bottom of the etching hole from being etched.
  • the bottom of the etching hole is guided into the central through hole between the annular spacers, so that the bottom of the etching hole is corrected to the correct position, so that the formed opening structure can normally expose the surface of the target metal layer , so that the contact plug formed in the opening structure can be normally connected to the target metal layer.
  • the existence of the annular gasket can prevent abnormal leakage caused by metal diffusion caused by the formation of the contact plug in the subsequent opening structure.
  • 1 is a schematic structural diagram of a conventionally formed through hole
  • FIGS. 2 to 14 are schematic cross-sectional structural diagrams of the formation process of the opening structure according to the embodiment of the present application.
  • FIG. 15 is a schematic cross-sectional structure diagram of a process of forming a contact plug according to an embodiment of the present application.
  • the etched via 104 is easily bent, so that the bottom of the etched via deviates from the normal position, so that the surface of the target metal layer cannot be exposed normally. Or, due to the deviation of the over-etching process, the formed etched through hole deviates from the normal position.
  • the present application provides an opening structure and a method for forming the same, a contact plug and a method for forming the same, and the method for forming the opening structure provides a substrate in which a target layer is formed, and the substrate exposes the the surface of the target layer; an annular gasket is formed on the surface of the target layer, and the annular gasket has a central through hole exposing part of the surface of the target layer; a dielectric layer covering the substrate, the target layer and the annular gasket is formed; The dielectric layer is etched, an etching hole communicated with the central through hole is formed in the dielectric layer, and the etching hole and the central through hole constitute an opening structure.
  • the annular spacer when the etching hole is formed in the dielectric layer, when the etching hole is bent or the position is shifted, the annular spacer can prevent the lateral etching of the bottom of the etching hole, so that the The bottom is guided into the central through hole between the annular spacers, so that the bottom of the etched hole is corrected to the correct position, so that the formed opening structure can normally expose the surface of the target metal layer.
  • the existence of the annular spacer Abnormalities such as leakage caused by metal diffusion caused by the formation of contact plugs in subsequent opening structures can be prevented.
  • a substrate 201 having a target layer 202 formed therein is provided, and the substrate 201 exposes a surface of the target layer 202 .
  • the substrate 201 may be a semiconductor substrate
  • the target layer 202 may be a doped region (such as a doped region doped with N-type impurity ions or doped with P-type impurity ions) located in the semiconductor substrate. region) or a metal suicide region (such as a nickel suicide region or a cobalt suicide region) in a semiconductor substrate.
  • the material of the semiconductor substrate can be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or It can also be other materials, such as III-V group compounds such as gallium arsenide.
  • the base 201 may include a semiconductor substrate and an interlayer dielectric layer in the semiconductor substrate, and the target layer 202 is in the interlayer dielectric layer.
  • the interlayer dielectric layer may be a single-layer or multi-layer stack structure
  • the target layer 202 may be a metal layer
  • the metal layer may be connected to a conductive structure (such as a conductive plug) formed in the underlying dielectric layer.
  • the surface of the target layer 202 may be flush with the surface of the substrate 201 or slightly higher than the surface of the substrate 102 .
  • target layers 202 There may be one or more ( ⁇ 2) target layers 202 formed in the substrate 201. When there are multiple target layers 202, the adjacent target layers are separated. In this embodiment, only the substrate is used.
  • a target layer 202 in 201 is illustrated as an example.
  • a masking material layer 206 is formed on the substrate 201 and a portion of the surface of the target layer 202 , and a masking material layer 206 is formed to expose a portion of the surface of the target layer 202 . Via 207.
  • the material of the mask material layer 206 can be one or more of photoresist, silicon nitride, silicon oxide, silicon carbonitride, silicon oxynitride, polysilicon, amorphous silicon, amorphous carbon, and low-K dielectric materials. kind.
  • the formation process of the mask material layer 206 may be a chemical vapor deposition process.
  • the material of the mask material layer 206 is photoresist, and through holes 207 are formed in the mask material layer 206 through exposure and development processes.
  • a through hole 207 may be formed in the mask material layer 206 through an etching process.
  • the shape and position of the through hole 207 define the shape and position of the subsequently formed annular spacer.
  • a spacer material layer 208 is formed on the sidewall and bottom surfaces of the through hole 207 and the surface of the mask material layer 206 .
  • the shim material layer 208 is subsequently configured to form an annular shim.
  • the material of the gasket material layer 208 is different from the material of the subsequently formed dielectric layer.
  • the dielectric layer has a high etching selectivity ratio relative to the annular gasket, so that The annular structure can effectively prevent the lateral etching when the through hole is formed by the etching medium layer, and guide the bottom of the etching hole into the central through hole more effectively.
  • the material of the annular spacer material layer 208 may be one or more of silicon nitride, silicon oxide, silicon carbonitride, and silicon oxynitride.
  • the material of the annular spacer material layer 208 is silicon nitride, and a chemical vapor deposition process is used to form the annular spacer material layer.
  • the thickness of the spacer material layer 208 determines the width of the subsequently formed annular spacer. In one embodiment, the thickness of the spacer material layer 208 is 5nm-5um.
  • the surface of the mask material layer 206 and the spacer material layer on the bottom surface of the through hole are removed by maskless etching, and an annular spacer 203 is formed on the sidewall surface of the through hole, and the middle of the annular spacer 203 is formed.
  • a central through hole 213 is formed.
  • the annular spacer 203 when the etching hole is subsequently formed in the dielectric layer, when the etching hole is bent or the position is offset, the annular spacer can prevent the lateral etching of the bottom of the etching hole, so that the etching The bottom of the hole is guided into the central through hole between the annular spacers, so that the bottom of the etched hole is corrected to the correct position, so that the formed opening structure can normally expose the surface of the target metal layer. Existence can prevent abnormality such as leakage caused by metal diffusion caused by the formation of contact plugs in the subsequent opening structure.
  • the etching of the gasket material layer adopts an anisotropic dry etching process, which may be a plasma etching process.
  • the mask material layer 206 is removed, and the mask material layer 206 may be removed by a wet or dry etching process.
  • FIGS. 6 and 7 are schematic top views of the annular gasket 203 formed above.
  • the annular gasket 203 shown in FIG. 6 is in the shape of a circular ring, and the annular gasket shown in FIG.
  • the shape of the sheet 203 is an elliptical ring. In other embodiments, the shape of the annular gasket 203 may also be a rectangular annular shape.
  • the inner diameter of the annular gasket 203 may be greater than or equal to the diameter of the etching hole formed in the subsequent dielectric layer. When the etching hole is bent, the bottom of the etching hole can be more easily guided to the middle of the annular gasket 203. in the central through hole.
  • the outer diameter of the annular spacer may be smaller than the diameter of the etching hole formed in the subsequent dielectric layer.
  • the mask material layer 206 is an isolation material, which can be configured as electrical isolation between devices, for example, the mask material layer is the same material as the subsequently formed dielectric layer. Meanwhile, after the annular spacer 203 is formed, the mask material layer 206 is retained, and a dielectric layer is directly formed on the mask material layer 206 subsequently, so that no additional steps are required to remove the mask material layer 206 .
  • an etch guide structure 214 is formed in the central through hole; a dielectric layer 211 covering the substrate 201, the target layer 202, the annular spacer 203 and the etch guide structure 214 is formed.
  • the etch guide structure 214 By forming the etch guide structure 214 in the central through hole in the middle of the annular spacer 203, the etch guide structure 214 in the subsequent process of etching the dielectric layer 211 to form the etch hole, due to the The etching rate of the guide structure 214 is higher than the etching rate of the dielectric layer, so that the bottom of the through hole is easier to move in the direction of the etching guide structure 214, so that the bottom of the etching hole is guided into the central through hole. , and by etching the guiding structure, the formed opening structure can quickly reach the target layer, the etching time for forming the opening structure is shortened, and the complexity of the etching process of the opening structure is simplified, and the opening structure is optimized.
  • the etching process to prevent over-etching of the target layer.
  • the etching hole has the problem of alignment offset and the etching hole is bent, since the etching rate of the etching guide structure 214 is higher than the etching rate of the dielectric layer, the etching plasma gas can be guided correctly Move toward the central through hole, so that the bottom of the etched hole with alignment offset or bending can be guided into the central through hole more accurately and faster by etching the guiding structure, so as to achieve the effect of truncating and straightening, Therefore, the problem that the formed opening structure cannot normally expose the surface of the target layer can be prevented.
  • the etching guide structure 214 is an air gap structure, the top of the etching guide structure is lower than the top surface of the annular gasket, and the air gap structure is composed of air, so the subsequent etching When etching the dielectric layer to form the etching hole, the bottom of the etching hole can be more easily guided into the central through hole.
  • the air gap structure is formed when the dielectric layer 211 is formed.
  • the formation process of the air gap structure is: when the dielectric layer is formed by a chemical vapor deposition process, By adjusting the step coverage ratio of the deposition process, the formed dielectric layer 211 closes the top opening of the central through hole to form an air gap structure (214).
  • the dielectric layer 211 is etched, and an etching hole 215 is formed in the dielectric layer 211 that communicates with the central through hole 213 .
  • the etching hole 215 and the central through hole 213 form an opening structure.
  • the etching guiding structure 214 (refer to FIG. 9 ) is configured to guide the bottom of the etching hole 215 into the central through hole 213 .
  • the sidewall and the bottom dielectric layer of the central through hole 213 are etched and removed (a part of the dielectric layer will also be formed at the bottom of the central through hole 213 when the void structure is formed. sidewall and bottom of the central through hole 213).
  • the method of the present application can guide the curved etching hole 215 to connect with the central through hole 213 .
  • one etching hole 215 and one central through hole 213 are used as examples for description. In other embodiments, there may be multiple etching holes 215 and central through holes 213, one of the etching holes communicates with a corresponding one of the central through holes, or one of the etching holes is connected to a corresponding plurality of The central through hole communicates with each other, and a plurality of the etching holes communicate with a corresponding one of the central through holes.
  • the etch guide structure 214 is a sacrificial layer filling the central via.
  • the material of the sacrificial layer is different from the material of the subsequently formed dielectric layer.
  • the etching rate of the sacrificial layer is greater than the etching rate of the dielectric layer, so When the dielectric layer is subsequently etched to form an etch hole, the bottom of the etch hole can be more easily guided into the central through hole.
  • the material of the sacrificial layer may be one of silicon nitride, silicon oxide, silicon carbonitride, silicon oxynitride, amorphous carbon, polyimide or ultra-low-k material.
  • a second void structure is formed in the sacrificial layer, so that the rate of thickness etching of the etch guide structure can be faster, so that the etching rate of the opening is formed And the efficiency is faster, which is beneficial to prevent over-etching of the target layer.
  • the surface of the sacrificial layer (214) can be lower than the top surface of the annular spacer 203, or flush with the top surface of the annular spacer 203 to keep the final topography good, if the sacrificial layer (214) If the surface is higher than the top surface of the annular spacer 203 , the outer dielectric layer 211 of the annular spacer 203 will be damaged. In the subsequent metal filling process, metal may be filled into the dielectric layer, resulting in leakage.
  • a dielectric layer 211 covering the substrate 201 , the target layer 202 , the annular spacer 203 and the etch guide structure (sacrificial layer) 214 is formed.
  • the dielectric layer 211 is etched, an etching hole 215 is formed in the dielectric layer 211 that communicates with the central through hole 213 , and the etching hole 215 and the central through hole 213 form an opening structure.
  • the etching guide structure (sacrificial layer) 214 is configured to guide the bottom of the etching hole 215 into the central through hole 213 .
  • the etched hole 215 shown in FIG. 14 is an etched hole with a nesting offset, and the method of the present application can guide the etched hole 215 with the nesting offset to connect with the central through hole 213 .
  • the etched hole is an etched hole with no overlay offset.
  • metal is filled in the opening structure to form a contact plug.
  • An embodiment of the present application also provides a method for forming a contact plug. Referring to FIG. 15 ,
  • Conductive material is formed in the contact window structure to form contact plugs 216 .
  • the conductive material may be metal or doped polysilicon.
  • An embodiment of the present application further provides an opening structure, referring to FIG. 10 , FIG. 11 or FIG. 14 , including:
  • a substrate 201 a target layer 202 is formed in the substrate 201, and the substrate 201 exposes the surface of the target layer 202;
  • annular spacer 203 located on the surface of the target layer 202, the annular spacer 203 having a central through hole 213 exposing part of the surface of the target layer 202 in the middle;
  • a dielectric layer 211 covering the substrate 201, the target layer 202 and the annular spacer 203;
  • the etching hole 215 in the dielectric layer 211 communicates with the central through hole 213 .
  • the material of the annular spacer 203 is different from the material of the dielectric layer 211 .
  • the inner diameter of the annular spacer 203 is greater than or equal to the diameter of the etching hole 215 .
  • An embodiment of the present application also provides a contact plug, referring to FIG. 15 , including:
  • a substrate 201 a target layer 202 is formed in the substrate 201, and the substrate 201 exposes the surface of the target layer 202;
  • annular spacer 203 located on the surface of the target layer 202, the annular spacer 203 having a central through hole 213 in the middle exposing part of the surface of the target layer 202 (refer to FIG. 11 );
  • a dielectric layer 211 covering the substrate 201, the target layer 202 and the annular spacer 203;
  • An etching hole 215 located in the dielectric layer 211 and communicating with the central through hole 213 (refer to FIG. 11 );

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

一种开口结构及其形成方法、接触插塞及其形成方法，所述开口结构的形成方法，提供基底，所述基底中形成有目标层，所述基底露出所述目标层的表面；在所述目标层表面上形成环形垫片，所述环形垫片中间具有暴露出目标层部分表面的中央通孔；形成覆盖基底、目标层、环形垫片的介质层；刻蚀所述介质层，在介质层中形成与中央通孔连通的刻蚀孔，所述刻蚀孔和中央通孔构成开口结构。

Description

开口结构及其形成方法、接触插塞及其形成方法
相关申请的交叉引用
[根据细则91更正 12.08.2021]　
本申请基于申请号为202011000653.1、申请日为2020年9月22日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及半导体领域，尤其涉及一种开口结构及其形成方法、接触插塞及其形成方法。
背景技术
随着集成电路向超大规模集成电路发展，集成电路内部的电路密度越来越大，所包含的元件数量也越来越多，这种发展使得晶圆表面无法提供足够的面积来制作所需的互连线。
为了满足元件缩小后的互连线需求，两层及两层以上的多层金属互连线的设计成为超大规模集成电路技术所通常采用的一种方法。目前，不同金属层或者金属层与衬垫层的导通可通过接触插塞实现，现有接触插塞的形成过程一般包括：在基底中形成目标金属层，所述目标金属层与基底的表面齐平；在基底和目标金属层上形成介质层；在介质层中形成暴露出目标金属层表面的刻蚀通孔(或接触窗)；在刻蚀通孔(或接触窗)中填充金属，形成接触插塞。
随着器件的集成度越来越高，所述介质层中形成的刻蚀通孔的深宽比也不断提高，挑战高深宽比的通孔对于刻蚀工艺来说一直是非常大的挑战，形成高深宽比的刻蚀通孔时通常存在通孔偏移、孔接触不良或孔过刻蚀问 题。
发明内容
为解决相关技术问题，本申请实施例提出一种开口结构及其形成方法、接触插塞及其形成方法。
本申请提供了一种开口结构的形成方法，包括：
提供基底，所述基底中形成有目标层，所述基底露出所述目标层的表面；
在所述目标层表面上形成环形垫片，所述环形垫片中间具有暴露出目标层部分表面的中央通孔；
形成覆盖所述基底、目标层、环形垫片的介质层；
刻蚀所述介质层，在所述介质层中形成与中央通孔连通的刻蚀孔，所述刻蚀孔和中央通孔构成开口结构。
可选的，所述中央通孔中还形成有刻蚀导引结构，在刻蚀所述介质层形成与中央通孔连通的刻蚀孔时，对所述刻蚀导引结构的刻蚀速率大于对介质层的刻蚀速率。
可选的，所述刻蚀导引结构为气隙结构或者填充中央通孔的牺牲层，所述刻蚀导引结构的顶部低于所述环形垫片的顶部表面。
可选的，所述气隙结构的形成过程为：在通过化学气相沉积工艺形成所述介质层时，通过调节沉积工艺的台阶覆盖率，使得形成的介质层封闭所述中央通孔的开口结构，形成气隙结构。
可选的，所述牺牲层的材料与所述介质层的材料不相同，在刻蚀所述介质层形成与中央通孔连通的刻蚀孔时，对所述牺牲层的刻蚀速率大于对所述介质层的刻蚀速率。
可选的，所述环形垫片的材料与所述介质层的材料不相同，在刻蚀所述介质层形成与中央通孔连通的刻蚀孔时，对所述介质层的刻蚀速率大于 对所述环形垫片的刻蚀速率。
可选的，所述环形垫片的形成过程包括：在所述基底和目标层部分表面上形成掩膜材料层，所述掩膜材料层中形成有暴露出所述目标层部分表面的通孔；在所述通孔的侧壁和底部表面以及所述掩膜材料层的表面形成垫片材料层；无掩膜刻蚀去除所述掩膜材料层的表面以及通孔底部表面的垫片材料层，在所述通孔的侧壁表面形成环形垫片，环形垫片中间具有中央通孔；去除所述掩膜材料层。
可选的，所述环形垫片的形状为圆环状、椭圆环状或者长方环状。
可选的，所述环形垫片的内径大于或等于所述刻蚀孔的直径。
可选的，一个所述刻蚀孔与对应的一个中央通孔连通，或者一个所述刻蚀孔与对应的多个中央通孔连通，多个所述刻蚀孔与对应的一个所述中央通孔连通。
本申请还提供了一种接触插塞的形成方法，包括：
采用前述所述的方法形成开口结构，将所述开口结构作为接触窗结构；
在所述接触窗结构中形成导电材料，形成接触插塞。
本申请还提供了一种开口结构，包括：
基底，所述基底中形成有目标层，所述基底露出所述目标层的表面；
位于所述目标层表面上的环形垫片，所述环形垫片中间具有暴露出目标层部分表面的中央通孔；
覆盖所述基底、目标层和环形垫片的介质层；
位于所述介质层中与中央通孔连通的刻蚀孔。
可选的，所述环形垫片的材料与所述介质层的材料不相同。
可选的，所述环形垫片的内径大于或等于所述刻蚀孔的直径。
本申请还提供了一种接触插塞，包括：
基底，所述基底中形成有目标层，所述基底露出所述目标层的表面；
位于所述目标层表面上的环形垫片，所述环形垫片中间具有暴露出目标层部分表面的中央通孔；
覆盖所述基底、目标层和环形垫片的介质层；
位于所述介质层中与中央通孔连通的刻蚀孔；
位于所述刻蚀孔和中央通孔中的接触插塞。
与现有技术相比，本申请技术方案具有以下优点：
本申请的开口结构的形成方法，提供基底，所述基底中形成有目标层，所述基底露出所述目标层的表面；在所述目标层表面上形成环形垫片，所述环形垫片中间具有暴露出目标层部分表面的中央通孔；形成覆盖所述基底、目标层、环形垫片的介质层；刻蚀所述介质层，在所述介质层中形成与中央通孔连通的刻蚀孔，所述刻蚀孔和中央通孔构成开口结构。通过形成环形垫片，在介质层中形成刻蚀孔时，当刻蚀孔存在弯曲或者位置偏移时，所述环形垫片能防止刻蚀孔底部的侧向刻蚀，使得刻蚀孔的底部被导引至环形垫片之间的中央通孔中，因而使得刻蚀孔底部被纠正至正确的位置，使得形成的开口结构能正常的暴露目标金属层表面，此外，环形垫片的存在，能防止后续开口结构中形成接触插塞带来的金属扩散而导致的漏电等异常。
进一步，通过在环形垫片中间的中央通孔中形成刻蚀导引结构，所述刻蚀导引结构在后续刻蚀所述介质层形成刻蚀孔的过程之中，由于对刻蚀导引结构的刻蚀速率大于对介质层的刻蚀速率，因而使得通孔的底部更容易向刻蚀导引结构的方向移动，使得所述刻蚀孔的底部引导至所述中央通孔中，并且通过刻蚀导引结构能使得形成的开口结构能快速的到达目标层，整个形成开口结构的刻蚀时间减短，并且使得简化了开口结构的刻蚀工艺的复杂度，优化了开口结构的刻蚀工艺，从而防止对目标层的过刻蚀。此外，当刻蚀孔存在对准偏移以及刻蚀孔存在弯曲的问题时，由于对刻蚀导 引结构的刻蚀速率大于对介质层的刻蚀速率，能正确导引刻蚀等离子气体往中央通孔方向移动，从而通过刻蚀导引结构可以使得存在对准偏移或弯曲的刻蚀孔的底部更准确和更快的被导引至中央通孔中，达到截弯取直的效果，从而能防止形成的开口结构不能正常暴露目标层表面的问题。
进一步，所述环形垫片的形成过程包括：在所述基底和目标层部分表面上形成掩膜材料层，所述掩膜材料层中形成有暴露出所述目标层部分表面的通孔；在所述通孔的侧壁和底部表面以及所述掩膜材料层的表面形成垫片材料层；无掩膜刻蚀去除所述掩膜材料层的表面以及通孔底部表面的垫片材料层，在所述通孔的侧壁表面形成环形垫片。这样方法形成的环形垫片的尺寸和形状的精度较高，并具有较高的侧壁形貌。
进一步，所述刻蚀导引结构为气隙结构，气隙结构成分为空气，因而后续刻蚀介质层形成刻蚀孔时，能更容易的将所述刻蚀孔的底部引导至所述中央通孔中。
进一步，所述刻蚀导引结构为填充中央通孔的牺牲层，所述牺牲层的材料与后续形成的介质层材料不相同，在刻蚀所述介质层形成刻蚀孔时，对所述牺牲层的刻蚀速率大于对所述介质层的刻蚀速率，因而后续刻蚀介质层形成刻蚀孔时，能更容易的将所述刻蚀孔的底部引导至所述中央通孔中。
本申请的开口结构，通过环形垫片，在介质层中形成刻蚀孔时，当刻蚀孔存在弯曲或者位置偏移时，所述环形垫片能防止刻蚀孔底部的侧向刻蚀，使得刻蚀孔的底部被导引至环形垫片之间的中央通孔中，因而使得刻蚀孔底部被纠正至正确的位置，使得形成的开口结构能正常的暴露目标金属层表面，此外，环形垫片的存在，能防止后续开口结构中形成接触插塞带来的金属扩散而导致的漏电等异常。
本申请的接触插塞以及形成方法，通过环形垫片，在介质层中形成刻 蚀孔时，当刻蚀孔存在弯曲或者位置偏移时，所述环形垫片能防止刻蚀孔底部的侧向刻蚀，使得刻蚀孔的底部被导引至环形垫片之间的中央通孔中，因而使得刻蚀孔底部被纠正至正确的位置，使得形成的开口结构能正常的暴露目标金属层表面，使得开口结构中形成的接触插塞能正常与所述目标金属层连接，此外，环形垫片的存在，能防止后续开口结构中形成接触插塞带来的金属扩散而导致的漏电等异常。
附图说明
图1为现有形成的通孔的结构示意图；
图2-图14为本申请实施例开口结构的形成过程的剖面结构示意图；
图15为本申请实施例接触插塞形成过程的剖面结构示意图。
具体实施方式
如背景技术所言，形成高深宽比的刻蚀通孔时通常存在通孔偏移问题。
研究发现，参考图1，由于晶圆边缘的磁场偏压较弱所以容易造成刻蚀通孔104弯曲，使得刻蚀通孔的底部会偏离正常位置，因而不能正常的暴露目标金属层表面。或者，由于套刻工艺的偏差，使得形成的刻蚀通孔偏离正常的位置。
为此，本申请提供了一种开口结构及其形成方法、接触插塞及其形成方法，所述开口结构的形成方法，提供基底，所述基底中形成有目标层，所述基底露出所述目标层的表面；在所述目标层表面上形成环形垫片，所述环形垫片中间具有暴露出目标层部分表面的中央通孔；形成覆盖所述基底、目标层、环形垫片的介质层；刻蚀所述介质层，在所述介质层中形成与中央通孔连通的刻蚀孔，所述刻蚀孔和中央通孔构成开口结构。通过形成环形垫片，在介质层中形成刻蚀孔时，当刻蚀孔存在弯曲或者位置偏移时，所述环形垫片能防止刻蚀孔底部的侧向刻蚀，使得刻蚀孔的底部被导 引至环形垫片之间的中央通孔中，因而使得刻蚀孔底部被纠正至正确的位置，使得形成的开口结构能正常的暴露目标金属层表面，此外，环形垫片的存在，能防止后续开口结构中形成接触插塞带来的金属扩散而导致的漏电等异常。
为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合附图对本申请的具体实施方式做详细的说明。在详述本申请实施例时，为便于说明，示意图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本申请的保护范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
参考图2，提供基底201，所述基底201中形成有目标层202，所述基底201露出所述目标层202的表面。
在一实施例中，所述基底201可以为半导体衬底，所述目标层202可以为位于半导体衬底中的掺杂区(比如掺杂有N型杂质离子或掺杂有P型杂质离子的区域)或者位于半导体衬底中的金属硅化物区(比如硅化镍区或硅化钴区)。所述半导体衬底的材料可以为硅(Si)、锗(Ge)、或硅锗(GeSi)、碳化硅(SiC)；也可以是绝缘体上硅(SOI)，绝缘体上锗(GOI)；或者还可以为其它的材料，例如砷化镓等Ⅲ-Ⅴ族化合物。
在其他实施例中，所述基底201可以包括半导体衬底和位于半导体衬底中的层间介质层，所述目标层202位于层间介质层中。所述层间介质层可以为单层或多层堆叠结构，所述目标层202可以为金属层，所述金属层可以与下层介质层中形成的导电结构(比如导电插塞)连接。
所述目标层202的表面可以与所述基底201的表面齐平，或者略高于所述基底102的表面。
所述基底201中形成目标层202可以为一个或多个(≥2个)，所述目标层202为多个时，相邻目标层之间是分立的，本实施例中仅以所述基底 201中具有一个目标层202作为示例进行说明。
所述目标层202上后续需要形成环形垫片。在一实施例中，继续参考图2，在所述基底201和目标层202部分表面上形成掩膜材料层206，所述掩膜材料层206中形成有暴露出所述目标层202部分表面的通孔207。
所述掩膜材料层206的材料可以为光刻胶、氮化硅、氧化硅、碳氮化硅、氮氧化硅、多晶硅、无定型硅、无定型碳、低K介质材料中一种或几种。所述掩膜材料层206的形成工艺可以为化学气相沉积工艺。
在一实施例中，所述掩膜材料层206的材料为光刻胶，通过曝光和显影工艺在所述掩膜材料层206中形成通孔207。所述掩膜材料层206为其他材料时，可以通过，可以通过刻蚀工艺在所述掩膜材料层206中形成通孔207。
所述通孔207的形状和位置限定后续形成的环形垫片的形状和位置。
参考图3，在所述通孔207的侧壁和底部表面以及所述掩膜材料层206的表面形成垫片材料层208。
所述垫片材料层208后续配置为形成环形垫片。所述垫片材料层208的材料与后续形成的介质层的材料不相同，后续在介质层中形成刻蚀孔时，使得介质层相对于所述环形垫片具有高的刻蚀选择比，从而使得环形结构能有效的防止刻蚀介质层形成通孔时的侧向刻蚀，将刻蚀孔的底部更有效的导引至所述中央通孔中。
所述环形垫片材料层208的材料可以为氮化硅、氧化硅、碳氮化硅、氮氧化硅中的一种或几种。本实施例中，所述环形垫片材料层208的材料为氮化硅，形成所述环形垫片材料层采用化学气相沉积工艺。
所述垫片材料层208的厚度决定后续形成的环形垫片的宽度。在一实施例中，所述垫片材料层208的厚度为5nm-5um。
参考图4，无掩膜刻蚀去除所述掩膜材料层206的表面以及通孔底部表 面的垫片材料层，在所述通孔的侧壁表面形成环形垫片203，环形垫片203中间形成中央通孔213。
通过形成环形垫片203，后续在介质层中形成刻蚀孔时，当刻蚀孔存在弯曲或者位置偏移时，所述环形垫片能防止刻蚀孔底部的侧向刻蚀，使得刻蚀孔的底部被导引至环形垫片之间的中央通孔中，因而使得刻蚀孔底部被纠正至正确的位置，使得形成的开口结构能正常的暴露目标金属层表面，此外，环形垫片的存在，能防止后续开口结构中形成接触插塞带来的金属扩散而导致的漏电等异常。
刻蚀所述垫片材料层采用各项异性的干法刻蚀工艺，可以为等离子体刻蚀工艺。
参考图5，在形成环形垫片203后去除所述掩膜材料层206，去除所述掩膜材料层206可以采用湿法或干法刻蚀工艺。
参考图6和图7，图6和图7为前述形成的环形垫片203的俯视结构示意图，图6中所示的环形垫片203的形状为圆环形，图7中所示的环形垫片203的形状为椭圆环形。在其他实施例中，所述环形垫片203的形状也可以为长方环状。所述环形垫片203的内径可以大于或等于后续介质层中形成的刻蚀孔的直径，当刻蚀孔存在弯曲时，使得刻蚀孔的底部更容易被导引至环形垫片203中间的中央通孔中。在其他实施例中，所述环形垫片的外径可以小于所述后续介质层中形成的刻蚀孔的直径。
在另一实施例中，参考图8，当所述掩膜材料层206为隔离材料，可以配置为器件之间的电学隔离时，比如所述掩膜材料层与后续形成的介质层的材料相同时，在形成环形垫片203后，保留所述掩膜材料层206，后续在所述掩膜材料层206上直接形成介质层，从而无需额外的步骤去除所述掩膜材料层206。
参考图9，在所述中央通孔中形成刻蚀导引结构214；形成覆盖所述基 底201、目标层202、环形垫片203和刻蚀导引结构214的介质层211。
通过在环形垫片203中间的中央通孔中形成刻蚀导引结构214，所述刻蚀导引结构214在后续刻蚀所述介质层211形成刻蚀孔的过程之中，由于对刻蚀导引结构214的刻蚀速率大于对介质层的刻蚀速率，因而使得通孔的底部更容易向刻蚀导引结构214的方向移动，使得所述刻蚀孔的底部引导至所述中央通孔中，并且通过刻蚀导引结构能使得形成的开口结构能快速的到达目标层，整个形成开口结构的刻蚀时间减短，并且使得简化了开口结构的刻蚀工艺的复杂度，优化了开口结构的刻蚀工艺，从而防止对目标层的过刻蚀。此外，当刻蚀孔存在对准偏移以及刻蚀孔存在弯曲的问题时，由于对刻蚀导引结构214的刻蚀速率大于对介质层的刻蚀速率，能正确导引刻蚀等离子气体往中央通孔方向移动，从而通过刻蚀导引结构可以使得存在对准偏移或弯曲的刻蚀孔的底部更准确和更快的被导引至中央通孔中，达到截弯取直的效果，从而能防止形成的开口结构不能正常暴露目标层表面的问题。
本实施例中，所述刻蚀导引结构214为气隙结构，所述刻蚀导引结构的顶部低于所述环形垫片的顶部表面，所述气隙结构成分为空气，因而后续刻蚀介质层形成刻蚀孔时，能更容易的将所述刻蚀孔的底部引导至所述中央通孔中。
在一实施例中，所述气隙结构在形成介质层211时形成，在一具体的实施例中，所述气隙结构的形成过程为：在通过化学气相沉积工艺形成所述介质层时，通过调节沉积工艺的台阶覆盖率，使得形成的介质层211封闭所述中央通孔的顶部开口，形成气隙结构(214)。
参考图10，刻蚀所述介质层211，在所述介质层211中形成与中央通孔213连通的刻蚀孔215，所述刻蚀孔215和中央通孔213构成开口结构，在刻蚀所述介质层211形成刻蚀孔215的过程之中，所述刻蚀导引结构214 (参考图9)配置为将所述刻蚀孔215的底部引导至所述中央通孔213中。
在刻蚀介质层211的过程中，当形成的刻蚀孔215底部与空气隙结构连通时，刻蚀去除中央通孔213侧壁和底部的介质层(形成空隙结构时部分介质层也会形成在中央通孔213的侧壁和底部)。
在一实施例中，在刻蚀介质层211时，当形成的刻蚀孔215存在弯曲时，参考图11，本申请方法能将所述弯曲的刻蚀孔215引导至与中央通孔213连接。
需要说明的是，前述实施例中，均是以一个刻蚀孔215和一个中央通孔213作为示例进行说明。在其他实施例中，所述形成的刻蚀孔215和中央通孔213均可以为多个，一个所述刻蚀孔与对应的一个中央通孔连通，或者一个所述刻蚀孔与对应的多个中央通孔连通，多个所述刻蚀孔与对应的一个所述中央通孔连通。
在本申请另一实施例中，参考图12，所述刻蚀导引结构214为填充中央通孔的牺牲层。
所述牺牲层的材料与后续形成的介质层材料不相同，在刻蚀所述介质层形成刻蚀孔时，对所述牺牲层的刻蚀速率大于对所述介质层的刻蚀速率，因而后续刻蚀介质层形成刻蚀孔时，能更容易的将所述刻蚀孔的底部引导至所述中央通孔中。
在一实施例中，所述牺牲层的材料可以为氮化硅、氧化硅、碳氮化硅、氮氧化硅、无定型碳、聚酰亚胺或超低k材料中的一种。
在一实施例中，在形成牺牲层时，在所述牺牲层中形成第二空隙结构，使得厚度刻蚀所述刻蚀导引结构时的速率可以更快，使得形成开口时的刻蚀速率和效率较快，有利于防止对目标层的过刻蚀。
所述牺牲层(214)的表面可以低于所述环形垫片203顶部表面，或者与所述环形垫片203顶部表面齐平，以保持最终形貌良好，如果所述牺牲 层(214)的表面高于所述环形垫片203顶部表面，则会导致环形垫片203外部介质层211受损，在后续填充金属工艺中，可能金属填充至介质层中，导致漏电。
参考图13，形成覆盖所述基底201、目标层202、环形垫片203和刻蚀导引结构(牺牲层)214的介质层211。
参考图14，刻蚀所述介质层211，在所述介质层211中形成与中央通孔213连通的刻蚀孔215，所述刻蚀孔215和中央通孔213构成开口结构，在刻蚀所述介质层211形成刻蚀孔215的过程之中，所述刻蚀导引结构(牺牲层)214配置为将所述刻蚀孔215的底部引导至所述中央通孔213中。
图14中所示的刻蚀孔215为存在套刻偏移的刻蚀孔，本申请方法能将所述套刻偏移的刻蚀孔215引导至与中央通孔213连接。在其他实施例中，所述所述刻蚀孔为不存在套刻偏移的刻蚀孔。
在一实施例中，在形成前述所述的开口结构后，在所述开口结构中填充金属，形成接触插塞。
本申请一实施例还提供了一种接触插塞的形成方法，参考图15，
采用前述所述的方法形成开口结构，将所述开口结构作为接触窗结构；
在所述接触窗结构中形成导电材料，形成接触插塞216。
所述导电材料可以为金属或掺杂的多晶硅。
需要说明的是，本实施例中(接触插塞的形成方法)与前述实施例中(开口结构的形成过程)中相似或相同结构的限定或描述，在本实施例中不再限定，具体请参考前述实施例相应部分的限定或描述。
本申请一实施例还提供了一种开口结构，参考图10，图11或图14，包括：
基底201，所述基底201中形成有目标层202，所述基底201露出所述目标层202的表面；
位于所述目标层202表面上的环形垫片203，所述环形垫片203中间具有暴露出目标层202部分表面的中央通孔213；
覆盖所述基底201、目标层202和环形垫片203的介质层211；
位于所述介质层211中与中央通孔213连通的刻蚀孔215。
在一实施例中，所述环形垫片203的材料与所述介质层211的材料不相同。
在一实施例中，所述环形垫片203的内径大于或等于所述刻蚀孔215的直径。
需要说明的是，本实施例中(开口结构)与前述实施例中(开口结构的形成过程)中相似或相同结构的限定或描述，在本实施例中不再限定，具体请参考前述实施例相应部分的限定或描述。
本申请一实施例还提供了一种接触插塞，参考图15，包括：
基底201，所述基底201中形成有目标层202，所述基底201露出所述目标层202的表面；
位于所述目标层202表面上的环形垫片203，所述环形垫片203中间具有暴露出目标层202部分表面的中央通孔213(参考图11)；
覆盖所述基底201、目标层202和环形垫片203的介质层211；
位于所述介质层211中与中央通孔213连通的刻蚀孔215(参考图11)；
位于所述刻蚀孔和中央通孔中的接触插塞216。
需要说明的是，本实施例中(开接触插塞)与前述实施例中(开口结构的形成过程)中相似或相同结构的限定或描述，在本实施例中不再限定，具体请参考前述实施例相应部分的限定或描述。
本申请虽然已以较佳实施例公开如上，但其并不是用来限定本申请，任何本领域技术人员在不脱离本申请的精神和范围内，都可以利用上述揭示的方法和技术内容对本申请技术方案做出可能的变动和修改，因此，凡 是未脱离本申请技术方案的内容，依据本申请的技术实质对以上实施例所作的任何简单修改、等同变化及修饰，均属于本申请技术方案的保护范围。

Claims (15)

  1. 一种开口结构的形成方法，包括：
    提供基底，所述基底中形成有目标层，所述基底露出所述目标层的表面；
    在所述目标层表面上形成环形垫片，所述环形垫片中间具有暴露出目标层部分表面的中央通孔；
    形成覆盖所述基底、目标层、环形垫片的介质层；
    刻蚀所述介质层，在所述介质层中形成与中央通孔连通的刻蚀孔，所述刻蚀孔和中央通孔构成开口结构。
  2. 如权利要求1所述的开口结构的形成方法，其中，所述中央通孔中还形成有刻蚀导引结构，在刻蚀所述介质层形成与中央通孔连通的刻蚀孔时，对所述刻蚀导引结构的刻蚀速率大于对介质层的刻蚀速率。
  3. 如权利要求2所述的开口结构的形成方法，其中，所述刻蚀导引结构为气隙结构或者填充中央通孔的牺牲层，所述刻蚀导引结构的顶部低于所述环形垫片的顶部表面。
  4. 如权利要求3所述的开口结构的形成方法，其中，所述气隙结构的形成过程为：在通过化学气相沉积工艺形成所述介质层时，通过调节沉积工艺的台阶覆盖率，使得形成的介质层封闭所述中央通孔的开口结构，形成气隙结构。
  5. 如权利要求3所述的开口结构的形成方法，其中，所述牺牲层的材料与所述介质层的材料不相同，在刻蚀所述介质层形成与中央通孔连通的刻蚀孔时，对所述牺牲层的刻蚀速率大于对所述介质层的刻蚀速率。
  6. 如权利要求1所述的开口结构的形成方法，其中，所述环形垫片的材料与所述介质层的材料不相同，在刻蚀所述介质层形成与中央通孔连通的刻蚀孔时，对所述介质层的刻蚀速率大于对所述环形垫片的刻蚀 速率。
  7. 如权利要求1或6所述的开口结构的形成方法，其中，所述环形垫片的形成过程包括：在所述基底和目标层部分表面上形成掩膜材料层，所述掩膜材料层中形成有暴露出所述目标层部分表面的通孔；在所述通孔的侧壁和底部表面以及所述掩膜材料层的表面形成垫片材料层；无掩膜刻蚀去除所述掩膜材料层的表面以及通孔底部表面的垫片材料层，在所述通孔的侧壁表面形成环形垫片，环形垫片中间具有中央通孔；去除所述掩膜材料层。
  8. 如权利要求1所述的开口结构的形成方法，其中，所述环形垫片的形状为圆环状、椭圆环状或者长方环状。
  9. 如权利要求1或7所述的开口结构的形成方法，其中，所述环形垫片的内径大于或等于所述刻蚀孔的直径。
  10. 如权利要求1所述的开口结构的形成方法，其中，一个所述刻蚀孔与对应的一个中央通孔连通，或者一个所述刻蚀孔与对应的多个中央通孔连通，多个所述刻蚀孔与对应的一个所述中央通孔连通。
  11. 一种接触插塞的形成方法，包括：
    采用权利要求1-10任一项所述的方法形成开口结构，将所述开口结构作为接触窗结构；
    在所述接触窗结构中形成导电材料，形成接触插塞。
  12. 一种开口结构，包括：
    基底，所述基底中形成有目标层，所述基底露出所述目标层的表面；
    位于所述目标层表面上的环形垫片，所述环形垫片中间具有暴露出目标层部分表面的中央通孔；
    覆盖所述基底、目标层和环形垫片的介质层；
    位于所述介质层中与中央通孔连通的刻蚀孔，所述刻蚀孔和中央通 孔构成开口结构。
  13. 如权利要求12所述的开口结构，其中，所述环形垫片的材料与所述介质层的材料不相同。
  14. 如权利要求12所述的开口结构，其中，所述环形垫片的内径大于或等于所述刻蚀孔的直径。
  15. 一种接触插塞，包括：
    基底，所述基底中形成有目标层，所述基底露出所述目标层的表面；
    位于所述目标层表面上的环形垫片，所述环形垫片中间具有暴露出目标层部分表面的中央通孔；
    覆盖所述基底、目标层和环形垫片的介质层；
    位于所述介质层中与中央通孔连通的刻蚀孔；
    位于所述刻蚀孔和中央通孔中的接触插塞。
PCT/CN2021/100699 2020-09-22 2021-06-17 开口结构及其形成方法、接触插塞及其形成方法 WO2022062494A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/578,509 US20220139721A1 (en) 2020-09-22 2022-01-19 Opening structure and forming method thereof, contact plug structure and forming method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202011000653.1 2020-09-22
CN202011000653.1A CN114256135A (zh) 2020-09-22 2020-09-22 开口结构及其形成方法、接触插塞及其形成方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/578,509 Continuation US20220139721A1 (en) 2020-09-22 2022-01-19 Opening structure and forming method thereof, contact plug structure and forming method thereof

Publications (1)

Publication Number Publication Date
WO2022062494A1 true WO2022062494A1 (zh) 2022-03-31

Family

ID=80788395

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/100699 WO2022062494A1 (zh) 2020-09-22 2021-06-17 开口结构及其形成方法、接触插塞及其形成方法

Country Status (3)

Country Link
US (1) US20220139721A1 (zh)
CN (1) CN114256135A (zh)
WO (1) WO2022062494A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5285110A (en) * 1991-03-20 1994-02-08 Samsung Electronicw Co., Ltd. Interconnection structure in semiconductor device
US20040197986A1 (en) * 2003-04-07 2004-10-07 Nanya Technology Corporation Method of filling bit line contact via
KR20080093738A (ko) * 2007-04-18 2008-10-22 주식회사 하이닉스반도체 반도체 소자의 형성 방법
CN104425567A (zh) * 2013-08-23 2015-03-18 台湾积体电路制造股份有限公司 提高钝化完整性的系统和方法
CN108122845A (zh) * 2016-11-29 2018-06-05 台湾积体电路制造股份有限公司 接触结构制造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI225671B (en) * 2003-04-07 2004-12-21 Nanya Technology Corp Method of forming bit line contact via
KR100831250B1 (ko) * 2007-08-10 2008-05-22 주식회사 동부하이텍 반도체 소자 제조 방법
US9368395B1 (en) * 2014-05-06 2016-06-14 Globalfoundries Inc. Self-aligned via and air gap
CN105489490B (zh) * 2014-09-17 2020-03-17 联华电子股份有限公司 半导体元件及其制作方法
US11004733B2 (en) * 2018-06-29 2021-05-11 Taiwan Semiconductor Manufacturing Company, Ltd. Protection structures for bonded wafers
EP4002437B1 (en) * 2020-09-22 2023-08-02 Changxin Memory Technologies, Inc. Method of forming a contact window structure
CN114256417A (zh) * 2020-09-22 2022-03-29 长鑫存储技术有限公司 电容结构及其形成方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5285110A (en) * 1991-03-20 1994-02-08 Samsung Electronicw Co., Ltd. Interconnection structure in semiconductor device
US20040197986A1 (en) * 2003-04-07 2004-10-07 Nanya Technology Corporation Method of filling bit line contact via
KR20080093738A (ko) * 2007-04-18 2008-10-22 주식회사 하이닉스반도체 반도체 소자의 형성 방법
CN104425567A (zh) * 2013-08-23 2015-03-18 台湾积体电路制造股份有限公司 提高钝化完整性的系统和方法
CN108122845A (zh) * 2016-11-29 2018-06-05 台湾积体电路制造股份有限公司 接触结构制造方法

Also Published As

Publication number Publication date
US20220139721A1 (en) 2022-05-05
CN114256135A (zh) 2022-03-29

Similar Documents

Publication Publication Date Title
CN106469675B (zh) 用于互连的结构和方法
US8673544B2 (en) Method of forming openings
US10242881B2 (en) Self-aligned single dummy fin cut with tight pitch
JP4057083B2 (ja) 半導体集積回路の製造方法
TW202029339A (zh) 積體電路結構及其形成方法
TW202114117A (zh) 半導體結構
US6245621B1 (en) Semiconductor device manufacturing method
TW202310285A (zh) 半導體裝置
US9214392B1 (en) Method of forming contact hole and semiconductor structure with contact plug
WO2022062494A1 (zh) 开口结构及其形成方法、接触插塞及其形成方法
US12002748B2 (en) Contact window structure, metal plug and forming method thereof, and semiconductor structure
US11626289B2 (en) Semiconductor structure and method for forming the same
WO2022062485A1 (zh) 接触窗结构、金属插塞及其形成方法、半导体结构
JPH07161806A (ja) 半導体装置の製造方法
JP2007081347A (ja) 半導体装置の製造方法
JP2001077189A (ja) 半導体装置の製造方法
JP4257357B2 (ja) 半導体装置の製造方法
WO2022062486A1 (zh) 接触窗结构及其形成方法
CN110896051B (zh) 一种半导体器件的制造方法和半导体器件
CN114446770A (zh) 半导体结构及其形成方法
KR20090097426A (ko) 반도체 소자의 콘택 형성 방법
CN118098936A (zh) 半导体结构的制作方法、掩膜结构及半导体结构
CN114582797A (zh) 一种半导体器件的制造方法
KR20020049373A (ko) 반도체 소자의 제조방법
KR100277861B1 (ko) 반도체 소자의 플러그 형성방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21870876

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21870876

Country of ref document: EP

Kind code of ref document: A1