CN104900521B - 鳍式场效应晶体管及其形成方法 - Google Patents

鳍式场效应晶体管及其形成方法 Download PDF

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CN104900521B
CN104900521B CN201410077191.1A CN201410077191A CN104900521B CN 104900521 B CN104900521 B CN 104900521B CN 201410077191 A CN201410077191 A CN 201410077191A CN 104900521 B CN104900521 B CN 104900521B
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layer
buffer layer
fin
semiconductor substrate
effect transistor
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CN104900521A (zh
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肖德元
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to US14/548,736 priority patent/US9425101B2/en
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Priority to US15/218,631 priority patent/US9608115B2/en
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Abstract

一种鳍式场效应晶体管及其形成方法，所述鳍式场效应晶体管的形成方法包括：提供半导体衬底；在所述半导体衬底内形成若干凹槽；在所述半导体衬底表面形成缓冲层，所述缓冲层填充满凹槽并覆盖半导体衬底表面；刻蚀部分厚度的缓冲层，形成鳍部；在鳍部周围的缓冲层上形成绝缘层，所述绝缘层的表面低于鳍部的顶部表面；在鳍部表面形成沟道层；在部分绝缘层表面和部分沟道层表面形成横跨鳍部的栅极结构；在栅极结构两侧的沟道层内形成源漏区。上述方法可以提高形成的鳍式场效应晶体管的性能。

Description

鳍式场效应晶体管及其形成方法
技术领域
本发明涉及半导体技术领域，特别涉及一种鳍式场效应晶体管及其形成方法。
背景技术
随着半导体工艺技术的不断发展，工艺节点逐渐减小，后栅（gate-last）工艺得到了广泛应用，以获得理想的阈值电压，改善器件性能。但是当器件的特征尺寸进一步下降时，即使采用后栅工艺，常规的MOS场效应管的结构也已经无法满足对器件性能的需求，多栅器件作为常规器件的替代得到了广泛的关注。鳍式场效应晶体管是一种常见的多栅器件，得到了广泛的应用。
另一方面，随着硅基器件的尺寸缩小，受到硅材料自身的性质限制，硅基器件的性能无法再得到有效提高。通过高性能的材料与硅材料结合，例如在硅衬底表面形成III-V族材料层作为晶体管的沟道材料，可以提供更好的载流子迁移率以及更高的驱动电流，可以进一步提高半导体器件的性能。与采用硅材料作为沟道层的鳍式场效应晶体管相比，采用III-V族材料作为沟道层的鳍式场效应晶体管的具有更高的性能。
但是，由于III-V材料与硅衬底的晶格相差较大，在硅衬底上直接外延形成III-V族材料层，会在所述III-V族材料层内产生较高密度的缺陷，从而影响形成的鳍式场效应晶体管的性能。
发明内容
本发明解决的问题是提供一种鳍式场效应晶体管及其形成方法，提高形成的鳍式场效应晶体管的性能。
为解决上述问题，本发明提供一种鳍式场效应晶体管的形成方法，包括：提供半导体衬底；在所述半导体衬底内形成若干凹槽；在所述半导体衬底表面形成缓冲层，所述缓冲层填充满凹槽并覆盖半导体衬底表面；刻蚀部分厚度的缓冲层，形成鳍部；在鳍部周围的缓冲层上形成绝缘层，所述绝缘层的表面低于鳍部的顶部表面；在鳍部表面形成沟道层；在部分绝缘层表面和部分沟道层表面形成横跨鳍部的栅极结构；在栅极结构两侧的沟道层内形成源漏区。
可选的，所述凹槽的顶部宽度为5nm～500nm。
可选的，相邻凹槽之间的间距为10nm～1000nm。
可选的，所述凹槽的深度为8nm～1000nm。
可选的，形成所述凹槽的方法包括：在半导体衬底表面形成具有若干开口的掩膜层，沿所述开口刻蚀半导体衬底，在所述半导体衬底内形成若干凹槽。
可选的，沿所述开口刻蚀半导体衬底的方法为湿法刻蚀工艺或干法刻蚀工艺。
可选的，沿所述开口刻蚀半导体衬底的方法包括：采用干法刻蚀工艺对半导体衬底进行第一刻蚀，然后再采用湿法刻蚀工艺对半导体衬底进行第二刻蚀，最终形成所述凹槽。
可选的，所述干法刻蚀工艺采用的刻蚀气体为HBr和Cl2的混合气体作为刻蚀气体，O2作为缓冲气体，其中HBr的流量为50sccm～1000sccm，Cl2的流量为50sccm～1000sccm，O2的流量为5sccm～20sccm，压强为5mTorr～50mTorr，功率为400W～750W，O2的气体流量为5sccm～20sccm，温度为40℃～80℃，偏置电压为100V～250V；所述湿法刻蚀工艺采用的刻蚀溶液为四甲基氢氧化铵溶液，温度为30℃～80℃。
可选的，所述凹槽的侧壁为Σ形。
可选的，所述缓冲层包括第一缓冲层和位于第一缓冲层表面的第二缓冲层，所述第一缓冲层填充满凹槽并覆盖半导体衬底的表面。
可选的，位于半导体衬底表面的第一缓冲层的厚度为10nm～500nm，第二缓冲层的厚度为10nm～500nm。
可选的，所述第一缓冲层的材料和第二缓冲层的材料均半导体材料，所述半导体衬底的晶格常数、第一缓冲层的晶格常数、第二缓冲层的晶格常数、沟道层的晶格常数逐渐增大或逐渐减小。
可选的，所述第一缓冲层的材料包括锗硅，第二缓冲层的材料包括铟铝砷化合物或磷化铟。
可选的，以第一缓冲层表面作为停止层，刻蚀所述第二缓冲层形成鳍部。
可选的，对所述第一缓冲层表面进行氧化处理，形成所述绝缘层，所述绝缘层的厚度为
可选的，采用选择性外延工艺在所述鳍部表面形成沟道层，所述沟道层的厚度为1nm～10nm，所述沟道层的材料包括铟镓砷、铟镓碲或碲化镓。
为解决上述问题，本发明的技术方案还提供一种鳍式场效应晶体管，包括：半导体衬底，所述半导体衬底内形成有若干凹槽；位于所述半导体衬底表面的第一缓冲层，所述第一缓冲层填充满凹槽并覆盖半导体衬底表面；位于第一缓冲层表面的鳍部；位于鳍部周围的第一缓冲层表面的绝缘层，所述绝缘层的表面低于鳍部的顶部表面位于鳍部表面的沟道层；位于部分绝缘层表面和部分沟道层表面的横跨鳍部的栅极结构；位于栅极结构两侧的沟道层内的源漏区。
可选的，所述凹槽的顶部宽度为5nm～500nm，相邻凹槽之间的间距为10nm～1000nm，所述凹槽的深度为8nm～1000nm。
可选的，所述第一缓冲层的材料和鳍部的材料均半导体材料，所述半导体衬底的晶格常数、第一缓冲层的晶格常数、鳍部的晶格常数、沟道层的晶格常数逐渐增大或逐渐减小。
可选的，所述第一缓冲层的材料包括锗硅，鳍部的材料包括铟铝砷化合物或磷化铟。
与现有技术相比，本发明的技术方案具有以下优点：
本发明的技术方案，在半导体衬底内形成若干凹槽后，再在所述半导体衬底表面形成缓冲层，使所述缓冲层填充满凹槽并覆盖半导体衬底的表面，然后刻蚀部分厚度的缓冲层形成鳍部，再在鳍部表面形成沟道层。所述缓冲层在外延生长的过程中，沿凹槽的内壁表面以及半导体衬底的表面生长。由于在所述半导体衬底内形成了若干凹槽，所述凹槽具有侧壁以及底部表面，缓冲层的材料同时沿凹槽的侧壁及底部表面生长，使得所述缓冲层材料同时具有横向及纵向的生长分量。所述缓冲层材料在生长过程中会产生缺陷，并且不同生长方向的缓冲层材料内具有不同方向的缺陷。在所述凹槽内，随着缓冲层材料的厚度增加，不同生长方向上的缓冲层材料发生闭合，使得缓冲层材料内的不同方向的位错缺陷之间互相抵消使缓冲层内的缺陷数量减少，随着不同方向上闭合的缓冲层材料的厚度的增加，缺陷的数量也会逐渐降低，使得最终形成的缓冲层表面的缺陷较少，从而刻蚀部分厚度的缓冲层形成的鳍部表面的缺陷也较少，可以降低在鳍部表面形成的沟道层内的缺陷，进而提高最终形成的鳍式场效应晶体管的性能。
进一步的，所述凹槽的侧壁为Σ形，可以使所述凹槽具有更多不同方向的侧壁表面，从而在半导体衬底上形成缓冲层时，缓冲层具有更多的生长方向，随着缓冲层厚度增加，可以进一步降低缓冲层内的缺陷。
进一步的，所述凹槽的顶部宽度为5nm～500nm，可以使得后续在所述凹槽内形成缓冲层时，沉积气体容易进入所述凹槽内，从而使的凹槽内形成的缓冲层具有较高的质量；所述凹槽的深度为8nm～1000nm，使的凹槽的深宽比较低，在凹槽内形成缓冲层时，不会在所述缓冲层内产生空洞等缺陷；相邻凹槽之间的间距为10nm～1000nm，使得在半导体衬底内形成的凹槽的数量较多，从而充分降低后续形成的缓冲层内的缺陷。
进一步的，所述缓冲层还可以包括位于半导体衬底表面的第一缓冲层和位于第一缓冲层表面的第二缓冲层，刻蚀第二缓冲层形成鳍部，然后在鳍部表面形成沟道层，所述半导体衬底、第一缓冲层、第二缓冲层以及沟道层的晶格常数逐渐增大或逐渐降低，所述第一缓冲层和第二缓冲层与单层的缓冲层结构相比，可以进一步降低相邻材料层之间的晶格常数的差异，减少相邻材料层之间由于晶格常数差异而产生的缺陷，从而减少形成的沟道层内的缺陷，提高最终形成的鳍式场效应晶体管的性能。
附图说明
图1至图20是本发明的鳍式场效应晶体管的形成过程的结构示意图。
具体实施方式
如背景技术中所述，由于III-V族材料层与硅衬底的晶格常数相差较大，现有技术中直接在所述硅衬底表面外延形成III-V族材料层作为沟道层会在沟道层内形成较多的缺陷，从而影响最终形成的鳍式场效应晶体管的性能。
研究发现，可以在所述硅衬底表面先形成晶格常数介于硅衬底和沟道层的晶格常数之间的缓冲层，降低相邻层之间的晶格常数差异，使缓冲层内的缺陷较少，从而在缓冲层表面外延形成的沟道层内的缺陷也较少。但是由于所述缓冲层与硅衬底之间依旧存在晶格常数的差异，在硅衬底表面形成的缓冲层内的缺陷会通过外延工艺传递给缓冲层表面形成的沟道层内，所以直接在硅衬底表面形成缓冲层，然后在缓冲层表面形成沟道层，对沟道层内缺陷的减少效果有限。
本发明的实施例，在半导体衬底内形成若干凹槽之后，再在半导体衬底表面形成缓冲层，所述缓冲层填充满凹槽并覆盖半导体衬底表面，可以进一步降低缓冲层内的缺陷，后续再刻蚀部分厚度的缓冲层形成鳍部，使得鳍部表面的缺陷较少，从而进一步降低鳍部表面形成的沟道层内的缺陷，提高最终形成的鳍式场效应晶体管的性能。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
请参考图1，提供半导体衬底100。
所述半导体衬底100的材料包括硅、锗、锗化硅、砷化镓等半导体材料，所述半导体衬底100可以是体材料也可以是复合结构如绝缘体上硅。本领域的技术人员可以根据半导体衬底100上形成的半导体器件选择所述半导体衬底100的类型，因此所述半导体衬底100的类型不应限制本发明的保护范围。
本实施例中，所述半导体衬底100为体硅。
请参考图2，在半导体衬底100表面形成具有若干开口102的掩膜层101。
所述掩膜层101的材料可以是光刻胶、氧化硅、氮化硅等掩膜材料。本实施例中，所述掩膜层101的材料为氧化硅。
本实施例中，形成所述掩膜层101的方法包括：在所述半导体衬底100表面形成掩膜材料层，在所述掩膜材料层表面形成光刻胶层，对所述光刻胶层进行曝光形成图形化光刻胶层，以所述图形化光刻胶层为掩膜刻蚀所述掩膜材料层，在所述掩膜材料层内形成若干开口102，所述开口102暴露出部分半导体衬底100的表面。
请参考图3，采用干法刻蚀工艺沿开口102对半导体衬底100进行第一刻蚀，形成第一子凹槽110a。
所述干法刻蚀工艺采用的刻蚀气体为HBr和Cl2的混合气体作为刻蚀气体，O2作为缓冲气体，其中HBr的流量为50sccm～1000sccm，Cl2的流量为50sccm～1000sccm，O2的流量为5sccm～20sccm，压强为5mTorr～50mTorr，功率为20W～750W，O2的气体流量为5sccm～20sccm，温度为40℃～80℃，偏置电压为10V～250V。本实施例中，所述干法刻蚀工艺形成的第一子凹槽110a的侧壁为弧形。在其他实施例中，通过调整干法刻蚀工艺采用的刻蚀气体或刻蚀参数，可以使形成的第一子凹槽110a的侧壁为倾斜或垂直的侧壁。在本发明的其他所述例中，所述干法刻蚀气体还可以是其他气体，例如含氟气体等。
请参考图4，再采用湿法刻蚀工艺对半导体衬底100进行第二刻蚀，最终形成所述凹槽110。
本实施例中，沿所述第一子凹槽110a对半导体衬底100进行第二刻蚀，所述第二刻蚀采用的湿法刻蚀溶液为四甲基氢氧化铵（TMAH）溶液，刻蚀温度为30℃～80℃。由于所述湿法刻蚀工艺为各向异性刻蚀工艺，在半导体衬底100的不同晶向上具有不同的刻蚀速率，所以使得最终形成的凹槽110的侧壁为Σ形。在本发明的其他实施例中，所述湿法刻蚀工艺还可以采用其他刻蚀溶液，例如KOH或HNO3等。
在本发明的其他所述例中，也可以只进行第一刻蚀，直接将第一刻蚀之后形成的第一子凹槽110a（请参考图3）作为凹槽。
在本发明的其他实施例中，也可以直接采用第二刻蚀工艺形成凹槽。
所述凹槽110的顶部宽度为5nm～500nm，可以使得后续在所述凹槽110内沉积第一缓冲层时，沉积气体容易进入所述凹槽110内，从而使的凹槽110内形成的第一缓冲层具有较高的质量。
所述凹槽110的深度为8nm～1000nm，使的凹槽110的深宽比较低，在凹槽110内沉积第一缓冲层时，不会在所述第一缓冲层内产生空洞等缺陷。
相邻凹槽110之间的间距为10nm～1000nm。使得在半导体衬底110内形成的凹槽110的数量较多，从而充分降低后续形成的第一缓冲层内的缺陷。
请参考图5，去除掩膜层101（请参考图4）之后，在所述半导体衬底100表面形成第一缓冲层200，所述第一缓冲层200填充满凹槽110（请参考图4）并覆盖半导体衬底100的表面。
本实施例中，采用湿法刻蚀工艺去除所述掩膜层101，所述湿法刻蚀工艺采用的刻蚀溶液为HF溶液。
去除所述掩膜层101之后，暴露出半导体衬底100的表面，在所述半导体衬底100表面形成第一缓冲层200，采用外延工艺形成所述第一缓冲层200。
本实施例中，形成所述第一缓冲层200的方法为化学气相沉积工艺。所述第一缓冲层200的材料为锗硅。所述化学气相沉积工艺的反应温度为600℃～1100℃，压强为1托～500托，硅源气体是SiH4或SiH2Cl2，锗源气体为GeH4，还包括氢气，所述氢气作为缓冲气体，其中，硅源气体流量为0.1slm～50slm，锗源气体流量为0.1slm～50slm，氢气的流量为0.1slm～50slm。
所述第一缓冲层200的晶格常数大于半导体衬底100的晶格常数。在本发明的其他所述例中，所述第一缓冲层200还可以采用其他半导体材料，所述第一缓冲层200的晶格常数还可以小于半导体衬底100的晶格常数。
所述第一缓冲层200在外延生长过程中，沿凹槽110（请参考图4）的内壁表面以及半导体衬底100的表面生长。由于在所述半导体衬底100内形成了若干凹槽100，所述凹槽100具有侧壁以及底部表面，第一缓冲层200的材料同时沿凹槽的侧壁及底部表面生长，使得所述第一缓冲层200材料同时具有横向及纵向的生长分量。由于所述第一缓冲层200的材料的晶格常数与半导体衬底100的晶格常数不同，所以，所述第一缓冲层200的材料在生长过程中会产生缺陷，最显著的就是位错缺陷，并且不同生长方向的第一缓冲层200的材料内具有不同方向的位错缺陷。在所述凹槽100内，随着第一缓冲层200的材料的厚度增加，不同生长方向上的第一缓冲层200的材料发生闭合，使得不同生长方向上的第一缓冲层200的材料内的不同方向的位错缺陷之间互相抵消使缺陷数量减少，随着不同方向上闭合的第一缓冲层200的材料的厚度的增加，缺陷的数量也会逐渐降低。
本实施例中，形成的侧壁为Σ形的凹槽110，使凹槽110具有更多不同方向的侧壁表面，从而使第一缓冲层200在凹槽110内具有更多不同的生长方向，从而能够进一步降低第一缓冲层200内的缺陷。
并且，所述凹槽110将半导体衬底100分成不同的区域，使得在半导体衬底100表面生长的第一缓冲层200的材料内的原子的表面迁移在凹槽110处被打断，可以避免半导体衬底100表面形成的第一缓冲层200内的缺陷发生转移，当所述凹槽110内的第一缓冲层200材料厚度逐渐增加，与半导体衬底100表面的第一缓冲层200闭合后，可以去除所述半导体衬底100表面的第一缓冲层200的材料中的缺陷，从而提高最终形成的第一缓冲层200的沉积质量，使所述第一缓冲层200表面缺陷较少，提高后续在第一缓冲层200表面形成的第二缓冲层的质量。
本实施例中，位于半导体衬底100表面的第一缓冲层200的厚度为10nm～500nm。
请参考图6，在所述第一缓冲层200表面形成第二缓冲层300。
所述第二缓冲层300为半导体材料，所述第二缓冲层300的晶格常数大于第一缓冲层200的晶格常数。第二缓冲层300的材料包括铟铝砷化合物或磷化铟等。
采用外延工艺形成所述第二缓冲层300，所述外延工艺可以是金属氧化物化学气相沉积或分子束外延工艺等。本实施例中，所述第二缓冲层300的材料为铟铝砷化合物，采用分子束外延工艺形成所述第二缓冲层300。
所述第二缓冲层300用于形成鳍部。本实施例中，在半导体衬底100表面形成第一缓冲层200之后，在第一缓冲层200表面形成第二缓冲层300。所述第二缓冲层300与后续形成的沟道层的晶格常数接近，可以减少形成沟道层过程中，沟道层内产生的缺陷数量；并且，所述半导体衬底100的晶格常数、第一缓冲层200的晶格常数、第二缓冲层300的晶格常数逐渐增大，第一缓冲层200作为半导体衬底100与第二缓冲层300之间的过渡层，第二缓冲层300与第一缓冲层200之间的晶格常数相差较小，可以提高形成的第二缓冲层300的质量，减少第二缓冲层300内的缺陷，从而提高最终形成的鳍式场效应晶体管的性能。
本实施例中，后续形成的沟道层的晶格常数大于半导体衬底100的晶格常数，所以，所述半导体衬底100的晶格常数、第一缓冲层200的晶格常数、第二缓冲层300的晶格常数逐渐增大至接近沟道层的晶格常数；在本发明的其他实施例中，后续形成的沟道层的晶格常数也可以小于半导体衬底100的晶格常数，从而，可以使所述半导体衬底100的晶格常数、第一缓冲层200的晶格常数、第二缓冲层300的晶格常数逐渐减小至接近沟道层的晶格常数。
本实施例中，所述第二缓冲层300的厚度为10nm～500nm。
在本发明的其他实施例中，也可以仅形成所述第一缓冲层或第二缓冲层作为缓冲层，后续刻蚀部分厚度的第一缓冲层或第二缓冲层形成鳍部。
本实施例中，形成第一缓冲层200和第二缓冲层300，可以进一步降低相邻材料层之间的晶格常数的差距，减少由于晶格常数差异造成的缺陷。
请参考图7和图8，以第一缓冲层200表面作为停止层，刻蚀所述第二缓冲层300（请参考图6）形成鳍部301。图8为形成所述鳍部301之后，沿图7中割线AA’方向的截面示意图。
形成所述鳍部301的方法包括：在所述第二缓冲层300表面形成图形化掩膜层，所述图形化掩膜层定义出后续形成的鳍部的位置和尺寸，以所述图形化掩膜层为掩膜，刻蚀所述第二缓冲层300，形成所述鳍部301后去除所述图形化掩膜层。
请参考图9，在第一缓冲层200表面形成绝缘层201，所述绝缘层201的表面低于鳍部301的顶部表面。
所述绝缘层201的材料为氧化硅、氮氧化硅、碳氧化硅等绝缘介质材料，所述绝缘层201的厚度为所述绝缘层201的表面低于鳍部301的顶部表面。
本实施例中，对所述第一缓冲层200表面进行氧化处理，形成所述绝缘层201，所述绝缘层201的材料为氧化硅。所述氧化处理可以是热氧化处理或者湿法氧化处理。由于所述第二缓冲层200的材料不易被氧化，所以，所述绝缘层201只能形成在第一缓冲层200表面。所述绝缘层201的表面低于鳍部301的顶部表面。采用上述氧化处理工艺形成所述绝缘层201步骤简单，可以节约工艺成本。
在本发明的其他实施例中，也可以采用沉积工艺在所述第一缓冲层200表面形成绝缘材料层，所述绝缘材料层覆盖鳍部表面；以所述鳍部顶部表面作为停止层，对所述绝缘材料层进行平坦化；对所述平坦化的绝缘材料层进行回刻蚀，使所述绝缘材料层的表面低于鳍部的顶部表面，形成所述绝缘层201。
所述绝缘层201作为后续形成的栅极结构与第一缓冲层200之间的隔离结构。
请参考图10和图11，在鳍部301表面形成沟道层302，图11为图10中形成沟道层302后沿割线AA’方向的截面示意图。
所述沟道层302的材料为具有高电子迁移率或高空穴迁移率的半导体材料，例如III-V族半导体材料。若待形成的鳍式场效应晶体管为N型鳍式场效应晶体管，则所述沟道层302为高电子迁移率的半导体材料，包括：铟镓砷或铟镓碲等化合物；若待形成的鳍式场效应晶体管为P型鳍式场效应晶体管，则所述沟道层302为高空穴迁移率的半导体材料，例如碲化镓化合物。
本实施例中，所述待形成的鳍式场效应晶体管为N型鳍式场效应晶体管，所述沟道层302的材料为铟镓砷化合物，具有较高的电子迁移率，可以提高形成的N型鳍式场效应晶体管开关速率等性能。
采用选择性外延工艺在所述绝缘层201上方的鳍部表面形成沟道层302，所述沟道层302不会在绝缘层201表面形成。所述选择性外延工艺可以是金属氧化物化学气相沉积工艺、原子层沉积工艺或分子束外延工艺等。所述沟道层302的厚度为10nm～100nm。
由于所述沟道层302的晶格常数与鳍部301的晶格常数较为接近，所以在所述鳍部301表面外延形成的沟道层302内的缺陷较少，使得所述沟道层302具有较高的质量，从而提高形成的鳍式场效应晶体管的性能。并且，由于在半导体衬底100内形成有凹槽之后，再形成填充满凹槽并覆盖半导体衬底100表面的第一缓冲层200，降低了第一缓冲层200表面的缺陷，从而可以降低在第一缓冲层200表面形成的第二缓冲层300内的缺陷，提高第二缓冲层300的质量，进而减少刻蚀第二缓冲层300后形成的鳍部301的缺陷，进一步提高在鳍部301表面形成的沟道层302的质量。
请参考图12和图13，在所述沟道层302表面以及绝缘层201表面形成栅介质材料层303，图13为沿图12中割线AA’方向的截面示意图。
所述栅介质材料层303的材料为高K介质材料，包括：氧化铝、氧化铪、氧化锆、硅氧化铪、铝硅氧化铪、硅氧化锆、硅氧化钛中的一种或几种。所述栅介质材料层303的厚度为1nm～5nm。可以采用金属氧化物化学气相沉积工艺、原子层沉积工艺或等离子体增强化学气相沉积形成所述栅介质材料层303。
请参考图14和图15，在所述栅介质材料层303表面形成栅极材料层304，图15为沿图14中割线AA’方向的截面示意图。
所述栅极材料层304的材料包括NiAu、CrAu、Al、Cu、Au、Pt、Ni、Ti、TiN、TaN或Ta中的一种或几种。
可以采用物理气相沉积工艺、金属氧化物化学气相沉积工艺、原子层沉积工艺或分子束外延工艺形成所述栅极材料层304。
请参考图16和图17，对所述栅极材料层304（请参考图14）和栅介质材料层303（请参考图14）进行图形化，形成横跨所述鳍部301的栅极结构，所述栅极结构包括栅介质层303a和栅极304a，并且对所述栅极结构两侧的沟道层进行轻掺杂离子注入形成轻掺杂区312（请参考图17）。图17为图16沿割线AA’的截面示意图。
具体的，所述栅极结构的形成方法包括：在栅极材料层304表面形成图形化掩膜层，所述图形化掩膜层定义出栅极结构的尺寸和位置；以所述图形化掩膜层为掩膜，采用干法刻蚀工艺刻蚀栅极材料层和栅介质材料层，形成栅极304a和栅介质层303a。形成所述栅极结构之后，对栅极结构两侧的沟道层302进行轻掺杂离子注入，形成轻掺杂区312。本实施例中，待形成的鳍式场效应晶体管为N型鳍式场效应晶体管，所述轻掺杂离子注入的离子为N型离子，包括P、As或Sb中的一种或几种离子。本发明的其他所述例中，待形成的鳍式场效应晶体管为P型鳍式场效应晶体管，所述轻掺杂离子注入的离子为P型离子。
请参考图18和图19，在所述栅极304a和栅介质层303a侧壁表面形成侧墙305，以所述侧墙305和栅极结构为掩膜，对所述栅极结构两侧的沟道层302进行重掺杂离子注入并进行退火处理激活掺杂离子，形成源漏区322。图19为图18沿割线AA’方向的截面示意图。
所述侧墙305的材料为氮化硅、氧化硅或氮氧化硅等绝缘材料。所述重掺杂离子注入的掺杂离子类型与轻掺杂离子注入的掺杂离子类型相同。
请参考图20，在所述源漏区322表面形成金属电极306。
所述金属电极306的材料为NiAu或CrAu，形成所述金属电极306的方法为物理气相沉积工艺，例如溅射或蒸发工艺。
所述金属电极306可以降低源漏区322的接触电阻。
本实施例还提供一种采用上述方法形成的鳍式场效应晶体管。
请参考图18和图20，所述鳍式场效应晶体管包括：半导体衬底100，所述半导体衬底100内形成有若干凹槽；位于所述半导体衬底100表面的第一缓冲层200，所述第一缓冲层200填充满凹槽并覆盖半导体衬底100表面；位于第一缓冲层200表面的鳍部301；位于鳍部301周围的第一缓冲层200表面的绝缘层201，所述绝缘层201的表面低于鳍部301的顶部表面；位于鳍部301表面的沟道层302；位于部分绝缘层201表面和部分沟道层302表面的横跨鳍部301的栅极结构，所述栅极结构包括栅介质层303a和位于栅介质层303a表面的栅极304a；位于栅极结构两侧的沟道层302内的源漏区322。
所述凹槽的顶部宽度为5nm～500nm，相邻凹槽之间的间距为10nm～1000nm，所述凹槽的深度为8nm～1000nm。
所述第一缓冲层200的材料和鳍部301的材料均半导体材料，所述半导体衬底100的晶格常数、第一缓冲层200的晶格常数、鳍部301的晶格常数、沟道层302的晶格常数逐渐增大或逐渐减小。
所述第一缓冲层200的材料包括锗硅，鳍部301的材料包括铟铝砷化合物或磷化铟。
所述沟道层302的厚度为1nm～10nm，所述沟道层302的材料包括铟镓砷、铟镓碲或碲化镓。
上述鳍式场效应晶体管中，第一缓冲层200的缺陷较少，使得位于第一缓冲层200表面的鳍部301的缺陷较少，进而使得位于鳍部301表面的沟道层内的缺陷较少，从而可以提高沟道层302内的载流子迁移率等性能，提高形成的鳍式场效应晶体管的性能。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (19)

1.一种鳍式场效应晶体管的形成方法，其特征在于，包括：
提供半导体衬底；
在所述半导体衬底内形成若干凹槽；
在所述半导体衬底表面形成缓冲层，所述缓冲层填充满凹槽并覆盖半导体衬底表面；
刻蚀部分厚度的缓冲层，形成鳍部，剩余的缓冲层填满凹槽并完全覆盖半导体衬底表面；
在鳍部周围的缓冲层上形成绝缘层，所述绝缘层的表面低于鳍部的顶部表面；
在鳍部表面形成沟道层；
在部分绝缘层表面和部分沟道层表面形成横跨鳍部的栅极结构；
在栅极结构两侧的沟道层内形成源漏区。
2.根据权利要求1所述的鳍式场效应晶体管的形成方法，其特征在于，所述凹槽的顶部宽度为5nm～500nm。
3.根据权利要求1所述的鳍式场效应晶体管的形成方法，其特征在于，相邻凹槽之间的间距为10nm～1000nm。
4.根据权利要求1所述的鳍式场效应晶体管的形成方法，其特征在于，所述凹槽的深度为8nm～1000nm。
5.根据权利要求1所述的鳍式场效应晶体管的形成方法，其特征在于，形成所述凹槽的方法包括：在半导体衬底表面形成具有若干开口的掩膜层，沿所述开口刻蚀半导体衬底，在所述半导体衬底内形成若干凹槽。
6.根据权利要求5所述的鳍式场效应晶体管的形成方法，其特征在于，沿所述开口刻蚀半导体衬底的方法为湿法刻蚀工艺或干法刻蚀工艺。
7.根据权利要求5所述的鳍式场效应晶体管的形成方法，其特征在于，沿所述开口刻蚀半导体衬底的方法包括：采用干法刻蚀工艺对半导体衬底进行第一刻蚀，然后再采用湿法刻蚀工艺对半导体衬底进行第二刻蚀，最终形成所述凹槽。
8.根据权利要求7所述的鳍式场效应晶体管的形成方法，其特征在于，所述干法刻蚀工艺采用的刻蚀气体为HBr和Cl2的混合气体作为刻蚀气体，O2作为缓冲气体，其中HBr的流量为50sccm～1000sccm，Cl2的流量为50sccm～1000sccm，O2的流量为5sccm～20sccm，压强为5mTorr～50mTorr，功率为20W～750W，O2的气体流量为5sccm～20sccm，温度为40℃～80℃，偏置电压为10V～250V；所述湿法刻蚀工艺采用的刻蚀溶液为四甲基氢氧化铵溶液，温度为30℃～80℃。
9.根据权利要求8所述的鳍式场效应晶体管的形成方法，其特征在于，所述凹槽的侧壁为Σ形。
10.根据权利要求1所述的鳍式场效应晶体管的形成方法，其特征在于，所述缓冲层包括第一缓冲层和位于第一缓冲层表面的第二缓冲层，所述第一缓冲层填充满凹槽并覆盖半导体衬底的表面。
11.根据权利要求10所述的鳍式场效应晶体管的形成方法，其特征在于，位于半导体衬底表面的第一缓冲层的厚度为10nm～500nm，第二缓冲层的厚度为10nm～500nm。
12.根据权利要求10所述的鳍式场效应晶体管的形成方法，其特征在于，所述第一缓冲层的材料和第二缓冲层的材料均为半导体材料，所述半导体衬底的晶格常数、第一缓冲层的晶格常数、第二缓冲层的晶格常数、沟道层的晶格常数逐渐增大或逐渐减小。
13.根据权利要求12所述的鳍式场效应晶体管的形成方法，其特征在于，所述第一缓冲层的材料包括锗硅，第二缓冲层的材料包括铟铝砷化合物或磷化铟。
14.根据权利要求10所述的鳍式场效应晶体管的形成方法，其特征在于，以第一缓冲层表面作为停止层，刻蚀所述第二缓冲层形成鳍部。
15.根据权利要求10所述的鳍式场效应晶体管的形成方法，其特征在于，对所述第一缓冲层表面进行氧化处理，形成所述绝缘层，所述绝缘层的厚度为
16.根据权利要求1所述的鳍式场效应晶体管的形成方法，其特征在于，采用选择性外延工艺在所述鳍部表面形成沟道层，所述沟道层的厚度为1nm～10nm，所述沟道层的材料包括铟镓砷、铟镓碲或碲化镓。
17.一种鳍式场效应晶体管，其特征在于，包括：
半导体衬底，所述半导体衬底内形成有若干凹槽；
位于所述半导体衬底表面的第一缓冲层，所述第一缓冲层填充满凹槽并覆盖半导体衬底表面；
位于第一缓冲层表面的鳍部；
位于鳍部周围的第一缓冲层表面的绝缘层，所述绝缘层的表面低于鳍部的顶部表面
位于鳍部表面的沟道层；
位于部分绝缘层表面和部分沟道层表面的横跨鳍部的栅极结构；
位于栅极结构两侧的沟道层内的源漏区；
所述第一缓冲层的材料和鳍部的材料均半导体材料，所述半导体衬底的晶格常数、第一缓冲层的晶格常数、鳍部的晶格常数、沟道层的晶格常数逐渐增大或逐渐减小。
18.根据权利要求17所述的鳍式场效应晶体管，其特征在于，所述凹槽的顶部宽度为5nm～500nm，相邻凹槽之间的间距为10nm～1000nm，所述凹槽的深度为8nm～1000nm。
19.根据权利要求17所述的鳍式场效应晶体管，其特征在于，所述第一缓冲层的材料包括锗硅，鳍部的材料包括铟铝砷化合物或磷化铟，所述沟道层的材料包括铟镓砷、铟镓碲或碲化镓。
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