CN111312800B - 具有外延层的半导体结构及其制作方法 - Google Patents

具有外延层的半导体结构及其制作方法 Download PDF

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CN111312800B
CN111312800B CN201811517688.5A CN201811517688A CN111312800B CN 111312800 B CN111312800 B CN 111312800B CN 201811517688 A CN201811517688 A CN 201811517688A CN 111312800 B CN111312800 B CN 111312800B
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substrate
layer
epitaxial layer
semiconductor structure
barrier layer
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CN111312800A (zh
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周孝邦
刘鸿辉
卢明昌
林进富
童宇诚
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United Microelectronics Corp
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Abstract

本发明公开了一种具有外延层的半导体结构及其制作方法，该具有外延层的半导体结构包含一基底、一阻挡层位于该基底上、多个凹槽形成在该基底中，其中该凹槽沿着该基底的<111>晶面分布、以及一外延层，位于该阻挡层上，其中该外延层具有形成在每个该凹槽中的埋入部位以及形成在该阻挡层上的表面部位。

Description

具有外延层的半导体结构及其制作方法
技术领域
本发明涉及一种具有外延层的半导体结构有关，更确切地说，其涉及一种具有外延层埋入在基底凹槽中的半导体结构。
背景技术
氮化镓(gallium nitride,GaN)具有优异的电性，诸如高击穿电场、高电子饱和速度、低导通电阻等，其适合用来作为功率元件的材料。然而，尽管有着比传统硅材优良的材料特性，氮化镓材料最大的问题就是很难制作出大尺寸的晶片。以现今成本最低的氮化镓覆硅(GaN-on-Si)基板来说，其是将氮化镓以外延方式生长在硅基板上。由于氮化镓的热膨胀系数远大于硅，再加上两者的晶格并不相容，这种不协调的状况很容易在晶膜成长或是后续加工时因为应力因素而导致氮化镓外延膜破裂(crack)、脱层(delamination)、产生错位(dislocation)缺陷、或是整个晶片弯曲变形等问题。
现今业界采用了一些做法来克服上述氮化镓覆硅基板制作时会发生的问题，例如先在硅材表面上生长数层氮化铝镓(AlGaN)材质的异质缓冲层，或是使用具有微图案特征的硅基板来生长外延等。这些做法虽然能改善上述问题，但是其错位缺陷的密度过高以及散热性不佳仍然是其亟待改善的地方。故此，现今业界仍需对氮化镓覆硅基板结构与相关制作方式做进一步的改良。
发明内容
为了对现有的氮化镓覆硅基板结构作进一步的改良，本案提出了一种新颖的半导体结构，其特点在于所形成的外延层具有嵌入在基底中的埋入部位，可以改善传统氮化镓覆硅基板的散热与缺陷问题。
本发明的其一目的在于提供一种具有外延层的半导体结构，其包含一基底、一阻挡层位于该基底上、多个凹槽形成在该基底中，其中该凹槽沿着该基底的<111>晶面分布、以及一外延层位于该阻挡层上，其中该外延层具有形成在每个该凹槽中的埋入部位以及形成在该阻挡层上的表面部位。
本发明的另一目的在于提出一种具有外延层的半导体结构的制作方法，其步骤包含提供一基底、在该基底上形成一阻挡层，其中该阻挡层具有预先界定好的凹槽图案、以该阻挡层为掩模进行一蚀刻制作工艺蚀刻该基底，以在该基底中形成多个凹槽，其中该凹槽沿着该基底的<111>晶面分布、以及进行一外延制作工艺在该基底上形成一外延层，其中该外延层具有位于每个该凹槽中的埋入部位以及位于该阻挡层上的表面部位。
本发明的这类目的与其他目的在阅者读过下文以多种图示与绘图来描述的优选实施例细节说明后必然可变得更为明了显见。
附图说明
图1至图3为本发明优选实施例中制作具有外延层的半导体结构的方法流程的截面示意图；
图4为本发明另一实施例中具有外延层的半导体结构的截面示意图；
图5为本发明又一实施例中具有外延层的半导体结构的截面示意图；以及
图6为本发明又一实施例中具有外延层的半导体结构的截面示意图。
主要元件符号说明
100 基底
102 阻挡层
104 图案化光致抗蚀剂层
104a 图案
106 凹槽
108 外延层
108a 埋入部位
108b 表面部位
108c 中间部位
110 空洞
112 空洞
114 缓冲层
具体实施方式
在下文的本发明细节描述中，元件符号会标示在随附的图示中成为其中的一部分，并且以可实行该实施例的特例描述方式来表示。这类的实施例会说明足够的细节使该领域的一般技术人士得以具以实施。为了图例清楚之故，图示中可能有部分元件的厚度会加以夸大。阅者需了解到本发明中亦可利用其他的实施例或是在不悖离所述实施例的前提下作出结构性、逻辑性、及电性上的改变。因此，下文的细节描述将不欲被视为是一种限定，反之，其中所包含的实施例将由随附的权利要求来加以界定。
一般而言，文中的术语可以至少部分地根据上、下文中的用法来理解。例如，如本文所使用的术语「一或多个」可用于以单数意义描述任何特征、结构或特性，或可用于描述特征、结构或特征的复数组合，至少可部分取决于上、下文。类似地，术语诸如「一」、「一个」或「该」也可以被理解为表达单数用法或传达复数用法，至少可部分取决于上、下文。
应该容易理解的是，本文中的「在...上面」、「在...之上」及「在...上方」的含义应该以最宽泛的方式来解释，使得「在...上面」不仅意味着「直接在某物上」，而且还包括在某物上且两者之间具有中间特征或中间层，并且「在...之上」或「在...上方」不仅意味着在某物之上或在某物上方的含义，而且还可以包括两者之间没有中间特征或中间层(即，直接在某物上)的含义。
此外，为了便于描述，可以在说明书使用诸如「在...下面」、「在...之下」、「较低」、「在...之上」、「较高」等空间相对术语来描述一个元件或特征与另一个或多个元件或特征的关系，如图式中所表示者。除了图式中描绘的方向之外，这些空间相对术语旨在涵盖使用或操作中的装置的不同方位或方向。该装置可以其他方式定向(例如以旋转90度或以其它方向来定向)，并且同样能相应地以说明书中所使用的空间相关描述来解释。
如本文所用，术语「基底」是指在其上添加后续材料层的材料。基底本身可以被图案化。添加在基底顶部的材料可以被图案化或可以保持未图案化。此外，基底可以包括多种半导体材料，例如硅、锗、砷化镓、磷化铟等。或者，基底可以由非导电材料制成，例如玻璃、塑料或蓝宝石晶片。
现在图1至图3将依序绘示出根据本发明优选实施例制作具有外延层的半导体结构的方法流程。请参照图1，首先提供一基底100，如一硅基板、碳化硅基板、或蓝宝石基板，作为外延层的生长基础。接着，在基底100上形成一阻挡层102，如一以化学气相沉积(chemical vapor deposition,CVD)制作工艺形成的氧化硅层或氮化硅层。阻挡层102会遮盖基底100的表面，使得其所遮盖的部位在外延制作工艺中不会有外延生成。之后，在阻挡层102上形成一图案化光致抗蚀剂层104。图案化光致抗蚀剂层104中具有预先界定出的微图案104a，其可以使用先进无掩模光刻技术如电子束(E-beam)或是纳米压印(nanoimprint)技术来形成。
在本发明实施例中，图案104a可以是圆形、方形、或长方形等对称图案，其开口大小约介于10nm至200nm之间，可以一定的密度均匀地分布在基底100的表面，用途为在后续制作工艺中在基底中形成凹槽图案。图案104a与图案104a之间的间距不会太宽，较佳为其开口大小的二至三倍。接着，以图案化光致抗蚀剂层104为掩模对阻挡层102进行一干蚀刻制作工艺，以将图案化光致抗蚀剂层104中的图案104a转移到阻挡层102中。阻挡层102中的图案104a会裸露出下方的基底100。阻挡层102图案化后可以将图案化光致抗蚀剂层104加以移除。
接着请参照图2。在形成图案化阻挡层102后，接着以图案化阻挡层102为蚀刻掩模进行一蚀刻制作工艺，以在基底100中形成凹槽106。在本发明实施例中，该蚀刻制作工艺包含一斜角度湿蚀刻(slope wet etch)制作工艺，特别是使用氢氧化钾(KOH)蚀刻液的湿蚀刻制作工艺来蚀刻晶面为<100>的硅基底，其可在基底100中形成如图中所示沿着<111>晶面形成的钻石形凹槽106。在本发明实施例中，此特殊形状的凹槽106将可使后续生长在其中的外延具有对应的形状，以达到本发明所需的功效。
接下来请参照图3。在形成钻石形凹槽106后，接下来进行一外延制作工艺在基底上形成外延层108，其材质可为氮化镓(GaN)或氮化铝镓(AlxGayN)。由于阻挡层102存在之故，外延层108只会从未被阻挡层102遮盖的基底100表面开始生长，即为从凹槽106的表面开始生长。尽管在本发明实施例中外延层108是从个别的凹槽106开始生长，其在长出凹槽106外后会合并形成一共同的外延结构，其可完全覆盖住整个基底100表面。在本发明实施例中，外延层108包含形成在每个凹槽106中的埋入部位108a以及形成在阻挡层102上的表面部位108b，外延层108的埋入部位108a与表面部位108b之间还有连接彼此的中间部位108c，其形成在阻挡层102中。
复参照图3。在本发明实施例中，由于外延层108并非从基底100表面开始生长之故，从图中可以看到外延层108的表面部位108b与阻挡层102之间会有空洞110形成，每个空洞110都分别形成在两个埋入部位108a之间。此外延层108与阻挡层102之间空洞110的形成将有助于释放外延介面的应力，降低外延材料与基底材料之间晶格不相配而会产生的破裂问题。此外，由于形成于凹槽106中的外延层108埋入部位108a具有钻石状的外型，相比于直接长在平坦的基底面上的外延结构，其可有效地将外延介面在热循环过程中产生的剪力转换为压应力，避免晶片产生弯曲变形或是脱层问题。再者，嵌在基底中的该埋入部位108a可大幅增加外延层108与基底100的接触面积，以改善整个基板的散热效率。最后，由于外延层108是从具有<111>晶面的凹槽106表面开始生长，外延层与基底之间固有的错位缺陷都会局限在该凹槽106中而不会向上扩散至外延层108的表面部位108b，使得外延层108真正会用到的该表面部位108b会具有优良的外延性质。
在整个基底表面上形成外延层108后，后续就可以在该外延层108上进行半导体元件的制作，如发光二极管或功率元件等。由于该些半导体元件与相关特征并非本发明的重点，故文中将不多予赘述。
现在请参照图4，其为根据本发明另一实施例中具有外延层的半导体结构的截面示意图。如图4所示，在本实施例中，形成在凹槽106中的外延层108埋入部位108a内部可能有空洞112形成，其也有助于释放外延层的应力。另一方面，外延层108与阻挡层102之间也有可能没有空洞形成。
现在请参照图5，其为根据本发明另一实施例中具有外延层的半导体结构的截面示意图。在本发明实施例中，进行外延制作工艺之前可先在凹槽106的表面形成一缓冲层114，缓冲层114会具有与外延层108较为相似的材料组成。例如，当所要形成的外延层108为氮化镓(GaN)时，缓冲层114的材料可选用氮化铝(AlN)层或是氮化铝镓(AlxGayN)等材料。此缓冲层114将可进一步减缓外延层108与基底100之间的性质不匹配的问题，使得后续在其上生长出的外延层108品质较佳。
在其他实施例中，例如在斜角度湿蚀刻制作工艺未进行完全的情况下，其基底100中所形成的凹槽106也有可能不具备完美的钻石形状，而是会具有一水平底面106a，如图6所示。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (17)

1.一种具有外延层的半导体结构，其特征在于，包含：
基底；
阻挡层，位于该基底上，其中该阻挡层具有预先界定好的凹槽图案；
多个凹槽，形成在该基底中，其中该多个凹槽的每一个具有中心线垂直于该基底的表面的三维钻石形状；
缓冲层，形成在该凹槽的表面上；以及
外延层，位于该缓冲层上，其中该外延层具有形成在该多个凹槽的每一个中的埋入部位以及形成在该阻挡层正上方和该阻挡层的该凹槽图案正上方的仅一个表面以上部位，且该表面以上部位直接连接该多个凹槽的每一个中的该埋入部位，且第一空洞形成在该外延层的位于该凹槽中的每个该埋入部位内部。
2.如权利要求1所述的具有外延层的半导体结构，其中该外延层的该表面以上部位与该阻挡层之间形成有多个第二空洞。
3.如权利要求2所述的具有外延层的半导体结构，其中每一个该第二空洞都分别形成在两个该凹槽之间。
4.如权利要求1所述的具有外延层的半导体结构，其中该外延层还包含位于该阻挡层中的多个中间部位，且该多个中间部位的每一个连接该埋入部位之一与该表面以上部位。
5.如权利要求1所述的具有外延层的半导体结构，其中该缓冲层的材质为氮化铝或氮化铝镓。
6.如权利要求1所述的具有外延层的半导体结构，其中该凹槽沿着该基底的<111>晶面分布。
7.如权利要求1所述的具有外延层的半导体结构，其中该凹槽具有水平底面。
8.如权利要求1所述的具有外延层的半导体结构，其中该基底为晶面为<100>的硅基底。
9.如权利要求1所述的具有外延层的半导体结构，其中该外延层的材质为氮化镓或氮化铝镓。
10.如权利要求1所述的具有外延层的半导体结构，其中该外延层形成在整个该基底表面上。
11.一种具有外延层的半导体结构的制作方法，包含：
提供基底；
在该基底上形成阻挡层，其中该阻挡层具有预先界定好的凹槽图案；
以该阻挡层为掩模进行蚀刻制作工艺蚀刻该基底，以在该基底中形成多个凹槽，其中该多个凹槽的每一个具有中心线垂直于该基底的表面的三维钻石形状；
在该多个凹槽的每一个的表面上形成缓冲层；以及
进行外延制作工艺在该缓冲层上形成外延层，其中该外延层具有位于该多个凹槽的每一个中的埋入部位以及具有位于该阻挡层正上方和该阻挡层的该凹槽图案正上方的仅一个表面以上部位，该表面以上部位直接连接该多个凹槽的每一个中的该埋入部位，且第一空洞形成在该外延层的位于该凹槽中的每个该埋入部位内部。
12.如权利要求11所述的具有外延层的半导体结构的制作方法，其中该外延层还包括形成在该表面以上部位与该阻挡层之间的多个第二空洞。
13.如权利要求12所述的具有外延层的半导体结构的制作方法，其中该多个第二空洞的每一个都分别形成在两个该凹槽之间。
14.如权利要求11所述的具有外延层的半导体结构的制作方法，其中该蚀刻制作工艺包含斜角度湿蚀刻制作工艺。
15.如权利要求11所述的具有外延层的半导体结构的制作方法，还包含：
在该阻挡层上形成光致抗蚀剂层；
进行电子束光刻制作工艺在该光致抗蚀剂层上形成该凹槽图案；
以该光致抗蚀剂层为掩模进行另一蚀刻制作工艺，以在该阻挡层上形成该凹槽图案；以及
移除该光致抗蚀剂层。
16.如权利要求11所述的具有外延层的半导体结构的制作方法，其中该多个凹槽的每一个沿着该基底的<111>晶面分布。
17.如权利要求11所述的具有外延层的半导体结构的制作方法，其中该基底为晶面为<100>的硅基底。
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