TW201312751A - 半導體元件及其形成方法 - Google Patents
半導體元件及其形成方法 Download PDFInfo
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- TW201312751A TW201312751A TW101114866A TW101114866A TW201312751A TW 201312751 A TW201312751 A TW 201312751A TW 101114866 A TW101114866 A TW 101114866A TW 101114866 A TW101114866 A TW 101114866A TW 201312751 A TW201312751 A TW 201312751A
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- Prior art keywords
- fin structure
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- semiconductor device
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- 238000000034 method Methods 0.000 title claims abstract description 38
- 239000004065 semiconductor Substances 0.000 title claims description 52
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000013078 crystal Substances 0.000 claims description 18
- 230000004888 barrier function Effects 0.000 claims description 16
- 239000012535 impurity Substances 0.000 claims description 15
- 239000002019 doping agent Substances 0.000 claims description 14
- 238000009792 diffusion process Methods 0.000 claims description 13
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 239000000969 carrier Substances 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 143
- 150000002500 ions Chemical class 0.000 description 82
- 230000005669 field effect Effects 0.000 description 28
- 239000000463 material Substances 0.000 description 25
- 229910052732 germanium Inorganic materials 0.000 description 14
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 14
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- 125000006850 spacer group Chemical group 0.000 description 12
- 239000007789 gas Substances 0.000 description 11
- 229910052799 carbon Inorganic materials 0.000 description 10
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 8
- 238000005530 etching Methods 0.000 description 8
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 238000000151 deposition Methods 0.000 description 7
- -1 phosphorus ions Chemical class 0.000 description 7
- 239000007943 implant Substances 0.000 description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- 230000001186 cumulative effect Effects 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 3
- 229910052684 Cerium Inorganic materials 0.000 description 3
- GWXLDORMOJMVQZ-UHFFFAOYSA-N cerium Chemical compound [Ce] GWXLDORMOJMVQZ-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000001307 helium Substances 0.000 description 3
- 229910052734 helium Inorganic materials 0.000 description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 3
- 238000011065 in-situ storage Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- GPBUGPUPKAGMDK-UHFFFAOYSA-N azanylidynemolybdenum Chemical compound [Mo]#N GPBUGPUPKAGMDK-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000007654 immersion Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 229910003468 tantalcarbide Inorganic materials 0.000 description 2
- XSOKHXFFCGXDJZ-UHFFFAOYSA-N telluride(2-) Chemical compound [Te-2] XSOKHXFFCGXDJZ-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- NZIHMSYSZRFUQJ-UHFFFAOYSA-N 6-chloro-1h-benzimidazole-2-carboxylic acid Chemical compound C1=C(Cl)C=C2NC(C(=O)O)=NC2=C1 NZIHMSYSZRFUQJ-UHFFFAOYSA-N 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052691 Erbium Inorganic materials 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910003855 HfAlO Inorganic materials 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- MRPWWVMHWSDJEH-UHFFFAOYSA-N antimony telluride Chemical compound [SbH3+3].[SbH3+3].[TeH2-2].[TeH2-2].[TeH2-2] MRPWWVMHWSDJEH-UHFFFAOYSA-N 0.000 description 1
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- HPQRSQFZILKRDH-UHFFFAOYSA-M chloro(trimethyl)plumbane Chemical compound C[Pb](C)(C)Cl HPQRSQFZILKRDH-UHFFFAOYSA-M 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 description 1
- IAOQICOCWPKKMH-UHFFFAOYSA-N dithieno[3,2-a:3',2'-d]thiophene Chemical compound C1=CSC2=C1C(C=CS1)=C1S2 IAOQICOCWPKKMH-UHFFFAOYSA-N 0.000 description 1
- UYAHIZSMUZPPFV-UHFFFAOYSA-N erbium Chemical compound [Er] UYAHIZSMUZPPFV-UHFFFAOYSA-N 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000002294 plasma sputter deposition Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 1
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- CXXKWLMXEDWEJW-UHFFFAOYSA-N tellanylidenecobalt Chemical compound [Te]=[Co] CXXKWLMXEDWEJW-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02362—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment formation of intermediate layers, e.g. capping layers or diffusion barriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02293—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
- H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L2029/7857—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET of the accumulation type
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
本發明之實施例提供控制通道厚度的系統與方法,並避免因為形成較小的特徵而變異。本發明之實施例包含升高於基底之上的鰭片結構,以及形成在鰭片結構之上的覆蓋層,通道載子被重摻雜的鰭片結構排斥,並局限在覆蓋層內,其形成薄的通道,使得閘極具有較大的靜電控制。
Description
本發明係有關於半導體元件,特別有關於鰭式場效電晶體的結構與形成方法。
電晶體為近代積體電路關鍵的元件,為了滿足越來越快的速度需求,電晶體的驅動電流也必須越來越大。因為電晶體的驅動電流與電晶體的閘極寬度成比例,電晶體較佳為具有較大的寬度。
然而,增加閘極寬度與降低半導體元件尺寸的需求互相抵觸,因此發展出鰭式場效電晶體(fin field effect transistor;FinFET)。
採用鰭式場效電晶體(FinFET)具有增加驅動電流,但不需付出佔用更多晶片面積的代價之優異特徵,然而,即使鰭式場效電晶體相較於佔用相同晶片面積的平面式電晶體具有改善的短通道效應(short-channel effects;SCE),鰭式場效電晶體仍然受到短通道效應之苦,為了幫助在鰭式場效電晶體內控制短通道效應,鰭式場效電晶體的鰭片結構(fin)寬度通常很窄,要形成如此小的特徵之製程有其困難度,並且在狹窄的鰭片結構設計中,鰭片結構會完全地或大部分地被耗盡,並且會減少經由基底偏壓(bias)對臨界電壓(threshold voltage)的控制。
因此,業界亟需一種半導體元件,其可以合併鰭式場效電晶體,以擷取其在克服習知缺點的同時可以增加驅動電流的優勢,但不會增加使用的晶片面積。
依據本發明之一實施例,半導體元件包括:基底,鰭片結構升高於基底之上,鰭片結構包括:內側部分,具有第一能帶間隙和第一結晶方向;以及外側部分,設置在內側部分的頂部表面與側面上,外側部分具有第二能帶間隙和第二結晶方向,第二能帶間隙小於或等於第一能帶間隙。
依據本發明之一實施例,半導體元件包括:基底,鰭片結構升高於基底之上,鰭片結構包括:內側部分,具有第一結晶方向和第一濃度的摻雜物;以及外側部分,設置在內側部分的頂部表面與側面上,外側部分具有第二結晶方向和第二濃度的摻雜物。
依據本發明之一實施例,半導體元件包括:基底,非平面電晶體設置於基底上,非平面電晶體包括:鰭片結構,具有第一結晶方向,鰭片結構含有第一導電型的雜質;源極與汲極區設置在鰭片結構內,源極含有第二導電型的雜質,第二導電型與第一導電型不同;以及覆蓋層設置在鰭片結構的頂部表面與側面上,覆蓋層具有第二結晶方向和小於或等於該鰭片結構的能帶間隙。
依據本發明之一實施例,半導體元件的製造方法包括:提供基底;在基底的頂部表面上形成半導體鰭片結構;以及在半導體鰭片結構的頂部表面與側面上形成覆蓋層,覆蓋層具有小於或等於半導體鰭片結構的能帶間隙。
依據本發明之一實施例,半導體元件包括:基底,鰭片結構升高於基底之上,鰭片結構包括:內側部分,具有第一能帶間隙和第一結晶方向;中間部分,設置在內側部分的頂部表面與側面上,中間部分具有第二能帶間隙和第二結晶方向,第二能帶間隙大於第一能帶間隙;以及外側部分,設置在中間部分的頂部表面與側面上,外側部分具有第三能帶間隙和第三結晶方向。
為了讓本發明之上述目的、特徵、及優點能更明顯易懂,以下配合所附圖式,作詳細說明如下:
以下詳述各實施例的製造與使用,然而,可以理解的是,這些實施例提供許多可應用的發明概念,其可以在各種不同的特定領域中實施,在此所討論的特定實施例僅用於說明在此揭示的實施例之製造與使用的特定方式,並非用於限定不同實施例的範圍。
在此揭示新的鰭式場效電晶體(FinFET)以及其形成方法,以下說明製造本發明之實施例的中間階段,並討論實施例的各種變化。在本發明的各種圖式與實施例中,相似的元件以相似的參考數字標示。
第1圖顯示鰭式場效電晶體(FinFET)50的透視圖,其包含鰭片結構(fin)150、第一覆蓋層151、閘極180、源極區230以及汲極區231。鰭片結構150以垂直的矽鰭片形式在基底(未繪出)上方延伸形成,並用於形成源極區230、汲極區231以及介於源極與汲極區之間的通道區(未繪出)。第一覆蓋層151圍繞鰭片結構150形成,在通道區內形成閘極介電層(未繪出),然後形成閘極180圍繞鰭片結構,並且包圍通道區內的鰭片結構。對源極區230和汲極區231進行摻雜,使得鰭片結構150的這些部分具導電性。在另一實施例中,可藉由形成的第一凹陷(詳細討論請參閱第9A-9C圖),然後利用選擇性的磊晶成長(selective epitaxial growth;SEG)(詳細討論請參閱第10A-10C圖)磊晶地生成源極與汲極區,以形成源極區230和汲極區231。在另一實施例中,可使用非選擇性的磊晶成長。可經由以下討論的佈植方法對這些區域進行摻雜,或者當材料成長時藉由原位(in-situ)進行摻雜。
使用第2圖的流程圖說明形成鰭片型多閘極電晶體(fin type multiple-gate transistor)的方法20,在第2圖中所描述的各製程步驟期間的多閘極電晶體的剖面圖在第3A-10C圖中顯示。
步驟22為在基底上形成半導體層,如第3A、3B和3C圖所示。第3A圖為沿著第1圖的線Y-Y的Z平面,第3B圖為沿著第1圖的線X-X的Z平面,第3C圖為沿著第1圖的線X-X的Y平面。
參閱第3A、3B和3C圖,其顯示在基底110上的半導體層130,半導體層130可包括巨塊矽或絕緣層上的矽(silicon-on-insulator;SOI)基底的主動層。一般而言,絕緣層上的矽(SOI)基底包括一層半導體材料,例如矽、鍺、矽鍺、絕緣層上的矽(SOI)、絕緣層上的矽鍺(silicon germanium on insulator;SGOI)或前述之組合。半導體層130可由元素半導體例如矽,合金半導體例如矽鍺,或化合物半導體例如砷化鎵(gallium arsenide)或磷化銦(indium phosphide)形成。在一實施例中,半導體層130為矽。經由佈植製程140對半導體層130進行摻雜,將p型或n型雜質導入半導體層130內。依據一實施例,可使用硼或二氟化硼(boron difluoride)離子導入p型雜質,並且可使用砷或磷離子導入n型雜質,其摻雜程度從1e17離子數/立方公分(ions/cm3)至5e19離子數/立方公分(ions/cm3)。
步驟24為將半導體層圖案化成鰭片結構,如第4A、4B和4C圖所示。第4A圖為沿著第1圖的線Y-Y的Z平面,第4B圖為沿著第1圖的線X-X的Z平面,第4C圖為沿著第1圖的線X-X的Y平面。
參閱第4A、4B和4C圖,將半導體層130圖案化形成鰭片結構150。鰭片結構的圖案化製程可藉由在半導體層130之上沈積常用的遮罩材料(未繪出),例如光阻或氧化矽,然後將遮罩材料圖案化,並且依據此圖案將半導體層蝕刻而達成。在此方法中,可在基底上方形成半導體鰭片狀的半導體結構。如第4B和4C圖所示,鰭片結構150沿著第1圖的線X-X延伸。在另一實施例中,鰭片結構150可從基底110的頂部表面磊晶地成長在基底110頂上的圖案化層中的溝槽或開口內。此製程為習知技術,在此不再詳述。在一實施例中,如第4A和4C圖所示,鰭片結構150的寬度160可介於約2nm至20nm之間,並且如第4A和4B圖所示,鰭片結構150的高度161可介於約7nm至50nm之間。
步驟26為在鰭片結構的頂部表面與側面上形成覆蓋層,如第5A、5B和5C圖所示。第5A圖為沿著第1圖的線Y-Y的Z平面,第5B圖為沿著第1圖的線X-X的Z平面,第5C圖為沿著第1圖的線X-X的Y平面。
可使用第一覆蓋層151來幫助在閘極底下的薄層內保留通道載子,使得閘極的靜電控制獲得改善。在NMOS空乏型(depletion-mode)鰭式場效電晶體(FinFET)的實施例中,此薄的通道可藉由具有重摻雜的p型摻雜的鰭片結構150與未摻雜、輕摻雜的p型摻雜或輕摻雜的n型摻雜的覆蓋層151,以及重摻雜的n型摻雜的源極與汲極區的結合而完成。反之,在PMOS空乏型鰭式場效電晶體(FinFET)的實施例中,此薄的通道可藉由具有重摻雜的n型摻雜的鰭片50與未摻雜、輕摻雜的n型摻雜或輕摻雜的p型摻雜的覆蓋層151,以及重摻雜的p型摻雜的源極與汲極區的結合而完成。在這些實施例中,形成第一覆蓋層151的材料之能帶間隙(band gap)應該小於形成鰭片結構150的材料之能帶間隙,其可以讓通道載子停留在被第一覆蓋層151定義的閘極底下的薄層內。此外,可使用第一覆蓋層151來幫助奈米尺寸級的鰭片結構150的穩定度。
參閱第5A、5B和5C圖,第一覆蓋層151利用選擇性的磊晶成長(SEG)而磊晶地成長在鰭片結構150暴露出來的部分上,第一覆蓋層151可由與鰭片結構150相同或不同的半導體材料形成。在一實施例中,第一覆蓋層151由大抵上純的矽形成,在其他實施例中,第一覆蓋層151可包括矽鍺(SiGe)、碳化矽(SiC)或類似的材料。形成第一覆蓋層151的方法可包含原子層沈積(atomic layer deposition;ALD)、化學氣相沈積(chemical vapor deposition;CVD),例如降壓的化學氣相沈積(reduced pressure CVD;RPCVD)、有機金屬化學氣相沈積(metalorganic chemical vapor deposition;MOCVD)或其他可應用的方法。取決於第一覆蓋層151需要的組成,作為磊晶的前驅物可包含含有矽的氣體以及含有鍺的氣體,例如SiH4和GeH4,以及/或類似的材料,並且調整含矽氣體以及含鍺氣體的分壓,可以修改鍺對矽的原子比。在需要SiGe形成第一覆蓋層151的實施例中,其形成的第一覆蓋層151中包含大於20原子百分比的鍺。在第一覆蓋層151中,鍺的百分比也可介於約20原子百分比至約50原子百分比之間。第一覆蓋層151可經由前述討論的佈植方法進行摻雜,或者當材料成長時藉由原位(in-situ)摻雜方式進行摻雜。
在磊晶製程期間,可在製程氣體中加入蝕刻氣體,例如HCl氣體,作為蝕刻氣體,使得第一覆蓋層151選擇性地成長在鰭片結構150上,但不會成長在基底110上,如第5A、和5C圖所示。在其他實施例中,不添加蝕刻氣體,或蝕刻氣體的量很小,使得基底110上形成一層薄的第一覆蓋層151。在另一實施例中,基底110可以被犧牲層(未繪出)覆蓋,以避免磊晶在其上生長。
步驟28為在鰭片結構之上形成閘極介電層和閘極電極層,如第6A、6B和6C圖所示。第6A圖為沿著第1圖的線Y-Y的Z平面,第6B圖為沿著第1圖的線X-X的Z平面,第6C圖為沿著第1圖的線X-X的Y平面。
參閱第6A、6B和6C圖,可藉由熱氧化、CVD、濺鍍或任何其他習知用於形成閘極介電層的方法來形成閘極介電層170。在其他實施例中,閘極介電層170包含的介電材料具有高介電常數(k值),例如為大於3.9。此材料可包含氮化矽、氮氧化物(oxynitrides)、金屬氧化物如HfO2、HfZrOx、HfSiOx、HfTiOx、HfAlOx和類似的材料、前述之組合,以及前述之多層結構。在另一實施例中,閘極介電層170可具有由金屬氮化物材料形成的覆蓋層,例如氮化鈦(titanium nitride)、氮化鉭(tantalum nitride)或氮化鉬(molybdenum nitride),其厚度從1nm至20nm。
在閘極介電層170形成之後,可形成閘極電極層180。閘極電極層180包括導電材料,且可選自於包括多晶矽(poly-Si)、多晶矽鍺(poly-SiGe)、金屬氮化物(metallic nitrides)、金屬矽化物(metallic silicides)、金屬氧化物(metallic oxides)以及金屬的群組。金屬氮化物的例子包含氮化鎢、氮化鉬、氮化鈦、氮化鉭或前述之組合;金屬矽化物的例子包含矽化鎢、矽化鈦、矽化鈷、矽化鎳、矽化鉑、矽化鉺(erbium silicide)或前述之組合;金屬氧化物的例子包含氧化釕(ruthenium oxide)、氧化銦錫或前述之組合;金屬的例子包含鎢、鈦、鋁、銅、鉬、鎳、鉑等。
可藉由CVD、濺鍍沈積或其他習知用於沈積導電材料的技術沈積閘極電極層180,閘極電極層180的厚度範圍可在約200至約400之間。閘極電極層180的頂部表面通常為非平面的頂部表面,並且在閘極電極層180圖案化或閘極蝕刻之前可以是平面的。在閘極電極層180內可導入或不導入離子,例如可藉由離子佈植技術將離子導入。
步驟30為形成閘極結構,如第7A、7B和7C圖所示。第7A圖為沿著第1圖的線Y-Y的Z平面,第7B圖為沿著第1圖的線X-X的Z平面,第7C圖為沿著第1圖的線X-X的Y平面。
參閱第7A、7B和7C圖,將閘極介電層170和閘極電極層180圖案化形成閘極結構200,並且定義鰭片結構的第一部份230(參閱第7C圖)、鰭片結構的第二部份231(參閱第7C圖),以及位於鰭片結構150內,在閘極介電層170底下的通道區205(參閱第7B圖)。可藉由在閘極電極層180上沈積與圖案化閘極遮罩(未繪出)而形成閘極結構200,例如使用習知的沈積與微影技術。閘極遮罩可使用常用的遮罩材料,例如但不限定為光阻材料、氧化矽、氮氧化矽以及/或氮化矽。可使用電漿蝕刻方式蝕刻閘極介電層170和閘極電極層180,以形成如第7B和7C圖所示之圖案化的閘極結構200。
可藉由佈植製程220對鰭片結構的第一部份230和鰭片結構的第二部份231進行摻雜,以植入適當的摻雜物,藉此在鰭片結構150內補充相配的摻雜物,例如,可植入p型摻雜物,如硼、鎵、銦或類似的元素,另外,可植入n型摻雜物,如磷、砷、銻或類似的元素。可使用閘極堆疊作為遮罩,對第一部份230和第二部份231進行離子植入,在一實施例中,被植入的摻雜離子的程度從1e18離子數/立方公分(ions/cm3)至1e20離子數/立方公分(ions/cm3)。
步驟32為形成閘極間隙壁,如第8A、8B和8C圖所示。第8A圖為沿著第1圖的線Y-Y的Z平面,第8B圖為沿著第1圖的線X-X的Z平面,第8C圖為沿著第1圖的線X-X的Y平面。
參閱第8A、8B和8C圖,可在閘極結構200的相反側面上形成閘極間隙壁240和241,閘極間隙壁240和241通常藉由在先前形成的結構上全面性地沈積(blanket depositing)間隙壁層(未繪出)而形成,間隙壁層可包括SiN、氮氧化物、SiC、SiON、氧化物以及類似的材料,並且可藉由形成這些材料層的方法形成,例如化學氣相沈積(CVD)、電漿輔助化學氣相沈積(plasma enhanced CVD)、濺鍍以及其他習知的方法。然後將閘極間隙壁240和241圖案化,較佳為藉由非等向性蝕刻從結構的水平表面移除間隙壁層。閘極間隙壁240和241可具有相同的厚度250(參閱第8B和8C圖),其範圍可從1.5nm至40nm。
步驟34為在鰭片結構內形成凹陷作為源極與汲極結構,如第9A、9B和9C圖所示。第9A圖為沿著第1圖的線Y-Y的Z平面,第9B圖為沿著第1圖的線X-X的Z平面,第9C圖為沿著第1圖的線X-X的Y平面。
參閱第9A、9B和9C圖,鰭片結構150的第一部份230和第二部份231被移除或形成凹陷,形成源極凹陷270和汲極凹陷271。在一實施例中,藉由等向性的定向蝕刻(isotropic orientation dependent etching)製程260形成源極凹陷270和汲極凹陷271,可使用氫氧化四甲基銨(tetramethylammonium hydroxide;TMAH)作為蝕刻劑,所形成的源極凹陷270和汲極凹陷271的深度280(參閱第9B圖)範圍可從0nm至150nm。
步驟36為形成源極與汲極結構,如第10A、10B和10C圖所示。第10A圖為沿著第1圖的線Y-Y的Z平面,第10B圖為沿著第1圖的線X-X的Z平面,第10C圖為沿著第1圖的線X-X的Y平面。
參閱第10A、10B和10C圖,未摻雜的磊晶層290和291可分別在源極凹陷270和汲極凹陷271內形成,未摻雜的磊晶層290和291可避免重摻雜的磊晶層300/301與鰭片結構150之間的漏電流,可藉由選擇性的磊晶成長(SEG)形成未摻雜的磊晶層290和291,並且可參考上述討論的第5A、5B和5C圖的第一覆蓋層151的形成方法及材料。
在未摻雜的磊晶層290和291形成之後,形成重摻雜的磊晶層300和301,完成源極結構400與汲極結構401。可藉由選擇性的磊晶成長(SEG)形成重摻雜的磊晶層300和301,並且可參考上述討論的第5A、5B和5C圖的第一覆蓋層151的形成方法及材料。可用p型摻雜物或n型摻雜物對重摻雜的磊晶層300和301進行摻雜,其取決於鰭式場效電晶體(FinFET)元件所需的型態。在NMOS的實施例中,n型離子植入的程度從3e18離子數/立方公分(ions/cm3)至5e20離子數/立方公分(ions/cm3)。在PMOS的實施例中,p型離子植入的程度從3e18離子數/立方公分(ions/cm3)至5e20離子數/立方公分(ions/cm3)。
參閱第10A、10B和10C圖,在另一實施例中,形成源極結構400與汲極結構401,並藉由第一覆蓋層151在形成的通道層上給予張力(strain)。在此實施例中,可生成源極結構400與汲極結構401以形成應力器(stressor),在位於閘極結構200底下藉由第一覆蓋層151形成的通道層上給予應力。在一實施例中,鰭片結構150包括矽,然後可經由選擇性的磊晶成長(SEG)製程形成源極結構400與汲極結構401,其材料例如為矽鍺、碳化矽或類似的材料,具有與矽不同的晶格常數。在源極結構400與汲極結構401內的應力器的材料與藉由第一覆蓋層151形成的通道層的材料之間的晶格不匹配可在通道層內給予應力,其會增加載子移動率以及元件的整體效能。源極結構400與汲極結構401可經由上述討論的佈植方法進行摻雜,或者當材料成長時藉由原位摻雜進行摻雜。
第11A、11B和11C圖顯示另一實施例的剖面圖,其中源極與汲極結構包括輕摻雜區和重摻雜區,其中第11A圖為沿著第1圖的線Y-Y的Z平面,第11B圖為沿著第1圖的線X-X的Z平面,第11C圖為沿著第1圖的線X-X的Y平面。
在此實施例中,藉由鰭片結構150的凹陷部分以及在凹陷內的磊晶成長材料(參閱第9A至10C圖)取代源極結構400與汲極結構401的形成,源極結構400包括第一輕摻雜區350和第一重摻雜區360,汲極結構401包括第二輕摻雜區351和第二重摻雜區361。回到第7A、7B和7C圖,在閘極結構200形成之後,鰭片的第一部份230和鰭片的第二部份231藉由佈植製程220進行輕摻雜,以植入適當的摻雜物,藉此在鰭片結構150內補入相配的摻雜物,摻雜物離子植入的程度從1e13離子數/立方公分(ions/cm3)至2e18離子數/立方公分(ions/cm3)。在佈植製程220進行之後,形成閘極間隙壁240和241(參閱第8A、8B和8C圖)。在閘極間隙壁形成之後,鰭片的第一部份230和鰭片的第二部份231藉由植入摻雜離子的程度從5e19至2e21離子數/立方公分(ions/cm3)而成為重摻雜,以形成輕摻雜區350和351以及重摻雜區360和361。輕摻雜區主要在閘極間隙壁底下,而重摻雜區則沿著鰭片結構150在閘極間隙壁的外面。
第12A圖顯示NMOS空乏型(depletion-mode)鰭式場效電晶體(FinFET)實施例的剖面圖,其中第12A圖為沿著線Y-Y的Z平面。為了形成此實施例,鰭片結構150為重摻雜的p型(參閱上述的第3A至3C圖),並且源極與汲極結構400和401為重摻雜的n型(參閱上述的第10A至10C圖),第一覆蓋層151可以是輕摻雜的n型或p型,此型態具有n型功函數閘極金屬閘極,將作為NMOS空乏型FinFET。通道載子會被重p型摻雜的鰭片結構150排斥,並且會待在被第一覆蓋層151定義的閘極底下的薄層內。另外,為了形成PMOS空乏型鰭式場效電晶體(FinFET)的實施例,鰭片結構150為重摻雜的n型,並且源極與汲極結構400和401為重摻雜的p型,第一覆蓋層151可以與NMOS型態內的摻雜相同,此型態具有p型功函數閘極金屬閘極,將作為PMOS空乏型FinFET。通道載子會被重n型摻雜的鰭片結構150排斥,並且會待在被第一覆蓋層151定義的閘極底下的薄層內。在上述兩個實施例中,覆蓋層被植入n型離子或p型離子的程度從1e15離子數/立方公分(ions/cm3)至2e18離子數/立方公分(ions/cm3),或者覆蓋層內未植入任何離子。
第12B圖顯示NMOS空乏型鰭式場效電晶體(FinFET)的另一實施例的剖面圖,其中第12B圖為沿著線Y-Y的Z平面。此實施例與第12A圖的實施例相似,除了取代只有一層的覆蓋層(參閱第12A圖)之外。此實施例具有第二覆蓋層152,其介於鰭片結構150與第一覆蓋層151之間,第二覆蓋層152在鰭片結構150與第一覆蓋層151之間提供擴散阻障。在一實施例中,形成第一覆蓋層151的材料之能帶間隙可小於、等於或大於形成鰭片結構150的材料之能帶間隙,此擴散阻障可以讓鰭片結構150是正向偏壓(forward biased),以調整FinFET的臨界電壓。沒有擴散阻障,鰭片結構150只能是反向偏壓(reverse biased)。
如前述第5A至5C圖所討論,第二覆蓋層152在磊晶製程中於鰭片結構150的頂部表面與側面上形成,在第二覆蓋層152形成之後,第一覆蓋層151磊晶地成長在第二覆蓋層152之上。第二覆蓋層152不是用碳進行重摻雜,就是由載子阻障材料,例如用於n-Si的SiGe、用於n-GaAs的AlGaAs以及類似的材料製成。如果第二覆蓋層152用碳進行摻雜,其可以植入的碳離子的程度從1e20離子數/立方公分(ions/cm3)至1e21離子數/立方公分(ions/cm3)。另外,為了形成PMOS空乏型鰭式場效電晶體(FinFET)的實施例,鰭片結構150為重摻雜的n型,並且源極與汲極結構400和401為重摻雜的p型,第一覆蓋層151和第二覆蓋層152都可以與他們在上述NMOS型態內的摻雜相同,並且當搭配p型功函數閘極金屬閘極時,將作為PMOS空乏型FinFET。通道載子會被重n型摻雜的鰭片結構150排斥,並且會待在被第一覆蓋層151定義的閘極底下的薄層內。在上述兩個實施例中,覆蓋層被植入n型離子或p型離子的程度從1e15離子數/立方公分(ions/cm3)至2e18離子數/立方公分(ions/cm3),或者覆蓋層未植入任何離子。
第12A和12B圖的實施例都可以在閘極底下達到薄的通道,此薄的通道讓閘極具有改善的靜電控制,鰭片結構150也可以經由基底110施加偏壓,其可以調整FinFET的臨界電壓,調整臨界電壓的能力讓此FinFET可以應用在超低、低以及標準的電壓設計中。
第13A圖顯示NMOS累積型(accumulation-mode)鰭式場效電晶體(FinFET)實施例的剖面圖,其中第13A圖為沿著線Y-Y的Z平面。在此實施例中,鰭片結構150可植入p型離子的程度從3e18離子數/立方公分(ions/cm3)至5e18離子數/立方公分(ions/cm3),第一覆蓋層151可參閱第5A至5C圖以上述討論的方式形成。在此實施例中,覆蓋層可植入n型離子的程度從3e18離子數/立方公分(ions/cm3)至5e20離子數/立方公分(ions/cm3),此型態具有p型功函數閘極金屬閘極,將作為NMOS累積型FinFET。
第13B圖顯示NMOS累積型鰭式場效電晶體(FinFET)的另一實施例的剖面圖,其中第13B圖為沿著線Y-Y的Z平面。取代了只有一層覆蓋層(參閱第13A圖)的實施例,此實施例具有第二覆蓋層152,第二覆蓋層152在鰭片結構150與第一覆蓋層151之間形成,以作為擴散阻障,第二覆蓋層152的形成如前述所討論,參閱第12B圖。第二覆蓋層152不是用碳進行重摻雜,就是由載子阻障材料,例如用於n-Si的SiGe、用於n-GaAs的AlGaAs以及類似的材料製成。如果第二覆蓋層152摻雜碳,其可以植入的碳離子的程度從1e20離子數/立方公分(ions/cm3)至1e21離子數/立方公分(ions/cm3)進行佈植。第一覆蓋層151可參閱第5A至5C圖,以如上述討論的方式形成。在此實施例中,第一覆蓋層151可植入的n型離子的程度從3e18離子數/立方公分(ions/cm3)至5e20離子數/立方公分(ions/cm3),此型態具有p型功函數閘極金屬閘極,將作為NMOS累積型FinFET。
第13C圖顯示NMOS累積型鰭式場效電晶體(FinFET)的又另一實施例的剖面圖,其中第13C圖為沿著線Y-Y的Z平面。取代了具有均勻摻雜的鰭片結構(參閱第13B圖)的實施例,在此實施例中,鰭片結構150具有內側部分157和外側部分158。最初形成鰭片結構150,並且參閱第3A至4C圖,以如前述討論的相同方式進行摻雜,為了對外側部分158進行摻雜,鰭片結構150經過電漿浸潤離子佈植(plasma immersion ion implantation;PIII)製程形成鰭片結構的薄層,其包括外側部分158。外側部分158可輕摻雜n型或p型的程度從1e13離子數/立方公分(ions/cm3)至5e17離子數/立方公分(ions/cm3)。第二覆蓋層152在鰭片結構150與第一覆蓋層151之間形成,以作為擴散阻障,第二覆蓋層152的形成如前述所討論,參閱第12B圖。第二覆蓋層152不是用碳進行重摻雜,就是由載子阻障材料,例如用於n-Si的SiGe、用於n-GaAs的AlGaAs以及類似的材料製成。如果第二覆蓋層152摻雜碳,其可以植入的碳離子的程度從1e20離子數/立方公分(ions/cm3)至1e21離子數/立方公分(ions/cm3)。第一覆蓋層151以如上述討論的方式形成,參閱第5A至5C圖。在此實施例中,第一覆蓋層151可植入的n型離子的程度從3e18離子數/立方公分(ions/cm3)至5e20離子數/立方公分(ions/cm3)。輕摻雜的外側部分158與第二覆蓋層152結合而作為擴散阻障,其有助於將通道載子局限在第一覆蓋層151內,此型態具有p型功函數閘極金屬閘極,將作為NMOS累積型FinFET。
第13D圖顯示NMOS累積型鰭式場效電晶體(FinFET)的另一實施例的剖面圖,其中第13D圖為沿著線Y-Y的Z平面。取代了內側與外側部分被第一與第二覆蓋層圍繞的鰭片結構(參閱第13C圖)之實施例,在此實施例中,外側部分158以碳進行重摻雜,並且只被第一覆蓋層151圍繞,以碳重摻雜的外側部分158提供擴散阻障(參閱第12B圖的描述),因此不需要第二覆蓋層。第一覆蓋層151參閱第5A至5C圖,以如上述討論的方式形成,在此實施例中,第一覆蓋層151可植入的n型離子的程度從3e18離子數/立方公分(ions/cm3)至5e20離子數/立方公分(ions/cm3)。此型態具有p型功函數閘極金屬閘極,將作為NMOS累積型FinFET。
雖然本發明已揭露較佳實施例如上,然其並非用以限定本發明,在此技術領域中具有通常知識者當可瞭解,在不脫離本發明之精神和範圍內,當可做些許更動與潤飾。例如,有多種方法可用於沈積材料而形成上述結構,可依據本揭示,使用任何可達到與此所述之相對應的實施例大抵上相同結果的沈積方法。因此,本發明之保護範圍當視後附之申請專利範圍所界定為準。
20...形成鰭式場效電晶體的方法
22、24、26、28、30、32、34、36...方法20的各步驟
50...鰭式場效電晶體
110...基底
130...半導體層
140、220...佈植製程
150...鰭片結構
151...第一覆蓋層
152...第二覆蓋層
157...鰭片結構的內側部分
158...鰭片結構的外側部分
160...鰭片結構的寬度
161...鰭片結構的高度
170...閘極介電層
180...閘極電極層
200...閘極結構
205...通道區
230...鰭片結構的第一部份(源極區)
231...鰭片結構的第二部份(汲極區)
240、241...閘極間隙壁
250...閘極間隙壁的厚度
260...等向性定向蝕刻製程
270...源極凹陷
271...汲極凹陷
280...源極凹陷和汲極凹陷的深度
290、291...未摻雜的磊晶層
300、301...重摻雜的磊晶層
350...第一輕摻雜區
351...第二輕摻雜區
360...第一重摻雜區
361...第二重摻雜區
400...源極結構
401...汲極結構
第1圖係顯示依據一實施例,鰭式場效電晶體的透視圖;
第2圖係顯示依據一實施例,形成鰭式場效電晶體的方法之流程圖;
第3A-11C圖係顯示依據一實施例,製造鰭式場效電晶體的中間階段之剖面示意圖;
第12A和12B圖係顯示依據一實施例,空乏型鰭式場效電晶體的剖面示意圖;以及
第13A-13D圖係顯示依據一實施例,累積型鰭式場效電晶體的剖面示意圖。
110...基底
151...第一覆蓋層
157...鰭片結構的內側部分
158...鰭片結構的內側部分
170...閘極介電層
180...閘極電極層
Claims (13)
- 一種半導體元件,包括:一基底;一鰭片結構,升高於該基底之上,該鰭片結構包括:一內側部分,具有一第一能帶間隙和一第一結晶方向;以及一外側部分,設置在該內側部分的一頂部表面與複數個側面上,該外側部分具有一第二能帶間隙和一第二結晶方向,該第二能帶間隙小於或等於該第一能帶間隙。
- 如申請專利範圍第1項所述之半導體元件,其中該第二結晶方向與該第一結晶方向相同。
- 如申請專利範圍第1項所述之半導體元件,其中該鰭片結構更包括一中間部分介於該內側部分與該外側部分之間,該中間部分具有一第三能帶間隙和一第三結晶方向,該第三能帶間隙大於該第一能帶間隙,且該第三結晶方向與該第二結晶方向相同。
- 一種半導體元件,包括:一基底;一非平面電晶體,設置於該基底上,該非平面電晶體包括:一鰭片結構,具有一第一結晶方向,該鰭片結構含有一第一導電型的一雜質;一源極與汲極區,設置在該鰭片結構內,該源極含有一第二導電型的一雜質,該第二導電型與該第一導電型不同;以及一覆蓋層,設置在該鰭片結構的一頂部表面與複數個側面上,該覆蓋層具有一第二結晶方向和小於或等於該鰭片結構的一能帶間隙。
- 如申請專利範圍第4項所述之半導體元件,其中該半導體元件更包括一擴散阻障層,該擴散阻障層介於該鰭片結構與該覆蓋層之間,且具有一第三結晶方向。
- 如申請專利範圍第5項所述之半導體元件,其中該第二結晶方向與該第一結晶方向相同,且該第三結晶方向與該第二結晶方向相同。
- 如申請專利範圍第5項所述之半導體元件,其中該鰭片結構更包括:一內側部分,含有該第一導電型的一雜質;以及一外側部分,介於該內側部分與該擴散阻障層之間,該外側部分具有低於該內側部分和該擴散阻障層的一較低濃度的一雜質。
- 如申請專利範圍第4項所述之半導體元件,其中該覆蓋層含有該第二導電型的一雜質,該雜質的一濃度低於該源極與汲極區內的該第二導電型的該雜質的該濃度。
- 如申請專利範圍第4項所述之半導體元件,其中該覆蓋層不含有該第一導電型的雜質。
- 如申請專利範圍第4項所述之半導體元件,其中該鰭片結構更包括:一內側部分,含有一第一濃度的該第一導電型的一雜質;以及一外側部分,介於該內側部分與該擴散阻障層之間,該外側部分具有大於該覆蓋層的一能帶間隙;其中該覆蓋層含有一第二濃度的一雜質,該第二濃度低於該第一濃度。
- 一種半導體元件的形成方法,包括:提供一基底;在該基底的一頂部表面上形成一半導體鰭片結構;以及在該半導體鰭片結構的一頂部表面與複數個側面上形成一覆蓋層,該覆蓋層具有小於或等於該半導體鰭片結構的一能帶間隙。
- 如申請專利範圍第11項所述之半導體元件的形成方法,更包括在該半導體鰭片結構上磊晶地成長一擴散阻障層,其中形成該覆蓋層的步驟包括在該擴散阻障層上磊晶地成長該覆蓋層。
- 如申請專利範圍第11項所述之半導體元件的形成方法,其中形成該半導體鰭片結構的步驟更包括在該半導體鰭片結構的一內側部分內電漿佈植摻雜物,達到一高於該半導體鰭片結構的一外側部分的較高濃度,其中該內側部分具有一小於該外側部分的能帶間隙。
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US10163657B1 (en) | 2017-08-25 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of manufacture |
TWI646584B (zh) * | 2017-08-25 | 2019-01-01 | 台灣積體電路製造股份有限公司 | 半導體裝置及其形成方法 |
US10741412B2 (en) | 2017-08-25 | 2020-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gate structure of semiconductor device |
US11361977B2 (en) | 2017-08-25 | 2022-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gate structure of semiconductor device and method of manufacture |
Also Published As
Publication number | Publication date |
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CN102983165A (zh) | 2013-03-20 |
KR101371841B1 (ko) | 2014-03-07 |
CN102983165B (zh) | 2015-06-10 |
US8890207B2 (en) | 2014-11-18 |
US20150079752A1 (en) | 2015-03-19 |
US20130056795A1 (en) | 2013-03-07 |
TWI496291B (zh) | 2015-08-11 |
US9318322B2 (en) | 2016-04-19 |
KR20130026974A (ko) | 2013-03-14 |
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