CN107665862B - 通过扩散掺杂和外延轮廓成型 - Google Patents
通过扩散掺杂和外延轮廓成型 Download PDFInfo
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- CN107665862B CN107665862B CN201710561145.2A CN201710561145A CN107665862B CN 107665862 B CN107665862 B CN 107665862B CN 201710561145 A CN201710561145 A CN 201710561145A CN 107665862 B CN107665862 B CN 107665862B
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- doped dielectric
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- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
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Abstract
一种方法包括蚀刻半导体衬底以形成第一沟槽和第二沟槽。在第一沟槽和第二沟槽之间留下半导体衬底的剩余部分作为半导体区。在半导体区的侧壁上和半导体区的顶面上方形成掺杂的介电层。掺杂的介电层包括掺杂剂。第一沟槽和第二沟槽填充有介电材料。然后,执行退火,并且掺杂的介电层中的p型掺杂剂或n型掺杂剂被扩散至半导体区中以形成扩散的半导体区。本发明实施例涉及形成鳍式场效应晶体管(FinFET)的方法,具体地涉及通过扩散掺杂和外延轮廓成型。
Description
技术领域
本发明实施例涉及形成鳍式场效应晶体管(FinFET)的方法,具体地涉及通过扩散掺杂和外延轮廓成型。
背景技术
集成电路(IC)材料和设计的技术进步已经产生了数代的IC,其中每一代都比前一代具有更小和更复杂的电路。在IC演化过程中,功能密度(例如,每个芯片面积中的互连器件的数量)普遍增大而几何尺寸缩小。这种按比例缩小工艺通过增加生产效率和降低相关成本来提供益处。
这种按比例缩小工艺还增加了处理和制造IC的复杂性,并且为了实现这些进步,需要IC处理和制造方面的相似发展。例如,已经引入鳍式场效应晶体管(FinFET)以代替平面晶体管。正在开发FinFET的结构和制造FinFET的方法。
FinFET的形成通常涉及形成半导体鳍、注入半导体鳍以形成阱区、在半导体鳍上形成伪栅电极、蚀刻半导体鳍的端部以及执行外延以再生源极/漏极区。
发明内容
根据本发明的一个实施例,提供了一种形成鳍式场效应晶体管(FinFET)的方法,包括:蚀刻半导体衬底以形成第一沟槽和第二沟槽,其中,在所述第一沟槽和所述第二沟槽之间留下所述半导体衬底的剩余部分作为半导体区;在所述半导体区的侧壁上和所述半导体区的顶面上方形成掺杂的介电层,其中,所述掺杂的介电层包括掺杂剂;用介电材料填充所述第一沟槽和所述第二沟槽;以及执行退火,其中,所述掺杂的介电层中的所述掺杂剂扩散至所述半导体区内以形成扩散的半导体区。
根据本发明的另一实施例,还提供了一种形成鳍式场效应晶体管(FinFET)的方法,包括:蚀刻半导体衬底以形成半导体区,所述半导体区包括半导体基底以及位于所述半导体基底上方并且连接至所述半导体基底的多个半导体条,其中,延伸至所述半导体衬底内的第一沟槽和第二沟槽位于所述半导体区的相对两侧上;用介电材料填充所述第一沟槽和所述第二沟槽以形成隔离区;凹进所述隔离区,其中,所述多个半导体条的顶部形成多个半导体鳍;在所述多个半导体鳍的第一部分上形成栅极堆叠件;蚀刻所述多个半导体鳍的未被所述栅极堆叠件覆盖的第二部分;以及从所述半导体区的剩余部分执行外延以形成外延源极/漏极区。
根据本发明的又一实施例,还提供了一种形成鳍式场效应晶体管(FinFET)的方法,包括:蚀刻半导体衬底以形成由沟槽彼此分离的第一半导体区和第二半导体区;形成掺杂有具有第一导电类型的第一掺杂剂的第一掺杂的介电层,其中,在所述第一半导体区和所述第二半导体区的侧壁和顶面上形成所述第一掺杂的介电层;去除所述第一掺杂的介电层的位于所述第一半导体区上的部分;形成掺杂有具有与所述第一导电类型相反的第二导电类型的第二掺杂剂的第二掺杂的介电层,其中,所述第二掺杂的介电层形成在所述第一半导体区的所述侧壁和所述顶面上并且覆盖所述第一掺杂的介电层的位于所述第二半导体区上的剩余部分;在所述沟槽内以及在所述第一掺杂的介电层和所述第二掺杂的介电层上方填充介电材料;以及执行退火,其中,所述第二掺杂剂扩散至所述第一半导体区的第一表面层内,并且所述第一掺杂剂扩散至所述第二半导体区的第二表面层内。
附图说明
当结合附图进行阅读时,根据下面详细的描述可以更好地理解本发明的实施例。应该强调的是,根据工业中的标准实践,对各种部件没有按比例绘制并且仅仅用于说明的目的。实际上,为了清楚的讨论,各种部件的尺寸可以被任意增大或缩小。
图1至图14A是根据一些实施例的鳍式场效应晶体管(FinFET)的形成中的中间阶段的截面图和立体图。
图14B示出了根据一些实施例的FinFET的源极/漏极区的截面图。
图15和图16示出了根据一些实施例的FinFET的源极/漏极区的形成中的中间阶段的截面图。
图17示出了根据一些实施例的FinFET的截面图。
图18示出了根据一些实施例的用于形成FinFET的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件形成为直接接触的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实例中重复参考标号和/或字母。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为了便于描述,在此可以使用诸如“在...下面”、“在...下方”、“下部”、“在...上面”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外,空间相对位置术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),并且本文使用的空间相对描述符可以同样地作相应的解释。
根据各种示例性实施例提供了鳍式场效应晶体管(FinFET)及其形成方法。示出了形成FinFET的中间阶段。讨论了一些实施例的变型。贯穿各个视图和说明性实施例,相同的参考标号用于指示相同的元件。
图1至图14A示出了根据一些实施例的FinFET的形成中的中间阶段的截面图和立体图。图1至图14A中所示的步骤也在图18中所示的工艺流程图200中示意性地示出。
图1示出了是晶圆100的一部分的衬底20的截面图。衬底20可以是块状衬底或绝缘体上半导体衬底。根据本发明的一些实施例,衬底20是由从但不限制于硅锗、硅碳、锗、以及诸如GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP等的III-V族化合物半导体材料等选择的半导体材料形成的。衬底20可轻掺杂p型或n型杂质。晶圆100包括N型金属氧化物半导体(NMOS)区10A和P型金属氧化物半导体(PMOS)区10B,其中,NMOS晶体管和PMOS晶体管分别被形成。
在衬底20上形成垫氧化物22和硬掩模24。根据本发明的一些实施例,垫氧化物22是由可以通过氧化半导体衬底20的表面层形成的氧化硅形成。硬掩模24可以由氮化硅、氮氧化硅、碳化硅、碳氮化硅等形成。根据本发明的一些实施例,硬掩模24,例如,使用低压化学汽相沉积(LPCVD)由氮化硅形成。根据本发明的其它实施例,通过硅的热氮化、等离子增强化学汽相沉积(PECVD)、或等离子体阳极氮化形成掩模层24。
接下来,如图2所示,图案化硬掩模24、垫氧化物22、以及衬底20以形成沟槽26,其间,硬掩模24首先被图案化,并且然后用作蚀刻掩模以图案化下面的垫氧化物22和衬底20。因此,半导体条128A和128B分别形成在NMOS区10A和PMOS区10B中。对应的步骤示出为图18中所示的工艺流程图中的步骤202。沟槽26延伸至半导体衬底20中,并且将半导体条128A和128B彼此分隔开。在晶圆100的顶视图中,半导体条128A和128B中的每个或一些可以由对应的沟槽26环绕。根据本发明的一些实施例,沟槽26的深度D1在约100nm和约150nm之间的范围内。应当理解,贯穿说明书中记载的值是实例,并且也可以采用不同的值而不改变本发明的原理。
根据本发明的一些实施例,半导体条128A和128B称为冠形半导体条。半导体条128A包括半导体基底130A和在基底130A上方的半导体条132A。半导体条128B包括半导体基底130B和在基底130B上方的半导体条132B。尽管图2示出了在基底130A(或130B)上方具有三个半导体条132A(或132B),取决于得到的FinFET的期望的驱动电流,对应的基底130A和130B的每个上的半导体条132A和132B的数量可以是诸如1、2、3、4、5或更多的任何整数。基底130A的顶面130A'和基底130B的顶面130B'基本上可以是平坦的,或可以是弯曲的(具有凹陷)。例如,半导体条132A和/或132B的鳍宽度W1可以在约10nm和约20nm之间的范围内。
根据本发明的一些实施例,半导体条128A和/或128B的形成包括:蚀刻半导体衬底20以形成条132A和132B,形成牺牲间隔件层(未示出)以覆盖半导体条132A和132B的侧壁,以及使用牺牲间隔件层和硬掩模24的组合作为蚀刻掩模以进一步蚀刻半导体衬底20。相邻的半导体条132A彼此靠近,并且因此半导体衬底20的相邻的半导体鳍132A/132B之间的部分未被向下蚀刻。结果,形成基底130A和130B。然后,去除牺牲间隔件层。
图3和图4示出了在冠形半导体条128A和128B的暴露表面上形成的牺牲衬垫氧化物层34的形成和去除。参考图3,牺牲衬垫氧化物层34形成为共形层,共形层的水平部分和垂直部分具有彼此接近的厚度。根据本发明的一些实施例,通过在含氧环境中,例如,通过局部硅氧化(LOCOS)氧化晶圆100来形成牺牲衬垫氧化物层34,其中,氧气(O2)可以包括在对应的工艺气体中。根据本发明的其它实施例,例如,通过用于氧化暴露的半导体衬底20和冠形半导体条128A和128B的氢气(H2)和氧气(O2)的组合气体或水蒸气,使用原位蒸汽生成(ISSG)形成牺牲衬垫氧化物层34。可以在高于室温的升高的温度下执行ISSG氧化。
然后,例如在湿蚀刻或干蚀刻工艺中去除牺牲衬垫氧化物层34,其中,可以使用NH3(氨)和HF3的组合气体或HF溶液。在图4中示出了得到的结构。结果,再次露出冠形半导体条128A和128B的表面。牺牲衬垫氧化物层34的形成和去除可以造成冠形半导体条128A和128B的表面的有利的再成型。例如,由于突起的氧化速率比平滑部分的氧化速率高,因此可以去除一些不期望的突起。得到的FinFET的性能可以因此得益于牺牲衬垫氧化物层34的形成和去除。
图5示出了沉积为毯式层的n型掺杂的介电层36A的沉积。对应的步骤示出为图18中所示的工艺流程图中的步骤204。根据一些实施例,n型掺杂的介电层36A包括磷,并且可以是磷硅酸盐玻璃(PSG)层。N型掺杂的介电层36A还可以由诸如氧化硅的氧化物、诸如氮化硅的氮化物、或其它介电材料形成。N型掺杂的介电层36A可以掺杂有磷、砷和/或锑。可以使用诸如原子层沉积(ALD)、化学汽相沉积(CVD)等的共形沉积方法沉积N型掺杂的介电层36A。结果,n型掺杂的介电层36A的水平部分的厚度T1和垂直部分的厚度T2彼此接近,例如,厚度T1和厚度T2的差小于厚度T1的约20%(或10%)。根据本发明的一些实施例,n型掺杂的介电层36A是富磷层,其中,在n型掺杂的介电层36A中的磷的原子百分比高于约20%或更高。N型掺杂的介电层36A的厚度T1和T2可以在约和约之间的范围内。此外,比率T2/W1可以在约10%和约18%之间的范围内。
进一步参照图5,形成图案化的光刻掩模以覆盖PMOS区10B,而留下NMOS区10A开放。根据本发明的一些实施例,图案化的光刻掩模包括三层,包括底层(又称为下层)38、底层38上方的中间层40以及中间层40上方的上层42。根据本发明的一些实施例,底层38和上层42是由光刻胶形成的。中间层40可以是由无机材料形成的,无机材料可以是碳化物(诸如碳氧化硅)、氮化物(诸如氮化硅)、氮氧化物(诸如氮氧化硅)、氧化物(诸如氧化硅)等。上层42被图案化以形成开口44,通过开口44去除n型掺杂的介电层36A。
接下来,使用三层作为蚀刻掩模执行各向异性蚀刻。在蚀刻工艺中,使用作为蚀刻掩模的图案化的上层42蚀刻中间层40和底层38的直接位于开口44下面的部分,从而暴露出n型掺杂的介电层36A。在从NMOS区10A去除底层38之后,执行各向同性蚀刻以从NMOS区10A去除n型掺杂的介电层36A的暴露部分。对应的步骤示出为图18中所示的工艺流程图中的步骤206。层36A的蚀刻可以包括湿蚀刻和/或干蚀刻。在干蚀刻中,可以使用诸如HF和Ar的工艺气体。在湿蚀刻中,可以使用诸如H2SO4的蚀刻剂。n型掺杂的介电层36A的位于PMOS区10B中的部分被保护并且不被去除。然后,去除底层38的剩余部分,从而得到如图6中示出的结构。
图7示出了沉积为毯式层的p型掺杂的介电层36B的沉积。对应的步骤示出为图18中所示的工艺流程图中的步骤208。P型掺杂的介电层36B包括诸如硼和/或铟的p型掺杂剂。P型掺杂的介电层36B可以由诸如氧化硅的氧化物、诸如氮化硅的氮化物、或另一介电材料形成。根据本发明的一些实施例,p型掺杂的介电层36B是硼硅酸盐玻璃(BSG)层。可以使用诸如ALD、CVD等的共形沉积方法沉积P型掺杂的介电层36B。结果,p型掺杂的介电层36B的水平部分的厚度T3和垂直部分的厚度T4彼此接近,例如,厚度T3和厚度T4的差小于厚度T3的约20%(或10%)。根据本发明的一些实施例,p型掺杂的介电层36B是富硼层,其中,硼在p型掺杂的介电层36B中的原子百分比高于约35%或更高。p型掺杂的介电层36B的厚度T3和T4可以在与n型掺杂的介电层36A的厚度T1和T2相同的范围内。在NMOS区10A中,p型掺杂的介电层36B可以与冠形半导体条128A和128B的暴露表面物理接触。在PMOS区10B中,p型掺杂的介电层36B通过n型掺杂的介电层36A与下面的冠形半导体条128B分离。
图7还示出了填充分离的半导体条的沟槽的介电材料50的形成。对应的步骤示出为图18中所示的工艺流程图中的步骤210。介电层50可以由氧化硅、碳化硅、氮化硅、或它们的多层形成。介电材料50的形成方法可以选自可流动化学汽相沉积(FCVD)、旋涂、化学汽相沉积(CVD)、原子层沉积(ALD)、高密度等离子体化学汽相沉积(HDPCVD)、LPCVD等。介电材料50可以没有n型和p型掺杂剂。
根据其中使用FCVD的一些实施例,使用含硅前体(例如,三甲硅烷基胺(TSA)或二甲硅烷基胺(DSA)),并且所得到的介电材料50是可流动的(胶状的)。根据本发明的可选实施例,使用基于烷基胺硅烷的前体形成可流动介电材料50。在沉积期间,开通等离子体以激活用于形成可流动氧化物的气态前体。
在形成介电材料50之后,在晶圆100上执行退火步骤。对应的步骤示出为图18中所示的工艺流程图中的步骤212。如果介电材料50在此时是可流动的,则介电材料50将被转换为固态介电材料。退火还改善了介电材料50的质量,例如,导致介电材料50的密度的增加。根据本发明的一些实施例,使用选自熔炉退火、腔室退火、管式退火等的方法执行退火。例如,当执行熔炉退火时,退火温度可以在约750℃和约1050℃之间,并且退火持续时间可以在约10分钟和约30分钟之间的范围内。可以在含氧环境中或在不含氧(O2、O3等)环境中执行退火。
在NMOS区10A中,退火导致诸如硼的p型掺杂剂扩散至冠形半导体条128A的表面层内。因此,如图8中所示,形成p型区52A。退火造成p型掺杂剂扩散的深度深于半导体条132A的宽度W1的一半。因此,半导体条132A的整体和半导体基底130A的表面层被扩散以形成p型扩散区52A。又如图8中所示,在PMOS区10B中,退火导致层36A中的n型掺杂剂和层36B中的p型掺杂剂扩散以形成扩散区52B。然而,由于层36B位于层36A上方,并且远离冠形半导体条128B,所以n型掺杂剂浓度高于p型掺杂剂浓度,并且扩散区52B是n型区。此外,层36A中的n型掺杂剂浓度可以被调节以高于层36B中的p型掺杂剂浓度以确保扩散区52B具有n型。相似地,退火导致n型掺杂剂扩散深于W1/2。因此,半导体条132B的整体和半导体基底130B的表面层是n型区。根据本发明的一些实施例,扩散深度D2在约5nm和约20nm之间的范围内。
根据本发明的可选实施例,不是形成n型掺杂的介电层36A和将其从区10A去除并且然后毯式形成p型掺杂的介电层36B,而是p型掺杂的介电层36B被毯式形成并且从区10A去除,随后形成作为毯式层的n型掺杂的介电层36A。得到的扩散区52A和52B还分别具有p型和n型。
然后,又如图9中所示,执行诸如化学机械抛光(CMP)的平坦化。对应的步骤示出为图18中所示的工艺流程图中的步骤214。层36A和36B的剩余部分以及介电材料形成又称为浅沟槽隔离(STI)区的隔离区54。掩模层24可以用作CMP停止层,并且因此掩模层24的顶面与STI区54的顶面基本上共平面。然后,例如,使用H3PO4作为蚀刻剂去除掩模层24。
在随后的工艺步骤中,例如,分别在NMOS区10A和PMOS区10B中形成n型FinFET和p型FinFET。随后的附图示出了同时表示n型FinFET和p型FinFET的一个FinFET的形成。例如,参照图10,当将要形成的对应的FinFET是n型FinFET时,图10中示出的结构表示NMOS区10A(图9)中示出的结构。因此,扩散区52表示扩散p型区52A,条132表示半导体条132A,以及掺杂的层36表示p型掺杂的介电层36B。此外,冠形半导体条128表示半导体条128A。当将要形成的对应的FinFET是p型FinFET时,图10中示出的结构表示PMOS区10B(图9)中示出的结构。因此,区52表示扩散n型区52B,条132表示半导体条132B,以及掺杂的层36表示n型掺杂的介电层36A和层36A上方的p型掺杂的介电层36B。此外,冠形半导体条128表示半导体条128B。应该理解,在同一晶圆100上和相同的条中兼形成n型FinFET和p型FinFET。
参考图10,使STI区54凹进,并且在同一工艺中还可以去除垫层22(图9)。对应的步骤示出为图18中所示的工艺流程图中的步骤216。可以使用可以是干蚀刻工艺或湿蚀刻工艺的各向同性蚀刻工艺执行STI区54的凹进。STI区54的凹进导致半导体条132的顶部突起于STI区54的顶面上方。突起部分在下文中称为半导体鳍(或突起鳍)56。
图11示出了根据本发明的一些实施例的伪栅极堆叠件58的形成的立体图。对应的步骤示出为图18中所示的工艺流程图中的步骤218。伪栅极堆叠件58可以包括伪栅极电介质60和位于伪栅极电介质60上方的伪栅电极62。伪栅极电介质60可以由氧化硅形成。根据一些实施例,伪栅电极62可以由多晶硅形成。例如,可以由氮化硅形成的硬掩模63可以在伪栅电极62上方形成。
间隔件层64形成为毯式层。根据本发明的一些实施例,使用诸如ALD、CVD等的共形沉积方法形成间隔件层64,从而间隔件层64的侧壁部分具有足够的厚度。间隔件层64的水平部分和垂直部分可以具有基本上相同的厚度,其中,垂直部分的垂直厚度以及水平部分的水平厚度的差小于水平厚度的20%。
间隔件层64的材料可以包括氮化硅、碳氧氮化硅(SiOCN)、或诸如氧化铝的金属氧化物。根据本发明的一些实施例,间隔件层64是由SiOCN形成的,并且可以具有单层结构。在可选实施例中,间隔件层64具有包括多个层的复合结构。例如,间隔件层64可以包括氧化硅层和位于氧化硅层上方的氮化硅层。
参考图12A,执行各向异性蚀刻以去除间隔件层64的水平部分。间隔件层64的剩余的垂直部分在伪栅极堆叠件58的侧壁上形成栅极间隔件66,并且在半导体鳍56的侧壁上形成鳍间隔件68。对应的步骤示出为图18中所示的工艺流程图中的步骤220。图12B示出了图12A中示出的结构的一部分的截面图,其中,从图12A中的垂直面交叉线12B-12B获得该截面图。随后图13至图16中示出的截面图也从如图12A中所示的同一垂直面(穿过半导体鳍56的未覆盖部分)交叉线12B-12B获得。
接下来,如图13所示,在蚀刻工艺中使半导体鳍56的暴露部分凹进。对应的步骤示出为图18中所示的工艺流程图中的步骤222。在同一工艺中,还回蚀刻鳍间隔件68,并且减小鳍间隔件68的高度。可以调节工艺条件(诸如半导体鳍56的蚀刻速率和鳍间隔件68的蚀刻速率之间的蚀刻选择性)从而降低鳍间隔件68,并且留下鳍间隔件68的一些剩余。在半导体鳍56的凹进结束之后,还有半导体鳍56(或半导体条132)的一些剩余部分留下,并且一些STI部分54保留在半导体基底130的正上方。在蚀刻之后,半导体鳍56的位于伪栅极堆叠件62正下面的部分保留(图12A)。通过调节诸如蚀刻剂、温度、蚀刻持续时间、和鳍间隔件56的材料的蚀刻条件,剩余的鳍56的顶面可以在如由虚线70表示的各个位置处。
参照图14A和图14B,执行外延以再生长外延区72,外延区72从剩余的鳍56或条132生长,但不从鳍间隔件68和STI区54生长。对应的步骤示出为图18中所示的工艺流程图中的步骤224。外延区72形成得到的FinFET的源极/漏极区。当对应的FinFET是p型FinFET时,外延区72可以包括掺杂有硼的硅锗,或当对应的FinFET是n型FinFET时,外延区72可以包括硅磷或硅碳磷。
图14A示出了当外延区72具有p型时的外延区72的轮廓,并且得到的FinFET是p型FinFET。因此,对应的外延区72是p型FinFET,并且扩散区52和鳍56是n型区。区52/56的掺杂有利地导致它们掺杂剂浓度的增加和它们电阻值的减小。这有利地影响外延区72的轮廓。例如,在鳍56之间形成孔74,并且截面图在截面图中具有圆形形状和/或椭圆形状。角度A1可以在约60度和约100度之间的范围内。孔74的高度H2可以大于对应的宽度W2。
图14B示出了当外延区72具有n型,并且得到的FinFET是n型FinFET时的外延区72的轮廓。因此,对应的外延区72是n型区,并且扩散区52和鳍56是p型区。区52/56的掺杂有利地导致它们掺杂剂浓度的增加和它们电阻值的减小。这有利地影响外延区72的轮廓。例如,孔74在鳍56之间形成,并且孔74的截面图包括圆形底部部分和三角形顶部。如图所示,三角形顶部具有基本上直的边缘。角度A2可以在约60度和约100度之间的范围内。角度A3可以在约130度和约160度之间的范围内。在图14A和图14B中,由于半导体鳍56不在示出平面中,所以使用虚线示出仍然保持在伪栅极堆叠件58(图12A)正下方的半导体鳍56。
图14A和图14B中示出的结构可以形成在同一半导体衬底20上和同一半导体芯片中以改善p型FinFET和n型FinFET的性能。结果发现,当分别为p型FinFET和n型FinFET生成如图14A和图14B中示出的轮廓时,FinFET具有很好的性能。
图15示出了根据可选实施例的在如图12A和图12B示出的半导体鳍56被凹进/蚀刻之后的结构的截面图。根据这些实施例的初始步骤类似于图1至图12A和图12B中示出的步骤,并且不再赘述。调节用于蚀刻半导体鳍56(图12A和图12B)的工艺条件从而去除鳍间隔件68(图12B)、半导体鳍56和下面的半导体条132、以及去除STI区54的高于半导体基底130的部分。因此,去除在基底130上方和在示出的截面图中的所有介电材料。半导体基底130可以不被蚀刻或可以被稍微蚀刻。仍然保持基底130的顶部中的扩散区52。
接下来,如图16中所示,外延区72形成为块状区,其中,在外延区72中不形成孔。外延区72形成最终FinFET的源极/漏极区。在图16中,由于半导体鳍56不在示出平面中,所以使用虚线示出仍然保持在伪栅极堆叠件58(图12A)正下方的半导体鳍56。
随后,执行多个工艺步骤以完成FinFET的形成。在图17中示出示例性FinFET 80。如图12A中示出的伪栅极堆叠件58被替代为替换栅极78。对应的步骤示出为图18中所示的工艺流程图中的步骤226。替换栅极78包括对应的鳍56的顶面和侧壁上的栅极电介质76和栅极电介质76上方的栅电极77。可以通过热氧化形成栅极电介质76,且因此可以包括热氧化硅。栅极电介质76的形成还可包括一个或多个沉积步骤,并且得到的栅极电介质76可以包括高k介电材料或非高k介电材料。然后,栅电极77形成在栅极电介质76上并且可以由金属层形成。这些组件的形成工艺不详细地描述。在源极/漏极区72的表面上形成源极/漏极硅化物区86。源极/漏极接触插塞88形成在层间电介质(ILD)82中,并且电连接至对应的源极/漏极硅化物区86。扩散区52形成FinFET 80的阱区的一部分。
本发明的实施例具有一些有利的特征。通过在前期阶段中掺杂半导体条并且通过在源极/漏极区的形成期间调节半导体鳍的凹进,可以为外延源极/漏极区形成导致改善的性能的期望的轮廓。此外,通过蚀刻多个半导体鳍和生长块状源极/漏极区,减少了源极/漏极电阻,并且改善了FinFET的性能。
根据本发明的一些实施例,一种方法包括蚀刻半导体衬底以形成第一沟槽和第二沟槽。在第一沟槽和第二沟槽之间留下半导体衬底的剩余部分作为半导体区。在半导体区的侧壁上和半导体区的顶面上方形成掺杂的介电层。掺杂的介电层包括掺杂剂。第一沟槽和第二沟槽填充有介电材料。然后,执行退火,并且掺杂的介电层中的p型掺杂剂或n型掺杂剂被扩散至半导体区中以形成扩散的半导体区。
根据本发明的一些实施例,一种方法包括蚀刻半导体衬底以形成包括半导体基底以及在半导体基底上方并且连接至半导体基底的多个半导体条的半导体区。第一沟槽和第二沟槽延伸至半导体衬底中,并且位于半导体区的相对两侧上。
第一沟槽和第二沟槽填充有介电材料以形成隔离区。该方法还包括凹进隔离区,从而多个半导体条的顶部形成多个半导体鳍;在多个半导体鳍的第一部分上形成栅极堆叠件;蚀刻多个半导体鳍的未由栅极堆叠件覆盖的第二部分;以及从半导体区的剩余部分执行外延以形成外延源极/漏极区。
根据本发明的一些实施例,一种方法包括蚀刻半导体衬底以形成通过沟槽彼此分离的第一半导体区和第二半导体区,并且形成掺杂有具有第一导电类型的第一掺杂剂的第一掺杂介电层。在第一半导体区和第二半导体区的侧壁和顶面上形成第一掺杂的介电层。该方法还包括去除第一掺杂的介电层在第一半导体区上的部分并且形成掺杂有具有与第一导电类型相反的第二导电类型的第二掺杂剂的第二掺杂的介电层。在第一半导体区的侧壁和顶面上形成第二掺杂的介电层,并且覆盖第二半导体区上的第一掺杂的介电层的剩余部分。该方法还包括在沟槽中以及在第一掺杂的介电层和第二掺杂的介电层上方填充介电材料,并且执行退火。退火造成第二掺杂剂被扩散至第一半导体区的第一表面层内,并且第一掺杂剂被扩散至第二半导体区的第二表面层内。
根据本发明的一个实施例,提供了一种形成鳍式场效应晶体管(FinFET)的方法,包括:蚀刻半导体衬底以形成第一沟槽和第二沟槽,其中,在所述第一沟槽和所述第二沟槽之间留下所述半导体衬底的剩余部分作为半导体区;在所述半导体区的侧壁上和所述半导体区的顶面上方形成掺杂的介电层,其中,所述掺杂的介电层包括掺杂剂;用介电材料填充所述第一沟槽和所述第二沟槽;以及执行退火,其中,所述掺杂的介电层中的所述掺杂剂扩散至所述半导体区内以形成扩散的半导体区。
在上述方法中,所述半导体区包括半导体基底以及位于所述半导体基底上方并且连接至所述半导体基底的半导体条,并且所述方法还包括:蚀刻所述半导体条;以及从所述半导体区的所述剩余部分执行外延以形成外延半导体区。
在上述方法中,还包括:在所述半导体条的顶部的侧壁上形成间隔件;以及凹进所述半导体条的所述顶部,其中,所述外延半导体区的从所述半导体条的所述剩余部分生长的部分彼此合并。
在上述方法中,所述外延从所述扩散的半导体区生长。
在上述方法中,所述掺杂的介电层中的所述掺杂剂具有n型,并且所述方法还包括在所述退火之前在所述掺杂的介电层上方形成附加的p型掺杂的层。
在上述方法中,形成所述掺杂的介电层包括沉积磷硅酸盐玻璃(PSG)层。
在上述方法中,形成所述掺杂的介电层包括沉积硼硅酸盐玻璃(BSG)层。
根据本发明的另一实施例,还提供了一种形成鳍式场效应晶体管(FinFET)的方法,包括:蚀刻半导体衬底以形成半导体区,所述半导体区包括半导体基底以及位于所述半导体基底上方并且连接至所述半导体基底的多个半导体条,其中,延伸至所述半导体衬底内的第一沟槽和第二沟槽位于所述半导体区的相对两侧上;用介电材料填充所述第一沟槽和所述第二沟槽以形成隔离区;凹进所述隔离区,其中,所述多个半导体条的顶部形成多个半导体鳍;在所述多个半导体鳍的第一部分上形成栅极堆叠件;蚀刻所述多个半导体鳍的未被所述栅极堆叠件覆盖的第二部分;以及从所述半导体区的剩余部分执行外延以形成外延源极/漏极区。
在上述方法中,还包括:在所述多个半导体鳍的所述第二部分的侧壁上形成鳍间隔件;以及当蚀刻所述多个半导体鳍时凹进所述鳍间隔件。
在上述方法中,当开始所述外延时,所述鳍间隔件具有剩余的部分。
在上述方法中,在蚀刻所述多个半导体鳍的所述第二部分之后,暴露所述半导体基底,并且从所述半导体基底开始执行所述外延。
在上述方法中,在所述外延期间,在所述外延源极/漏极区中生长孔。
在上述方法中,生长所述孔以具有椭圆形形状。
在上述方法中,生长所述孔以具有圆形的下部以及连接至对应的所述圆形的下部的三角形上部。
根据本发明的又一实施例,还提供了一种形成鳍式场效应晶体管(FinFET)的方法,包括:蚀刻半导体衬底以形成由沟槽彼此分离的第一半导体区和第二半导体区;形成掺杂有具有第一导电类型的第一掺杂剂的第一掺杂的介电层,其中,在所述第一半导体区和所述第二半导体区的侧壁和顶面上形成所述第一掺杂的介电层;去除所述第一掺杂的介电层的位于所述第一半导体区上的部分;形成掺杂有具有与所述第一导电类型相反的第二导电类型的第二掺杂剂的第二掺杂的介电层,其中,所述第二掺杂的介电层形成在所述第一半导体区的所述侧壁和所述顶面上并且覆盖所述第一掺杂的介电层的位于所述第二半导体区上的剩余部分;在所述沟槽内以及在所述第一掺杂的介电层和所述第二掺杂的介电层上方填充介电材料;以及执行退火,其中,所述第二掺杂剂扩散至所述第一半导体区的第一表面层内,并且所述第一掺杂剂扩散至所述第二半导体区的第二表面层内。
在上述方法中,所述第一半导体区的所述第一表面层具有所述第二导电类型,并且所述第二半导体区的所述第二表面层具有所述第一导电类型。
在上述方法中,在所述退火期间,所述第二掺杂剂也扩散至所述第二半导体区的所述第二表面层内。
在上述方法中,形成所述第一掺杂的介电层包括沉积磷硅酸盐玻璃(PSG)层。
在上述方法中,形成所述第二掺杂的介电层包括沉积硼硅酸盐玻璃(BSG)层。
在上述方法中,还包括:去除所述第一半导体区的部分;以及执行外延以从所述第一表面层生长外延区。
上面概述了若干实施例的部件、使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实现与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围、并且在不背离本发明的精神和范围的情况下,在此他们可以做出多种变化、替换以及改变。
Claims (20)
1.一种形成鳍式场效应晶体管(FinFET)的方法,包括:
蚀刻半导体衬底以形成第一沟槽和第二沟槽,其中,在所述第一沟槽和所述第二沟槽之间留下所述半导体衬底的剩余部分作为半导体区;
在所述半导体区的侧壁上和所述半导体区的整个顶面上方形成掺杂的介电层,其中,所述掺杂的介电层包括掺杂剂;
用介电材料填充所述第一沟槽和所述第二沟槽;以及
执行退火,其中,在所述退火过程中,所述掺杂的介电层保持覆盖所述半导体区的所述侧壁和所述整个顶面,所述掺杂的介电层中的所述掺杂剂扩散至所述半导体区内以形成扩散的半导体区。
2.根据权利要求1所述的方法,其中,所述半导体区包括半导体基底以及位于所述半导体基底上方并且连接至所述半导体基底的半导体条,并且所述方法还包括:
蚀刻所述半导体条;以及
从所述半导体区的蚀刻所述半导体条剩余的部分执行外延以形成外延半导体区。
3.根据权利要求2所述的方法,还包括:
在所述半导体条的顶部的侧壁上形成间隔件;以及
凹进所述半导体条的所述顶部,其中,所述外延半导体区的从所述半导体条的蚀刻所述半导体条剩余的部分生长的部分彼此合并。
4.根据权利要求2所述的方法,其中,所述外延从所述扩散的半导体区生长。
5.根据权利要求1所述的方法,其中,所述掺杂的介电层中的所述掺杂剂具有n型,并且所述方法还包括在所述退火之前在所述掺杂的介电层上方形成附加的p型掺杂的层。
6.根据权利要求1所述的方法,其中,形成所述掺杂的介电层包括沉积磷硅酸盐玻璃(PSG)层。
7.根据权利要求1所述的方法,其中,形成所述掺杂的介电层包括沉积硼硅酸盐玻璃(BSG)层。
8.一种形成鳍式场效应晶体管(FinFET)的方法,包括:
蚀刻半导体衬底以形成半导体区,所述半导体区包括半导体基底以及位于所述半导体基底上方并且连接至所述半导体基底的多个半导体条,其中,延伸至所述半导体衬底内的第一沟槽和第二沟槽位于所述半导体区的相对两侧上;
在所述半导体区的侧壁上和所述半导体区的整个顶面上方形成掺杂的介电层,其中,所述掺杂的介电层包括掺杂剂;
形成所述掺杂的介电层后,用介电材料填充所述第一沟槽和所述第二沟槽以形成隔离区,其中在所述填充之后以及形成所述隔离区之前执行退火,在所述退火过程中,所述掺杂的介电层保持覆盖所述半导体区的所述侧壁和所述整个顶面,所述掺杂的介电层中的所述掺杂剂扩散至所述半导体区内以形成扩散的半导体区;
在形成所述隔离区之后凹进所述隔离区,其中,所述多个半导体条的顶部形成多个半导体鳍;
在所述多个半导体鳍的第一部分上形成栅极堆叠件;
蚀刻所述多个半导体鳍的未被所述栅极堆叠件覆盖的第二部分;以及
从所述半导体区的剩余部分执行外延以形成外延源极/漏极区。
9.根据权利要求8所述的方法,还包括:
在所述多个半导体鳍的所述第二部分的侧壁上形成鳍间隔件;以及
当蚀刻所述多个半导体鳍时凹进所述鳍间隔件。
10.根据权利要求9所述的方法,其中,当开始所述外延时,所述鳍间隔件具有剩余的部分。
11.根据权利要求8所述的方法,其中,在蚀刻所述多个半导体鳍的所述第二部分之后,暴露所述半导体基底,并且从所述半导体基底开始执行所述外延。
12.根据权利要求8所述的方法,其中,在所述外延期间,在所述外延源极/漏极区中生长孔。
13.根据权利要求12所述的方法,其中,生长所述孔以具有椭圆形形状。
14.根据权利要求12所述的方法,其中,生长所述孔以具有圆形的下部以及连接至对应的所述圆形的下部的三角形上部。
15.一种形成鳍式场效应晶体管(FinFET)的方法,包括:
蚀刻半导体衬底以形成由沟槽彼此分离的第一半导体区和第二半导体区;
形成掺杂有具有第一导电类型的第一掺杂剂的第一掺杂的介电层,其中,在所述第一半导体区和所述第二半导体区的侧壁和顶面上形成所述第一掺杂的介电层;
去除所述第一掺杂的介电层的位于所述第一半导体区上的部分;
形成掺杂有具有与所述第一导电类型相反的第二导电类型的第二掺杂剂的第二掺杂的介电层,其中,所述第二掺杂的介电层形成在所述第一半导体区的所述侧壁和整个顶面上并且覆盖所述第一掺杂的介电层的位于所述第二半导体区上的剩余部分;
在所述沟槽内以及在所述第一掺杂的介电层和所述第二掺杂的介电层上方填充介电材料;以及
执行退火,其中,在所述退火过程中,所述第二掺杂的介电层保持至少覆盖所述第一半导体区的所述侧壁和所述整个顶面,所述第二掺杂剂扩散至所述第一半导体区的第一表面层内,并且所述第一掺杂剂扩散至所述第二半导体区的第二表面层内。
16.根据权利要求15所述的方法,其中,所述第一半导体区的所述第一表面层具有所述第二导电类型,并且所述第二半导体区的所述第二表面层具有所述第一导电类型。
17.根据权利要求16所述的方法,其中,在所述退火期间,所述第二掺杂剂也扩散至所述第二半导体区的所述第二表面层内。
18.根据权利要求15所述的方法,其中,形成所述第一掺杂的介电层包括沉积磷硅酸盐玻璃(PSG)层。
19.根据权利要求15所述的方法,其中,形成所述第二掺杂的介电层包括沉积硼硅酸盐玻璃(BSG)层。
20.根据权利要求15所述的方法,还包括:
去除所述第一半导体区的部分;以及
执行外延以从所述第一表面层生长外延区。
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