TWI500154B - 半導體裝置、電晶體及其形成方法 - Google Patents

半導體裝置、電晶體及其形成方法 Download PDF

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TWI500154B
TWI500154B TW100139540A TW100139540A TWI500154B TW I500154 B TWI500154 B TW I500154B TW 100139540 A TW100139540 A TW 100139540A TW 100139540 A TW100139540 A TW 100139540A TW I500154 B TWI500154 B TW I500154B
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sidewall
fins
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dielectric layer
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Chi Wen Liu
Chao Hsiung Wang
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Taiwan Semiconductor Mfg Co Ltd
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Description

半導體裝置、電晶體及其形成方法
本發明係有關於鰭式場效應電晶體，且特別是有關於一種多鰭板的鰭式場效應電晶體。
在高性能、小尺寸的積體電路中，鰭式場效應電晶體(Fin field effect transistor；FinFET)裝置的應用日益增加。由於其閘極圍繞在通道區的三側，鰭式場效應電晶體在小的關鍵尺寸下提供良好的通道控制。另一方面，由於鰭式場效應電晶體結構本身的特性，使得典型鰭式場效應電晶體裝置的通道寬度難以調整。既然許多裝置的性能參數，例如驅動電流(IDsat )與通道寬度有關，通道寬度無法輕易調整為典型鰭式場效應電晶體裝置的缺點。現在亟需一種鰭式場效應電晶體結構及其製造方法，可克服傳統技術中的缺點。
本發明一實施例提供一種半導體裝置，包括：一基板；複數個鰭板，形成在該基板上；源極及汲極區，形成在各該鰭板中；一介電層，形成在該基板上，該介電層具有一第一厚度鄰近一第一鰭板的一側，且具有不同於該第一厚度的一第二厚度鄰近該第一鰭板的另一側；以及一連續閘極結構，覆蓋該複數個鰭板，該連續閘極結構鄰近各鰭板的一頂表面及至少一鰭板的至少一側壁。
本發明另一實施例提供一種電晶體，包括：一第一半導體鰭板，在一介電層中，該第一半導體鰭板具有一第一側壁在該介電層上延伸一第一距離、一頂表面、以及一第二側壁在該介電層上延伸一第二距離；一第二半導體鰭板，在該介電層中，該第二鰭板具有一第側壁在該介電層上延伸該第一距離、一頂表面、以及一第二側壁在該介電層上延伸該第一距離；一閘極結構，覆蓋該第一及第二半導體鰭板，其中該閘極結構在該頂表面及至少一側壁上與該第一半導體鰭板接觸，且在該頂表面及至少一側壁上與該第二半導體鰭板接觸；一源極區，分佈在該第一及第二半導體鰭板中；以及一汲極區，分佈在該第一及第二半導體鰭板中。
本發明又一實施例提供一種電晶體的形成方法，包括：在一基板上形成複數個鰭板；在該複數個鰭板中形成源極及汲極區；在該鰭板中形成一介電層；調整該複數個鰭板之至少二個鰭板間該介電層的一厚度；以及在該鰭板及該介電層上形成一連續閘極結構。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
以下依本發明之不同特徵舉出數個不同的實施例。本發明中特定的元件及安排係為了簡化，但本發明並不以這些實施例為限。舉例而言，於第二元件上形成第一元件的描述可包括第一元件與第二元件直接接觸的實施例，亦包括具有額外的元件形成在第一元件與第二元件之間、使得第一元件與第二元件並未直接接觸的實施例。此外，為簡明起見，本發明在不同例子中以重複的元件符號及/或字母表示，但不代表所述各實施例及/或結構間具有特定的關係。
第1a圖顯示在製造鰭式場效應電晶體裝置1的中間階段的立體圖。第1b圖顯示在第1a圖中沿著線a-a的剖面圖結構。在所述實施例中，鰭式場效應電晶體1將延伸過數個鰭板，且具體而言為三個鰭板，將詳述如下。在第1a圖所顯示製程的中間階段中，在基板4上形成圖案化感光層(patterned photo-sensitive layer)2。更準確的說，圖案化感光層4，例如為光阻等，形成在硬罩幕6上，硬罩幕6則形成在氧化物墊8上，氧化物墊8則形成在基板4上。硬罩幕6可為氮化矽、氮氧化矽等。氧化物墊8則可為氧化矽，且其形成方法為已知技術。
基板4可為塊基板(bulk substrate)，例如塊矽晶圓。或者，基板4可僅為化合物晶圓的上部半導體層，例如絕緣層上有矽(silicon-on-insulator)基板。在另一實施例中，基板4可為塊基板或化合物晶圓的上層，包括磊晶成長的鍺、矽鍺、Ⅲ-Ⅴ材料例如砷化鎵、砷化銦、Ⅱ-Ⅵ材料如硒化鋅(ZeSe)、硫化鋅等。藉由利用如砷化銦、硫化鋅等Ⅲ-Ⅴ或Ⅱ-Ⅵ材料的性質，可得良好的應變性質(strain properties)，因此以Ⅲ-Ⅴ或Ⅱ-Ⅵ材料形成上述裝置可能特別有利。
如第2a及2b圖所示(其中第2a圖及第2b圖分別為第1a及1b剖面圖的延續)，利用已知的蝕刻製程將圖案化感光層4的圖案轉移到硬罩幕6、氧化物墊8及基板4中，其詳細製程並非了解本發明所必須，故在此不重述。在此圖案轉移的製程中，圖案化感光層2可完全耗盡，如第2a及2b圖所示。在一些實施例中，圖案化感光層2並非完全耗盡，而仍保有部分圖案化感光層2，其係利用氧電漿或所謂灰化製程(ash process)加以移除。所形成的結構包括在基板4中形成複數個鰭板10。複數個鰭板10的各鰭板具有側壁，側壁的一部分大體上與基板4的主要表面正交，側壁較低的部分則並非與基板4的主要表面正交。這些鰭板10係作為所欲形成的鰭式場效應電晶體裝置1的鰭板結構。在一些實施例中，蝕刻基板4至一深度，亦即形成鰭板10至一高度，為約40nm至約80nm。在一特定實施例中，形成鰭板10的高度約60nm。
參照第3圖，氧化物層12毯覆沉積在裝置1上。可利用如化學氣相沉積製程、旋塗玻璃(spin-on-glass)製程等本領域技藝人士已知的製程步驟沉積氧化物層12，其有時可稱為淺溝槽隔離氧化物或淺溝槽隔離。在形成氧化物12之前，可選擇進行鰭板10的熱氧化，以修復在蝕刻步驟中(第2a及2b圖所示)所造成側壁的損害。
如第4a及4b圖所示，對薄氧化物層12進行化學機械研磨至與鰭板10的頂部齊平。應注意的是，圖案化硬罩幕6及圖案化氧化物墊8在化學機械研磨中被移除。化學機械研磨步驟的條件為已知技術，故為了清楚與簡化的緣故在此不重複敘述。在一些實施例中，在化學機械研磨之後，在基板4上形成複數個鰭板10的步驟可更包括一製程，其大抵選自下列所組成之群組：蝕刻鰭板至基板內、在基板上磊晶成長鰭板、及前述之組合。因此，複數個鰭板可大抵選自下列所組成之群組：磊晶材料、基板材料、及前述之組合。
第5a圖顯示製程步驟的下一個階段，其中氧化物層12更進一步的進行薄化(thinned back)。可利用各種方法使氧化物層12進行薄化。在一實施例中，藉由稀氫氟酸(diluted hydrofluoric acid；DHF)處理或氣相氫氟酸處理適當的時間，以進行氧化物層12的薄化。應注意氧化物層12係選擇性的薄化，如標記A(係指氧化物層12未被薄化的部分)及標記B(係指氧化物層12被薄化的部分)所示。可藉由在回蝕製程中，利用保護層如光阻層覆蓋在氧化物層12上，以達到上述選擇性薄化。
在第5b圖所示實施例中，鰭板10在基板4的表面上延伸一距離H，且在氧化物層12的薄化部分B上延伸一距離h。在實施例中，在B區中1/4<h/H<1/3。在B區中氧化物層12上鰭板10上述延伸的比例可提供較佳的通道寬度，詳述如下。
接著，在三個鰭板10上形成單一連續的閘極結構，如第6a及6b圖所示。在第6a圖中也顯示在各鰭板10中形成源極區S及汲極區D。在一實施例中，形成源極及汲極區包括在各鰭板中摻雜摻質。在另一實施例中，源極及汲極區的形成包括蝕刻鰭板至基板中，以及在基板上磊晶成長源極及汲極區。本領域技藝人士了解可利用多個製程步驟形成閘極結構14，其中包括形成並圖案化閘極介電質，以及形成並圖案化閘極電極。本發明並不需要了解上述詳情，且閘極介電質及閘電極此後統稱為閘極結構14。同樣的，形成摻雜的源極及汲極區為已知技術，故為了簡化起見在此不重複詳述。在此實施例中，第一金屬層可連續且覆蓋三個源極區，以形成鰭式場效應電晶體裝置的源極區。此外，第二金屬層可為連續且覆蓋三個汲極區，以形成鰭式場效應電晶體裝置的汲極區。
本領域技藝人士應可了解通道長度及通道寬度為電晶體的兩個重要參數，包括如裝置1所示的鰭式場效應電晶體裝置。通道長度大體上相等於源極S及汲極D區之間的距離。在上述實施例中，使用多個鰭板，且特定的多個鰭板具有不同的高度而造成各鰭板間氧化物層12的厚度不同，其通道長度不會被影響。亦即，在各鰭板間氧化物層12的不同厚度，不會影響源極S及汲極D之間的距離或通道長度。通道長度會影響電晶體的性能，例如開關速度。
通道寬度也會影響裝置性能，例如裝置的驅動電流。在一實施例中，可藉由調整通道寬度來微調IDSAT 。藉由鰭板間氧化物層12的不同厚度，造成在氧化物層上不同的鰭板高度，因此可調整所形成鰭式場效應電晶體的整體通道寬度。此將於第6c至6f圖中更詳細的解釋。
首先參照第6c圖，顯示一實施例的最終結構，其中在各鰭板10間氧化物層12沒有被回蝕。在此實施例中，整體通道寬度(在形成閘極結構14後)將相等於鰭板10的厚度t。在此實施例中，三個鰭板10聚集形成鰭式場效應電晶體裝置(亦即，單一閘極結構14連續且覆蓋在三個鰭板10上，如第6b圖所示)，其整體通道寬度可相等於3t。此結構有效等於平面電晶體裝置。相反的，第6d圖顯示其他實施例的最終結構，其中所有鰭板10間的氧化物層12都被一致的回蝕。在此實施例中，整體的通道寬度會相等於各鰭板的厚度t加上兩倍的各鰭板高度h(由於閘極結構會覆蓋各鰭板的兩個側壁，各側壁各具有高度h，鰭板的頂部具有厚度t)。在上述實施例中，通道寬度相等於3t+6h。雖然上述結構可有利於形成三個鰭板，例如在相同面積中與平面電晶體具有類似的性質，多的鰭板結構可能會造成過多的驅動電流，其可能對裝置性能有負面的影響。
第6e圖顯示另一實施例結構，其中藉由各鰭板間氧化物層12不同的厚度以調整驅動電流。應注意在第6e圖所示實施例中，例如回蝕一對鰭板10(左側及中間鰭板)間的氧化物層12，但並未回蝕另一對鰭板(右側及中間鰭板)10間的氧化物層12。在此實施例中，由於鰭板只有兩個側壁暴露並被閘極結構14覆蓋(未顯示，但顯示於第6b圖中)，因此所形成結構的驅動電流將為3t+2h。
第6f圖顯示又一實施例，其中在兩對鰭板間的閘極氧化物12都被回蝕，然而並沒有回蝕外側鰭板的外側邊緣。在此實施例中，整體通道寬度為3t+4h。本領域技藝人士應了解可利用調整氧化物層12的厚度及各鰭板10的寬度形成各種其他結構，以微調通道寬度。
在第6圖所示的實施例中(其中包括第6a至6f圖)，氧化物層12在一些區域(區域B)中被蝕刻或在其他區域(區域A)中完整保留而未蝕刻。在其他實施例中，藉由回蝕特定區域中第一數量之氧化物層12，並回蝕其他區域中比第一數量更多的第二數量之氧化物層12，以進行更進一步的微調。第7a及7b圖即顯示上述實施例。
第7a圖顯示一實施例的立體圖，第7b圖顯示一實施例的剖面圖，其中，在第一回蝕步驟中，保護標記為C部分的氧化物層12(例如覆蓋有光阻、硬罩幕、犧牲層等)，而部分回蝕標記為E部分的氧化物層12。在下一製程步驟中，暴露出C部分，並進一步回蝕氧化物層12，包括C及E部分，蝕刻至第7a及7b圖所示程度。在此實施例中，最左側的鰭板10在氧化物層12上延伸一高度h2 ，而最右側的兩個鰭板在相對的外側側壁上氧化物層12上延伸一高度h2 (因氧化物層12在鰭板的外側區域的厚度為”E”)，且在相對的側壁內側具有厚度”C”的氧化物層12上具有較小的高度h1 。假設鰭板10具有厚度t，則在第7圖中的整體通道寬度為3t+4h2 +2h1 。
在一實施例中，電晶體中包括：第一半導體鰭板，其第一側壁在該介電層上延伸高度h1 及第二側壁在該介電層上延伸高度h2 ；第二半導體鰭板，其第一側壁及一第二側壁均在介電層上延伸高度h2 ；以及第三半導體鰭板，其第一側壁及一第二側壁亦在介電層上延伸高度h2 。雖然本發明各實施例及優點詳述如上，但應了解可進 行各種變化、取代、或替換而仍未脫離本發明之精神與範疇內。例如，雖然顯示鰭式場效應電晶體裝置延伸過三個鰭板，本發明也可應用延伸過二個鰭板、四個鰭板、或更多鰭板的鰭式場效應電晶體裝置。相同的，其他多重閘極裝置也在本發明之範疇，如w-閘極裝置、Ω-閘極裝置等。此外，可更由前述二個回蝕製程延伸出三個回蝕製程，以進一步的微調通道長度，其中氧化物層12可具有三種不同高度，使得鰭板具有三種不同鰭板側壁高度。此教示可更藉由增加額外的回蝕及罩幕步驟，進一步延伸出四種或更多種不同氧化物層的厚度。應了解本發明利用蝕刻進入基板所形成的鰭板的技術，也可應用於磊晶成長的鰭板。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
1‧‧‧鰭式場效應電晶體
4‧‧‧基板
2‧‧‧圖案化感光層
6‧‧‧硬罩幕
8‧‧‧氧化物墊
10‧‧‧鰭板
12‧‧‧氧化物層
A、B、C、E‧‧‧標記
H、h‧‧‧距離
S‧‧‧源極
D‧‧‧汲極
14‧‧‧閘極結構
t‧‧‧厚度
h1 、h2 ‧‧‧高度
第1a-1b、2a-2b、3a-3b、4a-4b、5a-5b、6a-6b圖顯示一實施例1的各製造階段。
第6c-6f圖顯示在另一實施例中調整介電層的厚度。
第7a-7b圖分別顯示另一實施例中在第6c-6f圖所示結構。
4．．．基板
10．．．鰭板
12．．．氧化物層
C、E．．．標記
H．．．距離
t．．．厚度
h1 、h2 ．．．高度

Claims (9)

  1. 一種半導體裝置，包括：一基板；複數個鰭板，形成在該基板上，該複數個鰭板之任一鰭板具有一側壁，該側壁之一上部實質上正交於與該基板之一主要表面，而該側壁之一下部係非正交於該基板之該主要表面，且該下部之寬度大於該上部之寬度；源極及汲極區，形成在各該鰭板中；一介電層，形成在該基板上，該介電層具有一第一厚度鄰近一第一鰭板的一側，且具有不同於該第一厚度的一第二厚度鄰近該第一鰭板的另一側，且該介電層至少接觸部分該第一鰭板之上部側壁，並更進一步接觸部分該第一鰭板之下部側壁；以及一連續閘極結構，於該複數個鰭板上，該連續閘極結構鄰近各鰭板的一頂表面及至少一鰭板的至少一側壁。
  2. 如申請專利範圍第1項所述之半導體裝置，包括：該第一鰭板，具有被該介電層覆蓋的一第一側壁，以及延伸至該介電層上的一第二側壁；一第二鰭板，具有一第一側壁及一第二側壁皆延伸至該介電層上；以及其中該閘極結構順應的在該第一鰭板的該第二側壁以及該第二鰭板的該第一及該第二側壁上。
  3. 如申請專利範圍第1項所述之半導體裝置，其中該複數個鰭板的各鰭板具有一厚度為t的頂表面，且在該介 電層上具有至少一高度為h的側壁，其中一通道形成在該複數個鰭板中，該通道具有由厚度t的總合及高度h的總合所定義的通道寬度。
  4. 如申請專利範圍第1項所述之半導體裝置，其中該複數個鰭板的至少一鰭板具有延伸至該介電層上的二側壁。
  5. 如申請專利範圍第1項所述之半導體裝置，其中該介電層的該第一厚度相等於該基板上該鰭板的一高度。
  6. 一種電晶體，包括：一第一半導體鰭板，在一介電層中，該第一半導體鰭板具有一第一側壁在該介電層上延伸一第一距離、一頂表面、以及一第二側壁在該介電層上延伸一第二距離；一第二半導體鰭板，在該介電層中，該第二半導體鰭板具有一第一側壁在該介電層上延伸該第一距離、一頂表面、以及一第二側壁在該介電層上延伸該第一距離；一閘極結構，於該第一及第二半導體鰭板上，其中該閘極結構在該頂表面及至少一側壁上與該第一半導體鰭板接觸，且在該頂表面及至少一側壁上與該第二半導體鰭板接觸；一源極區，分佈在該第一及第二半導體鰭板中；以及一汲極區，分佈在該第一及第二半導體鰭板中；其中，該第一側壁與該第二側壁個別具有一上部實質上正交於該基板之一主要表面，以及一下部非正交於該基板之該主要表面，且該下部之寬度大於該上部之寬 度，而該介電層接觸該些半導體鰭板至少一個之該第一側壁之該上部及該下部，並更進一步接觸該第二側壁之該上部及該下部。
  7. 如申請專利範圍第6項所述之電晶體，更包括一第三半導體鰭板在該介電層中，該第三半導體鰭板具有一第一側壁在該介電層上延伸該第一距離、一頂表面、以及一第二側壁在該介電層上延伸該第一距離。
  8. 如申請專利範圍第6項所述之電晶體，其中該電晶體包括在該第一及第二鰭板中的一通道區域，其中該通道區域具有一通道寬度，該通道寬度相等於該二個頂表面厚度的總合以及該距離的總合，其中該第二半導體鰭板的第一及第二側壁延伸至該介電層上。
  9. 一種電晶體的形成方法，包括：在一基板上形成複數個鰭板，該複數個鰭板之任一鰭板具有一側壁，該側壁之一上部實質上正交於與該基板之一主要表面，而該側壁之一下部係非正交於該基板之該主要表面，且該下部之寬度大於該上部之寬度；在該複數個鰭板中形成源極及汲極區；在該些鰭板間形成一介電層；調整該些鰭板之至少二個鰭板間該介電層的一厚度，並使至少一個該介電層至少接觸部分該第一鰭板之上部側壁，並更進一步接觸部分該第一鰭板之下部側壁；以及在該鰭板及該介電層上形成一連續閘極結構。
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US20180151566A1 (en) 2018-05-31
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US10679990B2 (en) 2020-06-09
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