CN109712934A - 一种制作半导体元件的方法 - Google Patents

一种制作半导体元件的方法 Download PDF

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CN109712934A
CN109712934A CN201711012210.2A CN201711012210A CN109712934A CN 109712934 A CN109712934 A CN 109712934A CN 201711012210 A CN201711012210 A CN 201711012210A CN 109712934 A CN109712934 A CN 109712934A
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area
epitaxial layer
well region
substrate
laying
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CN109712934B (zh
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曾冠豪
林建廷
蔡世鸿
谢柏光
曾于庭
戴觉非
郭承平
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United Microelectronics Corp
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United Microelectronics Corp
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Abstract

本发公开一种制作半导体元件的方法。首先提供一基底，该基底上具有一第一区域以及一第二区域，然后形成一第一阱区于第一区域的基底内以及一第二阱区于第二区域的基底内，去除部分第一阱区以形成一第一凹槽，再形成一第一外延层于第一凹槽内。

Description

一种制作半导体元件的方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种于基底内形成凹槽，成长外延层于凹槽内后再将外延层形成鳍状结构的方法。
背景技术
随着场效晶体管(field effect transistors,FETs)元件尺寸持续地缩小，现有平面式(planar)场效晶体管元件的发展已面临制作工艺上的极限。为了克服制作工艺限制，以非平面(non-planar)的场效晶体管元件，例如鳍状场效晶体管(fin field effecttransistor,Fin FET)元件来取代平面晶体管元件已成为目前的主流发展趋势。由于鳍状场效晶体管元件的立体结构可增加栅极与鳍状结构的接触面积，因此，可进一步增加栅极对于载流子通道区域的控制，从而降低小尺寸元件面临的漏极引发能带降低(draininduced barrier lowering,DIBL)效应，并可以抑制短通道效应(short channel effect,SCE)。再者，由于鳍状场效晶体管元件在同样的栅极长度下会具有更宽的通道宽度，因而可获得加倍的漏极驱动电流。甚而，晶体管元件的临界电压(threshold voltage)也可通过调整栅极的功函数而加以调控。
然而，在现行的鳍状场效晶体管元件制作工艺中，鳍状结构的形成仍存在许多瓶颈，进而影响整个元件的漏电流及整体电性表现。因此如何改良现有鳍状场效晶体管制作工艺即为现今一重要课题。
发明内容
本发明一实施例公开一种制作半导体元件的方法。首先提供一基底，该基底上具有一第一区域以及一第二区域，然后形成一第一阱区于第一区域的基底内以及一第二阱区于第二区域的基底内。接着形成一衬垫层于基底上，形成一图案化掩模于衬垫层上，去除部分衬垫层以及部分第一阱区以形成一凹槽，去除第一图案化掩模，最后再形成一外延层于第一凹槽内。
附图说明
图1至图11为本发明一实施例制作一半导体元件的方法示意图。
主要元件符号说明
12 基底 14 NMOS区域
16 PMOS区域 18 周边区
20 衬垫层 22 图案化光致抗蚀剂
24 离子注入制作工艺 26 N阱
28 图案化光致抗蚀剂 30 离子注入制作工艺
32 P阱 34 衬垫层
36 图案化光致抗蚀剂 38 凹槽
40 外延层 42 氧化层
44 图案化光致抗蚀剂 46 凹槽
48 外延层 50 鳍状结构
52 浅沟隔离
具体实施方式
请参照图1至图11，图1至图11为本发明一实施例制作一半导体元件的方法示意图。如图1所示，首先提供一基底12，例如一硅基底，且基底12上较佳定义有一第一区域、一第二区域以及一第三区域。在本实施例中，第一区域较佳为后续制作工艺中用来制备NMOS晶体管元件的NMOS区域14，第二区域较佳为后续用来制备PMOS晶体管元件的PMOS区域16，而第三区域较佳为一周边区18。然后形成一由氧化硅所构成的衬垫层20于基底12上，再分别形成一第一阱区于NMOS区域14的基底内以及一第二阱区于PMOS区域16的基底12内。
在本实施例中，形成第一阱区以及第二阱区的方式可先形成一图案化掩模，例如图案化光致抗蚀剂22于衬垫层20上覆盖NMOS区域14以及周边区18，然后利用图案化光致抗蚀剂22为掩模进行一离子注入制作工艺24，将例如磷离子或砷离子等N型掺质注入PMOS区域16的基底12内以形成一第二阱区或N阱26，之后再去除图案化光致抗蚀剂22。
如图2所示，然后形成另一图案化掩模，例如图案化光致抗蚀剂28于衬垫层20上覆盖周边区18以及PMOS区域16，并利用图案化光致抗蚀剂28为掩模进行另一离子注入制作工艺30，将例如硼离子等P型掺质注入NMOS区域14的基底12内以形成一第一阱区或P阱32。
如图3所示，接着去除图案化光致抗蚀剂28暴露出NMOS区域14、PMOS区域16以及周边区18的衬垫层20表面，进行一热处理制作工艺活化注入于基底12内的掺质，完全去除衬垫层20之后再形成另一同样由氧化硅所构成的衬垫层34于NMOS区域14、PMOS区域16以及周边区18的基底12表面。
随后如图4所示，先形成另一图案化掩模，例如图案化光致抗蚀剂36于周边区18以及PMOS区域16的衬垫层34上，并利用图案化光致抗蚀剂36为掩模进行一蚀刻制作工艺，去除NMOS区域14的部分衬垫层34以及部分P阱32以形成一凹槽38。在本实施例中，用来去除部分衬垫层34以及部分P阱32的蚀刻制作工艺较佳为一干蚀刻制作工艺，其可选用例如氯气(Cl2)、溴化氢(HBr)或其组合。之后再去除图案化光致抗蚀剂36。
如图5所示，然后进行一外延成长制作工艺以形成一外延层40于凹槽38内，其中所成长的外延层40上表面较佳高于基底12以及衬垫层34上表面。在本实施例中，外延层40较佳包含一无掺杂外延层，或更具体而言为一无掺杂硅层，但不局限于此。
接着如图6所示，进行一平坦化制作工艺，例如利用一化学机械研磨(chemicalmechanical polishing,CMP)制作工艺去除部分外延层40并使剩余的外延层40上表面切齐衬垫层34上表面。
如图7所示，随后可进行一氧化制作工艺，例如可利用现场蒸气成长(in-situsteam generation,ISSG)制作工艺形成一氧化层42于NMOS区域14的外延层40表面，其中所成长的氧化层42较佳与两侧周边区18以及PMOS区域16的衬垫层34包含相同材料，例如均由二氧化硅所构成且氧化层42上表面较佳切齐两侧的衬垫层34上表面。
如图8所示，接着利用蚀刻全面性去除基底12表面的氧化层42以及衬垫层34，包括设于NMOS区域14的氧化层42以及两侧周边区18以及PMOS区域16的衬垫层34。去除氧化层42以及衬垫层34后，所暴露出的外延层40上表面较佳切齐周边区18的基底12表面以及PMOS区域16的N阱26上表面。
之后可选择进行一图案转移制作工艺去除部分NMOS区域14以及PMOS区域16的基底12以形成多个鳍状结构，形成一浅沟隔离于鳍状结构之间，然后再依据制作工艺需求进行后续晶体管制作工艺，例如可于鳍状结构上形成栅极结构、间隙壁以及源极/漏极区域等晶体管元件。
此外，依据本发明一实施例，如图9所示，本发明可于图8以蚀刻去除基底12表面的氧化层42以及衬垫层34之后选择性进行另一微影曁蚀刻制作工艺形成另一外延层于PMOS区域16。举例来说，本发明可形成一图案化掩模，例如图案化光致抗蚀剂44于NMOS区域14以及周边区18的基底12上，然后利用图案化光致抗蚀剂44进行一蚀刻制作工艺，去除部分N阱26以形成一凹槽46，其中凹槽46底部较佳切齐NMOS区域14的外延层40底部或P阱32上表面。
如图10所示，然后可去除图案化光致抗蚀剂44，进行一外延层成长制作工艺以形成外延层48于凹槽46内，并进行一平坦化制作工艺，例如利用CMP去除部分外延层48使剩余的外延层48上表面切齐NMOS区域14的外延层40上表面。然而不局限于此顺序，依据本发明另一实施例，又可选择图案化光致抗蚀剂44仍设于NMOS区域14以及周边区18的情况下直接形成外延层48，之后再去除图案化光致抗蚀剂44并进行平坦化制作工艺，此实施例也属本发明所涵盖的范围。在本实施例中，NMOS区域14的外延层40以及PMOS区域16的外延层48较佳包含不同材料，例如PMOS区域16的外延层48虽同样包含一无掺杂外延层，又可细部包含一无掺杂锗化硅层。
随后如图11所示，可再进行一图案转移制作工艺去除部分NMOS区域14以及PMOS区域16的基底12以形成多个鳍状结构50。更具体而言，形成鳍状结构50的方式可先形成一图案化掩模(图未示)于周边区18上并覆盖部分外延层40以及部分外延层48上，然后利用蚀刻去除NMOS区域14的部分外延层40以及PMOS区域16的部分外延层48，以于NMOS区域14以及PMOS区域16分别形成多个鳍状结构50。之后可形成一浅沟隔离52于鳍状结构50之间，然后再依据制作工艺需求进行后续晶体管制作工艺，例如可于鳍状结构50上形成栅极结构、间隙壁以及源极/漏极区域等晶体管元件。至此即完成本发明一实施例的半导体元件的制作。
值得注意的是，本实施例形成鳍状结构50时较佳仅去除部分外延层40以及外延层48但不去除任何NMOS区域14的P阱32以及PMOS区域16的N阱26，因此所形成的鳍状结构50底部较佳切齐P阱32以及N阱26上表面。然而依据本发明其他实施例，例如利用前述图案转移制作工艺形成鳍状结构50时又可选择去除部分外延层40以及部分外延层48的时候不蚀刻至P阱32以及N阱26上表面，或去除部分外延层40以及部分外延层48的时候同时蚀刻部分P阱32以及部分N阱26。换句话说，相较于前述实施例鳍状结构50底部切齐P阱32以及N阱26上表面，本发明其他实施例于制作出鳍状结构50后P阱32以及N阱26上表面可略高于鳍状结构50底部且低于浅沟隔离52上表面或略低于鳍状结构50底部，这些变化型均属本发明所涵盖的范围且均可应用至前述图8后不形成外延层在PMOS区域16便直接形成鳍状结构的实施例。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (15)

1.一种制作半导体元件的方法，包含：
提供一基底，该基底上具有第一区域以及第二区域；
形成一第一阱区于该第一区域的该基底内以及一第二阱区于该第二区域的该基底内；
去除部分该第一阱区以形成一第一凹槽；以及
形成一第一外延层于该第一凹槽内。
2.如权利要求1所述的方法，另包含：
形成一衬垫层于该基底上；
形成一第一图案化掩模于该衬垫层上；
去除部分该衬垫层以及部分该第一阱区以形成该第一凹槽；
去除该第一图案化掩模；以及
形成该第一外延层于该第一凹槽内。
3.如权利要求2所述的方法，其中该第一外延层上表面高于该基底上表面。
4.如权利要求2所述的方法，另包含进行一平坦化制作工艺去除部分该第一外延层并使该第一外延层上表面切齐该衬垫层上表面。
5.如权利要求4所述的方法，另包含去除该衬垫层并使该第一外延层上表面切齐该第二阱区上表面。
6.如权利要求5所述的方法，另包含：
去除部分该第一外延层、部分该第一阱区以及部分该第二阱区以形成多个鳍状结构于该第一区域以及该第二区域上；以及
形成一浅沟隔离于该多个鳍状结构之间。
7.如权利要求4所述的方法，另包含：
形成一第二图案化掩模于该第一区域上；
去除该第二区域上的该衬垫层以及部分该第二阱区以形成一第二凹槽；
去除该第二图案化掩模；以及
形成一第二外延层于该第二凹槽内。
8.如权利要求7所述的方法，另包含：
去除部分该第一外延层、部分该第一阱区、部分该第二外延层以及部分该第二阱区以形成多个鳍状结构于该第一区域以及该第二区域上；以及
形成一浅沟隔离于该多个鳍状结构之间。
9.如权利要求7所述的方法，其中该第一外延层以及该第二外延层包含不同材料。
10.如权利要求7所述的方法，其中该第二外延层包含一无掺杂外延层。
11.如权利要求10所述的方法，其中该第二外延层包含一无掺杂锗化硅层。
12.如权利要求1所述的方法，其中该第一外延层包含一无掺杂外延层。
13.如权利要求12所述的方法，其中该第一外延层包含一无掺杂硅层。
14.如权利要求1所述的方法，其中该第一区域包含一NMOS区域以及该第二区域包含一PMOS区域。
15.如权利要求1所述的方法，其中该第一阱区包含一P阱且该第二阱区包含一N阱。
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