TWI717338B - 半導體元件及其製作方法 - Google Patents

半導體元件及其製作方法 Download PDF

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TWI717338B
TWI717338B TW105106997A TW105106997A TWI717338B TW I717338 B TWI717338 B TW I717338B TW 105106997 A TW105106997 A TW 105106997A TW 105106997 A TW105106997 A TW 105106997A TW I717338 B TWI717338 B TW I717338B
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buffer layer
layer
substrate
dopants
epitaxial layer
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馮立偉
蔡世鴻
李一凡
陳坤新
黃同雋
鄭志祥
黃南元
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聯華電子股份有限公司
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Priority to US15/139,305 priority patent/US9653603B1/en
Priority to US15/481,419 priority patent/US10121881B2/en
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Abstract

本發明揭露一種製作半導體元件的方法。首先提供一基底，然後形成一凹槽於基底內，形成一緩衝層於凹槽內，形成一磊晶層於緩衝層上，最後再去除部分磊晶層、部分緩衝層以及部分基底以形成鰭狀結構。

Description

半導體元件及其製作方法
本發明是關於一種製作半導體元件的方法，尤指一種於形成鰭狀結構之前形成一緩衝層於一基底上之方法。
隨著場效電晶體(field effect transistors,FETs)元件尺寸持續地縮小，習知平面式(planar)場效電晶體元件之發展已面臨製程上之極限。為了克服製程限制，以非平面(non-planar)之場效電晶體元件，例如鰭狀場效電晶體(fin field effect transistor,Fin FET)元件來取代平面電晶體元件已成為目前之主流發展趨勢。由於鰭狀場效電晶體元件的立體結構可增加閘極與鰭狀結構的接觸面積，因此，可進一步增加閘極對於載子通道區域的控制，從而降低小尺寸元件面臨的汲極引發能帶降低(drain induced barrier lowering,DIBL)效應，並可以抑制短通道效應(short channel effect,SCE)。再者，由於鰭狀場效電晶體元件在同 樣的閘極長度下會具有更寬的通道寬度，因而可獲得加倍的汲極驅動電流。甚而，電晶體元件的臨界電壓(threshold voltage)亦可藉由調整閘極的功函數而加以調控。
然而，在現行的鰭狀場效電晶體元件製程中，鰭狀結構的形成仍存在許多瓶頸，進而影響整個元件的漏電流及整體電性表現。因此如何改良現有鰭狀場效電晶體製程即為現今一重要課題。
本發明較佳實施例揭露一種製作半導體元件的方法。首先提供一基底，然後形成一凹槽於基底內，形成一緩衝層於凹槽內，形成一磊晶層於緩衝層上，最後再去除部分磊晶層、部分緩衝層以及部分基底以形成鰭狀結構。
本發明另一實施例揭露一種製作半導體元件的方法。首先提供一基底，然後形成一鰭狀結構於基底上以及一絕緣層環繞鰭狀結構，去除部分鰭狀結構以形成一凹槽，形成一緩衝層於凹槽內，形成一磊晶層於緩衝層上以及去除部分絕緣層以形成一淺溝隔離。
本發明又一實施例揭露一種半導體元件，其主要包含：一基底，一鰭狀結構設於基底上，一緩衝層設於鰭狀結構上，以及一磊晶層設於緩衝層上。其中緩衝層包含三種或三種以上之元素。
12:基底
14:硬遮罩
16:圖案化光阻
18:離子佈植製程
20:井區
22:主動區
24:周邊區
26:凹槽
28:緩衝層
30:磊晶層
32:硬遮罩
34:硬遮罩
36:鰭狀結構
38:淺溝隔離
42:基底
44:鰭狀結構
46:絕緣層
48:凹槽
50:緩衝層
52:磊晶層
54:鰭狀結構
56:淺溝隔離
第1圖至第7圖為本發明第一實施例製作一半導體元件之方法示意圖。
第8圖至第11圖為本發明第二實施例製作一半導體元件之方法示意圖。
請參照第1圖至第7圖，第1圖至第7圖為本發明第一實施例製作一半導體元件之方法示意圖。如第1圖所示，首先提供一基底12，例如一矽基底，其中基底12上可選擇性設有一硬遮罩14，例如一由氧化矽或氮化矽所構成的硬遮罩14，但不侷限於此。然後形成一圖案化遮罩，例如一圖案化光阻16於硬遮罩14表面，並進行一蝕刻製程去除部分硬遮罩14暴露出基底12表面。接著進行一離子佈植製程18，將摻質植入未被圖案化光阻16所遮蔽的基底12內以形成一井區20，藉此於基底12上定義出一主動區22以及一周邊區24。其中設有井區20的基底12較佳於後續製程中製作例如鰭狀結構電晶體等主動元件。
在本實施例中，離子佈植製程18所植入的摻質較佳依據所製作之電晶體的型態而有所不同。以本實施例製作PMOS電晶體為例，所植入的摻質較佳為N型摻質，因此基底12中所形成的井區20較佳為一N型井。若所製備的電晶體為NMOS電晶體，可選擇將P型摻質植入基底12中以形成一P型井。然後可於井區20完成後選擇性進行一熱處理製程活化所植入的摻質。
如第2圖所示，接著可再利用圖案化光阻16為遮罩進行另一蝕刻製程，或先去除圖案化光阻16，改利用被圖案化的硬遮罩14來去除部分包含井區20的基底12以形成一凹槽26於基底12內。
需注意的是，本實施例雖以先形成井區20再形成凹槽26為例，但形成井區20與凹槽26的順序並不侷限於此。舉例來說，本發明一實施例又可選擇在形成圖案化光阻16後先以蝕刻去除部分基底12以形成凹槽26，然後再進行一離子佈植製程以形成一井區20於基底12內以及凹槽26下方，此實施例也屬本發明所涵蓋的範圍。
如第3圖所示，然後形成一緩衝層28於凹槽26內之井區20表面。在本實施例中，緩衝層28較佳為一用來調整應力之緩衝材料層，其較佳由鍺化矽所構成，但又可依據製程需求由矽、鍺、碳化矽(SiC)、砷化鎵(GaAs)、磷化銦(InP)、砷化銦鎵(InGaAs)、磷化銦鋁(InAlP)以及III-V族半導體材料中之任何一者或任何組合所構成。
依據本發明一實施例，形成緩衝層28的方式可先以現場摻雜(in-situly doped)方式形成具有摻質之緩衝層28，其中緩衝層28中的摻質較佳選自由磷(P)、砷(As)、銻(Sb)以及鉍(Bi)等電性離子所構成的群組，但不侷限於此。
然後再進行一離子佈植對緩衝層28進行一非晶化(amophization)步驟來改變緩衝層28的晶格結構，其中離子佈植所植入的離子可選自不帶有電性的摻質或帶有電性的摻質。在本實施例中， 若所植入的為不帶有電性的摻質，所形成的緩衝層可做為井區20與後續磊晶層之間的應力調整。若所植入的為帶有電性的摻質，由於所植入的離子與井區20為相同導電型式且離子濃度較井區20為高，所形成的緩衝層28可同時作為井區20與磊晶層之間的應力調整及隔離結構。在本實施例中，所植入的摻質可選自由磷(P)、砷(As)、電性銻(Sb)、鉍(Bi)、碳(C)以及氟(F)所構成的群組，但不侷限於此。
值得注意的是，本實施例以前述現場摻質及額外離子佈植方式植入摻質時可選擇植入前述所列舉中一種或一種以上的摻質至緩衝層28，使最終形成的緩衝層28中包含至少三種或三種以上的元素組合。以前述由鍺化矽所構成的緩衝層28為例，若選擇植入至少一種摻質，例如磷(P)至緩衝層28中，則所形成的緩衝層28便至少包含矽、鍺以及磷等三種元素。若再添入另一種摻質，例如砷(As)至緩衝層28中，則所形成的緩衝層28變包含矽、鍺、磷以及砷等四種元素。迨形成具有摻質之緩衝層28後，可選擇性進行一熱處理製程消除缺陷、修補晶格結構以及再結晶。
如第4圖所示，隨後進行一成長製程，例如利用選擇性磊晶成長方式形成一磊晶層30於緩衝層28上，且形成的磊晶層30上表面較佳高於周圍基底12與硬遮罩14的上表面。在本實施例中，磊晶層30較佳與緩衝層28為相同材料，例如較佳由鍺化矽所構成，但不排除可依據製程需求由矽、鍺、碳化矽(SiC)、砷化鎵(GaAs)、磷化銦(InP)、砷化銦鎵(InGaAs)、磷化銦鋁(InAlP)以及III-V族半導體材料中之任何一者或任何組合所構成。其次，磊晶層30的濃度也較佳大於緩衝層28的 濃度，例如磊晶層30中的鍺濃度較佳大於緩衝層28中的鍺濃度。
除了上述實施例中先以現場摻雜(in-situly doped)方式形成具有摻質之緩衝層28，然後利用一道離子佈植對緩衝層28進行非晶化之後再形成磊晶層30，本發明另一實施例又可選擇以現場摻雜(in-situly doped)方式形成具有摻質之緩衝層28後便直接以磊晶成長方式形成磊晶層30，或是先形成不具任何摻質的緩衝層28，以離子佈植植入帶有電性以及/或不具有電性的離子對緩衝層28進行非晶化，之後再形成磊晶層30於緩衝層28上，這幾種實施例均屬本發明所涵蓋的範圍。
然後如第5圖所示，進行一平坦化製程，例如以化學機械研磨(chemical mechanical polishing,CMP)製程去除部分磊晶層30，並使剩餘的磊晶層30上表面約略切齊周圍的硬遮罩14上表面。需注意的是，若第1圖中的基底12表面一開始不設置任何硬遮罩14，在此階段經由平坦化製程所形成的磊晶層30上表面則較佳切齊基底12表面。
如第6圖所示，接著可再形成至少一硬遮罩於原本的硬遮罩14與磊晶層30上，例如與原本硬遮罩14為相同材料之硬遮罩32以及另一不同材料之硬遮罩34，然後以側壁圖案轉移(sidewall image transfer,SIT)技術或微影暨蝕刻方式去除主動區22的部分硬遮罩34、部分硬遮罩32、部分磊晶層30、部分緩衝層28以及部分基底12以形成鰭狀結構36。由於以SIT或微影暨蝕刻製程形成鰭狀結構為本領域所熟知技藝，在此不另加贅述。
之後如第7圖所示，先沉積一絕緣層(圖未示)覆蓋周邊區24的硬遮罩34以及主動區22的鰭狀結構36並使絕緣層高於各鰭狀結構36頂部，然後進行一平坦化製程，例如利用化學機械研磨製程去除部分絕緣層、硬遮罩34、32與硬遮罩14，使剩餘的絕緣層上表面與鰭狀結構36的磊晶層30上表面齊平。接著再進行一蝕刻製程，去除部分絕緣層並使剩餘的絕緣層上表面略低於鰭狀結構36上表面，以形成一淺溝隔離38環繞鰭狀結構36。
之後可進行後續鰭狀結構電晶體製程，例如可依據製程需求形成閘極結構於鰭狀結構36上，形成側壁子於閘極結構旁以及源極/汲極區域於側壁子兩側的鰭狀結構36內。接著可形成一接觸洞蝕刻停止層覆蓋閘極結構，然後形成一層間介電層於接觸洞蝕刻停止層上，並選擇性進行一金屬閘極置換(replacement metal gate,RMG)製程將閘極結構轉換為金屬閘極。由於依據金屬閘極置換製程將虛置閘極轉換為金屬閘極乃此領域者所熟知技藝，在此不另加贅述。至此即完成本實施例之一半導體元件的製作。
請參照第8圖至第11圖，第8圖至第11圖為本發明第二實施例製作一半導體元件之方法示意圖。如第8圖所示，首先提供一基底42，例如一矽基底或矽覆絕緣(silicon on insulator,SOI)基板，然後形成至少一鰭狀結構44於基底42上。在本實施例中，鰭狀結構44雖以三根為例，但並不侷限於此，其數量可依據製程需求調整。
依據本發明之較佳實施例，鰭狀結構44較佳透過側壁圖案轉移(sidewall image transfer,SIT)技術製得，其程序大致包括：提供一佈局圖案至電腦系統，並經過適當地運算以將相對應之圖案定義於光罩中。後續可透過光微影及蝕刻製程，以形成多個等距且等寬之圖案化犧牲層於基底上，使其個別外觀呈現條狀。之後依序施行沉積及蝕刻製程，以於圖案化犧牲層之各側壁形成側壁子。繼以去除圖案化犧牲層，並在側壁子的覆蓋下施行蝕刻製程，使得側壁子所構成之圖案被轉移至基底內，再伴隨鰭狀結構切割製程(fin cut)而獲得所需的圖案化結構，例如條狀圖案化鰭狀結構。
除此之外，鰭狀結構44之形成方式又可包含先形成一圖案化遮罩(圖未示)於基底42上，再經過一蝕刻製程，將圖案化遮罩之圖案轉移至基底42中以形成鰭狀結構44。另外，鰭狀結構44之形成方式另也可以是先製作一圖案化硬遮罩層(圖未示)於基底42上，並利用磊晶製程於暴露出於圖案化硬遮罩層之基底42上成長出例如包含矽鍺的半導體層，而此半導體層即可作為相對應的鰭狀結構44。這些形成鰭狀結構44的實施例均屬本發明所涵蓋的範圍。
接著形成一絕緣層46覆蓋鰭狀結構44，並進行一平坦化製程，例如利用CMP去除部分絕緣層46甚至部分鰭狀結構44，使剩餘的絕緣層46上表面與鰭狀結構44上表面切齊。其中絕緣層46較佳由氧化矽所構成，但不侷限於此。
如第9圖所示，然後進行一蝕刻製程，例如以絕緣層46為遮 罩去除部分鰭狀結構44以形成複數個凹槽48。接著形成一緩衝層50於各凹槽48內但不填滿凹槽48，其中緩衝層50較佳由鍺化矽所構成，但又可依據製程需求由矽、鍺、碳化矽(SiC)、砷化鎵(GaAs)、磷化銦(InP)、砷化銦鎵(InGaAs)、磷化銦鋁(InAlP)以及III-V族半導體材料中之任何一者或任何組合所構成。
如同前述第一實施例，形成緩衝層50的方式可先以現場摻雜(in-situly doped)方式形成具有摻質之緩衝層50，其中緩衝層50中的摻質較佳選自由磷(P)、砷(As)、銻(Sb)以及鉍(Bi)等電性離子所構成的群組，但不侷限於此。
然後再進行一離子佈植對緩衝層50進行一非晶化(amophization)步驟來改變緩衝層50的晶格結構，其中離子佈植所植入的離子可選自由磷(P)、砷(As)、電性銻(Sb)、鉍(Bi)、碳(C)以及氟(F)所構成的群組，但不侷限於此。
又如同前述實施例，本實施例以前述現場摻質或額外離子佈植方式植入摻質時可選擇植入前述所列舉中一種或一種以上的摻質至緩衝層50，使最終形成的緩衝層50中包含至少三種或三種以上的元素組合。以前述由鍺化矽所構成的緩衝層50為例，若選擇植入至少一種摻質，例如磷(P)至緩衝層50中，則所形成的緩衝層50便至少包含矽、鍺以及磷等三種元素。
隨後如第10圖所示，進行一成長製程，例如利用選擇性磊晶 成長方式形成一磊晶層52於緩衝層上，且形成的磊晶層50上表面較佳高於周圍絕緣層46上表面。在本實施例中，磊晶層52較佳與緩衝層50為相同材料，例如較佳由鍺化矽所構成，但不排除可依據製程需求由矽、鍺、碳化矽(SiC)、砷化鎵(GaAs)、磷化銦(InP)、砷化銦鎵(InGaAs)、磷化銦鋁(InAlP)以及III-V族半導體材料等中之任何一者或任何組合所構成。其次，磊晶層52的濃度也較佳大於緩衝層50的濃度，例如磊晶層52中的鍺濃度較佳大於緩衝層50中的鍺濃度。
除了上述實施例中先以現場摻雜(in-situly doped)方式形成具有摻質之緩衝層50，然後利用一道離子佈植對緩衝層50進行非晶化之後再形成磊晶層52，本發明另一實施例又可選擇以現場摻雜(in-situly doped)方式形成具有摻質之緩衝層50後便直接以磊晶成長方式形成磊晶層52，或是先形成不具任何摻質的緩衝層50，以離子佈植植入帶有電性以及/或不具有電性的離子對緩衝層50進行非晶化，之後再形成磊晶層52於緩衝層50上，這幾種實施例均屬本發明所涵蓋的範圍。
接著進行一平坦化製程，例如以CMP製程去除部分磊晶層52甚至部分絕緣層46，使剩餘的磊晶層52上表面約略切齊周圍的絕緣層46上表面。在此階段，原本的鰭狀結構44與之後新增的緩衝層50及磊晶層52較佳一同構成新的鰭狀結構54。
如第11圖所示，然後以磊晶層52為遮罩進行另一蝕刻製程，去除部分絕緣層46以形成一淺溝隔離56。
之後可進行後續鰭狀結構電晶體製程，例如可依據製程需求形成閘極結構於鰭狀結構54上，形成側壁子於閘極結構旁以及源極/汲極區域於側壁子兩側的鰭狀結構54內。接著可形成一接觸洞蝕刻停止層覆蓋閘極結構，然後形成一層間介電層於接觸洞蝕刻停止層上，並選擇性進行一金屬閘極置換(replacement metal gate,RMG)製程將閘極結構轉換為金屬閘極。由於依據金屬閘極置換製程將虛置閘極轉換為金屬閘極乃此領域者所熟知技藝，在此不另加贅述。至此即完成本實施例之一半導體元件的製作。
此外，本發明亦可在形成閘極結構於鰭狀結構上之後，才蝕刻部分鰭狀結構以形成複數個凹槽。接著以例如選擇性磊晶成長方式形成一緩衝層於各凹槽內但不填滿凹槽，並以離子佈植將前述之摻質植入緩衝層內，使其非晶化作為應力調整及井區與磊晶層之間的摻雜隔離結構。之後可選擇性進行一熱處理製程，並利用選擇性磊晶成長方式形成一磊晶層於緩衝層上。以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
12:基底
20:井區
22:主動區
24:周邊區
28:緩衝層
30:磊晶層
36:鰭狀結構
38:淺溝隔離

Claims (8)

  1. 一種製作半導體元件的方法，包含：提供一基底；形成一凹槽於該基底內；形成一緩衝層於該凹槽內；進行一離子佈植製程對該緩衝層進行一非晶化步驟；形成一磊晶層於該緩衝層上；以及去除部分該磊晶層、部分該緩衝層以及部分該基底以形成鰭狀結構。
  2. 如申請專利範圍第1項所述之方法，另包含：進行一離子佈植製程以形成一井區於該基底內；以及去除部分該井區以形成該凹槽。
  3. 如申請專利範圍第1項所述之方法，另包含：形成該凹槽；以及進行一離子佈植製程以形成一井區於該基底內以及該凹槽下方。
  4. 如申請專利範圍第1項所述之方法，其中該緩衝層包含鍺化矽。
  5. 如申請專利範圍第1項所述之方法，另包含以現場摻雜(in-situly doped)方式形成具有摻質之該緩衝層。
  6. 如申請專利範圍第5項所述之方法，其中該摻質是選自由磷(P)、砷(As)、銻(Sb)、鉍(Bi)、碳(C)以及氟(F)所構成的群組。
  7. 如申請專利範圍第1項所述之方法，其中該離子佈植製程所植入之摻質是選自由磷(P)、砷(As)、銻(Sb)、鉍(Bi)、碳(C)以及氟(F)所構成的群組。
  8. 如申請專利範圍第1項所述之方法，另包含於形成該緩衝層之後及形成該磊晶層之前進行一熱處理製程。
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