CN105280496B - 具有鳍状结构的半导体元件及其制作方法 - Google Patents

具有鳍状结构的半导体元件及其制作方法 Download PDF

Info

Publication number
CN105280496B
CN105280496B CN201410247402.1A CN201410247402A CN105280496B CN 105280496 B CN105280496 B CN 105280496B CN 201410247402 A CN201410247402 A CN 201410247402A CN 105280496 B CN105280496 B CN 105280496B
Authority
CN
China
Prior art keywords
dielectric layer
fin structure
layer
semiconductor element
epitaxial layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201410247402.1A
Other languages
English (en)
Other versions
CN105280496A (zh
Inventor
简金城
许信国
刘志建
林进富
吴俊元
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to CN201410247402.1A priority Critical patent/CN105280496B/zh
Priority to US14/312,707 priority patent/US9263257B2/en
Priority to US14/979,594 priority patent/US9461150B2/en
Publication of CN105280496A publication Critical patent/CN105280496A/zh
Application granted granted Critical
Publication of CN105280496B publication Critical patent/CN105280496B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明公开一种具有鳍状结构的半导体元件及其制作方法，该半导体元件包含一基底，一鳍状结构设于基底上以及一外延层设于该鳍状结构的一上表面及部分侧壁，其中外延层及该鳍状结构之间包含一锗浓度的线性梯度(linear gradient)。

Description

具有鳍状结构的半导体元件及其制作方法
技术领域
本发明涉及一种具有鳍状结构的半导体元件，尤指一种利用外延材料包覆鳍状结构的半导体元件。
背景技术
近年来，随着各种消费性电子产品不断的朝小型化发展，半导体元件设计的尺寸也不断缩小，以符合高集成度、高效能和低耗电的潮流以及产品需求。
随着场效晶体管(field effect transistors,FETs)元件尺寸持续地缩小，现有平面式(planar)场效晶体管元件的发展已面临制作工艺上的极限。为了克服制作工艺限制，以非平面(non-planar)的场效晶体管元件，例如鳍状场效晶体管(fin field effecttransistor,Fin FET)元件来取代平面晶体管元件已成为目前的主流发展趋势。由于鳍状场效晶体管元件的立体结构可增加栅极与鳍状结构的接触面积，因此，可进一步增加栅极对于载流子通道区域的控制，从而降低小尺寸元件面临的漏极引发能带降低(draininduced barrier lowering,DIBL)效应，并可以抑制短通道效应(short channel effect,SCE)。再者，由于鳍状场效晶体管元件在同样的栅极长度下会具有更宽的通道宽度，因而可获得加倍的漏极驱动电流。甚而，晶体管元件的临界电压(threshold voltage)也可通过调整栅极的功函数而加以调控。
然而，在现有的鳍状场效晶体管元件制作工艺中，利用硅锗外延来对源极/漏极区域施加应力并提升载流子迁移率(carrier mobility)已达到一瓶颈，因此如何改良现有鳍状场效晶体管架构以提升通道区域的载流子迁移率即为现今一重要课题。
发明内容
为解决上述问题，本发明优选实施例是公开一种制作具有鳍状结构的半 导体元件的方法。首先形成一鳍状结构于一基底上，然后形成一第一介电层于基底及鳍状结构上。接着沉积一第二介电层于第一介电层上、回蚀刻部分第二介电层、去除部分第一介电层以暴露出鳍状结构的一顶表面及部分侧壁、形成一外延层并覆盖所暴露的鳍状结构的顶表面及部分侧壁以及去除部分第二介电层。
本发明另一实施例公开一种具有鳍状结构的半导体元件，包含一基底，一鳍状结构设于基底上以及一外延层设于该鳍状结构的一上表面及部分侧壁，其中外延层及该鳍状结构之间包含一锗浓度的线性梯度(linear gradient)。
附图说明
图1至图7是根据本发明优选实施例制作具有鳍状结构的半导体装置的方法示意图。
主要元件符号说明
12 基底 14 鳍状结构
16 第一介电层 18 第二介电层
20 外延层
具体实施方式
为详细揭示本发明的技术实质，下面结合附图举实施例详细说明。图1至图7是根据本发明的一优选实施例所绘示的半导体装置的制作方法示意图。如图1所示，首先提供一基底12，例如一硅基底或硅覆绝缘(silicon on insulator,SOI)基板，然后形成至少一鳍状结构14于基底12上。在本实施例中，鳍状结构14虽以三根为例，但其数量并不以此为限，可依据产品需求进行调整，例如可形成一根或一根以上的鳍状结构14于基底12上。
另外依据本发明的优选实施例，鳍状结构(fin structure)14优选通过侧壁图案转移(sidewall image transfer,SIT)技术制得，其程序大致包括：提供一布局图案至电脑系统，并经过适当地运算以将相对应的图案定义于光掩模中。后续可通过光刻及蚀刻制作工艺，以形成多个等距且等宽的图案化牺牲层于基底上，使其个别外观呈现条状。之后依序施行沉积及蚀刻制作工艺，以于图案化牺牲层的各侧壁形成间隙壁。继以去除图案化牺牲层，并在间隙壁的覆盖下施行蚀刻制作工艺，使得间隙壁所构成的图案被转移至基底内，再伴 随鳍状结构切割制作工艺(fin cut)而获得所需的图案化结构，例如条状图案化鳍状结构。
除此之外，鳍状结构14的形成方式又可包含先形成一图案化掩模(图未示)于基底12上，再经过一蚀刻制作工艺，将图案化掩模的图案转移至基底12中以形成鳍状结构14。另外，鳍状结构14的形成方式另也可以是先制作一图案化硬掩模层(图未示)于基底12上，并利用外延制作工艺于暴露出于图案化硬掩模层的基底12上成长出例如包含硅锗的半导体层，而此半导体层即可作为相对应的鳍状结构14。这些形成鳍状结构14的实施例均属本发明所涵盖的范围。
然后如图2所示，进行一原子层沉积(atomic layer deposition,ALD)制作工艺以形成一第一介电层16并覆盖基底12及鳍状结构14。在本实施例中，第一介电层16优选为一包含氧化硅的氧化层，但不局限于此。
接着如图3所示，沉积一第二介电层18于第一介电层16上，并进行一回蚀刻(etching back)制作工艺，去除部分第二介电层18，使第二介电层18的一顶表面与第一介电层16的顶表面齐平。在本实施例中，第二介电层18优选自由美国应用材料取得的进阶图案化薄膜(advanced pattern film,APF)(商品名)，但不局限于此。另需注意的是，本实施例虽采用由氧化硅所构成的第一介电层16以及由APF所构成的第二介电层18为例，但两者介电层的材料并不局限于此，又可依据产品需求选择任何具有蚀刻选择比的两种不同介电材料来分别形成第一介电层16与第二介电层18，此变化型也属本发明所涵盖的范围。
如图4所示，然后利用第二介电层18为掩模进行一蚀刻制作工艺，例如利用稀释氢氟酸(diluted HF,DHF)为蚀刻剂的湿蚀刻制作工艺来去除部分第一介电层16并暴露出鳍状结构14的一顶表面及部分侧壁。在本实施例中，所暴露出的鳍状结构14高度约略400埃。
随后如图5所示，进行一选择性外延成长制作工艺，形成一外延层20于第一介电层16上并覆盖所暴露的鳍状结构14的顶表面及部分侧壁以及第二介电层18。在本实施例中，外延层20优选包含一晶格大小与鳍状结构14不同的外延结构，而具有一压缩或伸张应力，例如为硅锗层、硅碳层，当然外延结构也可为纯硅或硅磷层等。本实施例以P通道金属氧化半导体(pMOS)而例，故其为硅锗层，且鳍状结构14及外延层20之间优选依据鳍状结构14 的材料包含一锗浓度的线性梯度(linear gradient)。举例来说，本发明可依据产品需求调整鳍状结构14与外延层20中的锗浓度，使锗浓度由鳍状结构14朝外延层20线性递增，或使锗浓度由外延层20朝鳍状结构14线性递增，这些变化型均属本发明所涵盖的范围。
然后如图6所示，进行一平坦化制作工艺，例如一化学机械研磨(chemicalmechanical polishing,CMP)制作工艺及/或回蚀刻制作工艺来平坦化外延层20，使外延层20表面与第二介电层18表面齐平。需注意的是，本实施例虽于形成外延层20后以平坦化制作工艺去除部分外延层20，但不局限于此方式，又可于成长外延层20的时候控制外延层20成长的高度，使外延层20在成长过程中，至少覆盖过鳍状结构14的顶面，优选约略与第二介电层18表面齐平，如此即可省略一道平坦化制作工艺所需的成本，此实施例也属本发明所涵盖的范围。
接着如图7所示，进行另一蚀刻制作工艺，例如以外延层20为掩模去除部分第二介电层18并暴露出部分外延层20侧壁。在本实施例中，剩余的第二介电层18高度优选略高于第一介电层16与外延层20的交界处，且经由前述蚀刻制作工艺后所剩余的第二介电层18表面至外延层20顶表面的距离优选成为后续载流子流通的通道高度(channel height)。至此即完成本发明优选实施例具有鳍状结构的半导体元件的制作。
之后可选择性形成一由硅所构成的硅保护盖(silicon cap)(图未示)于外延层20上并覆盖外延层20的顶表面与侧壁以及部分第二介电层18表面，然后可进行后续一般鳍状场效晶体管的标准制作工艺，例如可于外延层20上沉积多晶硅材料以形成栅极结构，形成轻掺杂漏极与源极/漏极区域等，甚至进行金属栅极置换(replacement metal gate,RMG)制作工艺以制作出具有金属栅极的鳍状场效晶体管。由于这些步骤均属此领域者所熟知技术，在此不另加赘述。
需注意的是，本实施例虽优选于栅极结构形成前于鳍状结构14周围形成前述的第一介电层16、第二介电层18与包覆鳍状结构14的外延层，但不局限于此形成的时间点，本发明又可选择于栅极结构制作完成后依据前述图1至图7的步骤于栅极结构两侧被裸露出的鳍状结构，例如鳍状结构上的预定源极/漏极区域形成如图7中的包覆源极/漏极区域的外延层及周边的第一介电层与第二介电层。其中外延层、第一介电层与第二介电层的相对位置均 可比照图7中各材料层的位置，此变化型也属本发明所涵盖的范围。另外，本实施例所公开的第一介电层16、第二介电层18以及外延层20虽优选由氧化硅、APF及锗化硅所构成，但这三者的材料并不局限于此，又可依据制作工艺需求选择三者不同的材料，或任何具有不同选择比的材料来作为这三个材料层，此变化型也属本发明所涵盖的范围。
请再参照图7，其另公开一种具有鳍状结构的半导体元件。如图7所示，本发明优选实施例的半导体元件包含一基底12、多个鳍状结构14设于基底12上、一外延层20设于鳍状结构14的上表面及部分侧壁、一第一介电层16设于鳍状结构14的部分侧壁上以及一第二介电层18设于第一介电层16上。更具体而言，第一介电层16较加设于外延层20与基底12之间，且是以共形(conformal)方式沿着鳍状结构14侧壁与基底12表面所形成，而第二介电层18的高度则优选高于外延层20及第一介电层16的交界处。再者，如图4至图6所示，外延层20形成于去除部分第一介电层16后的位置，因此后来形成于鳍状结构14侧壁与第二介电层18之间的外延层20膜厚应等于或小于鳍状结构14侧壁与第二介电层18之间的第一介电层16膜厚。
在本实施例中，第一介电层16优选为一包含氧化硅的氧化层，第二介电层18优选自由美国应用材料取得的进阶图案化薄膜(APF)(商品名)，外延层20优选包含一硅锗层，且外延层20与鳍状结构14之间包含一锗浓度的线性梯度(linear gradient)。举例来说，本发明可依据产品需求调整鳍状结构14与外延层20中的锗浓度，使锗浓度由鳍状结构14朝外延层线性递增，形成例如硅锗外延层包覆硅鳍状结构的实施例，或使锗浓度由外延层20朝鳍状结构线性递增，形成例如硅锗外延层包覆硅锗鳍状结构的实施例，这些变化型均属本发明所涵盖的范围。
综上所述，本发明优选于形成栅极结构前先形成一第一介电层于基底与鳍状结构上、沉积一第二介电层于第一介电层、回蚀刻部分第二介电层、去除部分第一介电层并暴露出鳍状结构、形成一外延层并覆盖所暴露出的鳍状结构，最后再去除部分第二介电层。依据上述步骤利用一外延层包覆鳍状结构的上半部，以及外延层与鳍状结构之间锗浓度的线性梯度，本发明可改善后续栅极结构形成后通道区域的载流子迁移率，进而再次提升现有鳍状场效晶体管进入10纳米制作工艺世代后的整体效能。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变 化与修饰，都应属本发明的涵盖范围。

Claims (18)

1.一种制作具有鳍状结构的半导体元件的方法，包含：
形成一鳍状结构于一基底上；
形成一第一介电层于该基底及该鳍状结构上；
沉积一第二介电层于该第一介电层上；
回蚀刻部分该第二介电层；
去除部分该第一介电层以暴露出该鳍状结构的一顶表面及部分侧壁；
形成一外延层并覆盖所暴露的该鳍状结构的顶表面及部分侧壁，该鳍状结构及该外延层之间包含一锗浓度的线性梯度(linear gradient)；以及
去除部分该第二介电层。
2.如权利要求1所述的方法，还包含进行一原子层沉积制作工艺，以形成该第一介电层。
3.如权利要求1所述的方法，还包含回蚀刻部分该第二介电层，使该第二介电层的一顶表面与该第一介电层的顶表面齐平。
4.如权利要求1所述的方法，还包含在去除部分该第二介电层之前平坦化该外延层。
5.如权利要求1所述的方法，其中该第一介电层包含一氧化层。
6.如权利要求1所述的方法，其中该第二介电层包含一进阶图案化薄膜(advancedpattern film,APF)。
7.如权利要求1所述的方法，其中该外延层包含一硅锗层。
8.如权利要求1所述的方法，其中该鳍状结构包含锗化硅。
9.如权利要求1所述的方法，包含一锗浓度由该鳍状结构朝该外延层线性递增。
10.如权利要求1所述的方法，包含一锗浓度由该外延层朝该鳍状结构线性递增。
11.一种具有鳍状结构的半导体元件，包含：
基底；
鳍状结构，设于该基底上；
第一介电层，设于该鳍状结构的部分侧壁上；以及
外延层，设于该鳍状结构的一上表面及部分侧壁，且该外延层直接接触该第一介电层，其中该外延层及该鳍状结构之间包含一锗浓度的线性梯度(linear gradient)。
12.如权利要求11所述的半导体元件，包含一锗浓度由该鳍状结构朝该外延层线性递增。
13.如权利要求11所述的半导体元件，包含一锗浓度由该外延层朝该鳍状结构线性递增。
14.如权利要求11所述的半导体元件，其中该第一介电层设于该外延层及该基底之间。
15.如权利要求11所述的半导体元件，其中该第一介电层包含氧化层。
16.如权利要求11所述的半导体元件，还包含第二介电层，设于该第一介电层上。
17.如权利要求16所述的半导体元件，其中该第二介电层的高度高于该外延层及该第一介电层的交界处。
18.如权利要求16所述的半导体元件，其中该第二介电层包含一进阶图案化薄膜(advanced pattern film,APF)。
CN201410247402.1A 2014-06-05 2014-06-05 具有鳍状结构的半导体元件及其制作方法 Active CN105280496B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201410247402.1A CN105280496B (zh) 2014-06-05 2014-06-05 具有鳍状结构的半导体元件及其制作方法
US14/312,707 US9263257B2 (en) 2014-06-05 2014-06-24 Semiconductor device having fin-shaped structure and method for fabricating the same
US14/979,594 US9461150B2 (en) 2014-06-05 2015-12-28 Method for fabricating semiconductor device with fin-shaped structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410247402.1A CN105280496B (zh) 2014-06-05 2014-06-05 具有鳍状结构的半导体元件及其制作方法

Publications (2)

Publication Number Publication Date
CN105280496A CN105280496A (zh) 2016-01-27
CN105280496B true CN105280496B (zh) 2019-06-11

Family

ID=54770160

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410247402.1A Active CN105280496B (zh) 2014-06-05 2014-06-05 具有鳍状结构的半导体元件及其制作方法

Country Status (2)

Country Link
US (2) US9263257B2 (zh)
CN (1) CN105280496B (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102175854B1 (ko) * 2013-11-14 2020-11-09 삼성전자주식회사 반도체 소자 및 이를 제조하는 방법
CN105990146B (zh) * 2015-02-17 2019-12-17 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法和电子装置
KR102270916B1 (ko) * 2015-04-06 2021-06-29 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US9548388B1 (en) * 2015-08-04 2017-01-17 International Business Machines Corporation Forming field effect transistor device spacers
US9659942B1 (en) * 2015-11-24 2017-05-23 International Business Machines Corporation Selective epitaxy growth for semiconductor devices with fin field-effect transistors (FinFET)
US9431486B1 (en) * 2015-11-30 2016-08-30 International Business Machines Corporation Channel strain and controlling lateral epitaxial growth of the source and drain in FinFET devices
US10483378B2 (en) * 2017-08-31 2019-11-19 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial features confined by dielectric fins and spacers
US10763255B2 (en) * 2018-08-14 2020-09-01 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US11101347B2 (en) * 2018-11-29 2021-08-24 Taiwan Semiconductor Manufacturing Company, Ltd. Confined source/drain epitaxy regions and method forming same
US11296227B2 (en) * 2019-10-16 2022-04-05 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing semiconductor devices and semiconductor devices
US20210296506A1 (en) * 2020-03-20 2021-09-23 Intel Corporation Fabrication of non-planar silicon germanium transistors using silicon replacement
US11355395B2 (en) 2020-05-22 2022-06-07 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit in hybrid row height structure

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007046150A1 (ja) * 2005-10-21 2007-04-26 Fujitsu Limited フィン型半導体装置及びその製造方法
CN102171794A (zh) * 2008-12-11 2011-08-31 英特尔公司 用于应变半导体器件的渐变高锗化合物膜

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6800910B2 (en) 2002-09-30 2004-10-05 Advanced Micro Devices, Inc. FinFET device incorporating strained silicon in the channel region
JP2007258485A (ja) * 2006-03-23 2007-10-04 Toshiba Corp 半導体装置及びその製造方法
US20070235763A1 (en) 2006-03-29 2007-10-11 Doyle Brian S Substrate band gap engineered multi-gate pMOS devices
US8659032B2 (en) * 2012-01-31 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET and method of fabricating the same
US8710632B2 (en) * 2012-09-07 2014-04-29 United Microelectronics Corp. Compound semiconductor epitaxial structure and method for fabricating the same
US9112030B2 (en) * 2013-11-04 2015-08-18 United Microelectronics Corp. Epitaxial structure and process thereof for non-planar transistor
CN104733312B (zh) * 2013-12-18 2018-09-07 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管的形成方法
US9704973B2 (en) * 2014-04-01 2017-07-11 Globalfoundries Inc. Methods of forming fins for FinFET semiconductor devices and the selective removal of such fins

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007046150A1 (ja) * 2005-10-21 2007-04-26 Fujitsu Limited フィン型半導体装置及びその製造方法
CN102171794A (zh) * 2008-12-11 2011-08-31 英特尔公司 用于应变半导体器件的渐变高锗化合物膜

Also Published As

Publication number Publication date
US9263257B2 (en) 2016-02-16
US20160111527A1 (en) 2016-04-21
US20150357190A1 (en) 2015-12-10
US9461150B2 (en) 2016-10-04
CN105280496A (zh) 2016-01-27

Similar Documents

Publication Publication Date Title
CN105280496B (zh) 具有鳍状结构的半导体元件及其制作方法
CN104051539B (zh) 形成FinFET半导体设备的低缺陷取代鳍部的方法及其所产生的设备
CN103050533B (zh) 用于三维晶体管应用的采用等离子体掺杂和蚀刻的选择性鳍成形工艺
CN103915345B (zh) 半导体器件及其制造方法
CN103177950B (zh) 制造鳍器件的结构和方法
US9318334B2 (en) Method for fabricating semiconductor device
CN106252392B (zh) 半导体元件及其制作方法
CN106711213A (zh) 半导体元件及其制作方法
CN105762068A (zh) 半导体元件及其制作方法
CN105431945B (zh) 具有带有顶部阻挡层的自对准鳍的非平面半导体器件
CN105374871A (zh) 鳍状结构及其形成方法
CN103579007B (zh) 用于鳍式场效应晶体管器件的后栅极隔离区域形成方法
CN110061054A (zh) 半导体元件及其制作方法
US9466699B2 (en) Manufacturing method for vertical channel gate-all-around MOSFET by epitaxy processes
US20150303274A1 (en) Method for manufacturing fin structure
KR20160099537A (ko) 완화된 기판이 없는 nmos 및 pmos 스트레인된 디바이스
CN106449749A (zh) 半导体元件及其制作方法
TW201628193A (zh) 半導體元件及其製作方法
CN110010684B (zh) 半导体元件及其制作方法
CN106486372B (zh) 半导体元件及其制作方法
CN106158748A (zh) 半导体元件及其制作方法
CN103325787B (zh) Cmos器件及其制造方法
CN109830462B (zh) 制作半导体元件的方法
CN105304490A (zh) 半导体结构的制作方法
US20160086952A1 (en) Preventing epi damage for cap nitride strip scheme in a fin-shaped field effect transistor (finfet) device

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant