CN103579007B - 用于鳍式场效应晶体管器件的后栅极隔离区域形成方法 - Google Patents
用于鳍式场效应晶体管器件的后栅极隔离区域形成方法 Download PDFInfo
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- CN103579007B CN103579007B CN201310278544.XA CN201310278544A CN103579007B CN 103579007 B CN103579007 B CN 103579007B CN 201310278544 A CN201310278544 A CN 201310278544A CN 103579007 B CN103579007 B CN 103579007B
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- 238000002955 isolation Methods 0.000 title claims abstract description 69
- 238000000034 method Methods 0.000 title claims abstract description 48
- 230000005669 field effect Effects 0.000 title claims abstract description 11
- 230000015572 biosynthetic process Effects 0.000 title claims description 12
- 239000011513 prestressed concrete Substances 0.000 title description 13
- 230000003647 oxidation Effects 0.000 claims abstract description 23
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000000463 material Substances 0.000 claims description 39
- 150000004767 nitrides Chemical class 0.000 claims description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 230000008021 deposition Effects 0.000 claims description 7
- 239000012212 insulator Substances 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 16
- 238000005530 etching Methods 0.000 description 8
- 230000008569 process Effects 0.000 description 7
- 230000008859 change Effects 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- 238000012545 processing Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
- H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
Claims (18)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/551,659 US8617961B1 (en) | 2012-07-18 | 2012-07-18 | Post-gate isolation area formation for fin field effect transistor device |
US13/551,659 | 2012-07-18 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103579007A CN103579007A (zh) | 2014-02-12 |
CN103579007B true CN103579007B (zh) | 2016-03-23 |
Family
ID=49776007
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201310278544.XA Active CN103579007B (zh) | 2012-07-18 | 2013-07-04 | 用于鳍式场效应晶体管器件的后栅极隔离区域形成方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8617961B1 (zh) |
CN (1) | CN103579007B (zh) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9812336B2 (en) * | 2013-10-29 | 2017-11-07 | Globalfoundries Inc. | FinFET semiconductor structures and methods of fabricating same |
US9305845B2 (en) | 2014-09-04 | 2016-04-05 | International Business Machines Corporation | Self-aligned quadruple patterning process |
CN106158637B (zh) * | 2015-03-31 | 2019-04-26 | 中芯国际集成电路制造(上海)有限公司 | 鳍式场效应晶体管及其形成方法 |
EP3136446A1 (en) | 2015-08-28 | 2017-03-01 | Nederlandse Organisatie voor toegepast- natuurwetenschappelijk onderzoek TNO | Tft device and manufacturing method |
KR102323943B1 (ko) | 2015-10-21 | 2021-11-08 | 삼성전자주식회사 | 반도체 장치 제조 방법 |
US10615255B2 (en) * | 2016-02-12 | 2020-04-07 | International Business Machines Corporation | Fin formation for semiconductor device |
US10128238B2 (en) | 2016-08-09 | 2018-11-13 | International Business Machines Corporation | Integrated circuit having oxidized gate cut region and method to fabricate same |
US9741823B1 (en) | 2016-10-28 | 2017-08-22 | Internation Business Machines Corporation | Fin cut during replacement gate formation |
CN106356305B (zh) * | 2016-11-18 | 2019-05-31 | 上海华力微电子有限公司 | 优化鳍式场效晶体管结构的方法以及鳍式场效晶体管 |
US10784148B2 (en) | 2018-04-20 | 2020-09-22 | International Business Machines Corporation | Forming uniform fin height on oxide substrate |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1839483A (zh) * | 2003-06-25 | 2006-09-27 | 国际商业机器公司 | 高密度finfet集成方案 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6974729B2 (en) | 2002-07-16 | 2005-12-13 | Interuniversitair Microelektronica Centrum (Imec) | Integrated semiconductor fin device and a method for manufacturing such device |
US6770516B2 (en) | 2002-09-05 | 2004-08-03 | Taiwan Semiconductor Manufacturing Company | Method of forming an N channel and P channel FINFET device on the same semiconductor substrate |
US6885055B2 (en) * | 2003-02-04 | 2005-04-26 | Lee Jong-Ho | Double-gate FinFET device and fabricating method thereof |
US6765303B1 (en) * | 2003-05-06 | 2004-07-20 | Advanced Micro Devices, Inc. | FinFET-based SRAM cell |
JP2005116969A (ja) | 2003-10-10 | 2005-04-28 | Toshiba Corp | 半導体装置及びその製造方法 |
KR100578130B1 (ko) * | 2003-10-14 | 2006-05-10 | 삼성전자주식회사 | 핀 전계효과 트랜지스터를 위한 다중 실리콘 핀 및 그형성 방법 |
KR100587672B1 (ko) * | 2004-02-02 | 2006-06-08 | 삼성전자주식회사 | 다마신 공법을 이용한 핀 트랜지스터 형성방법 |
KR100528486B1 (ko) * | 2004-04-12 | 2005-11-15 | 삼성전자주식회사 | 불휘발성 메모리 소자 및 그 형성 방법 |
US7300837B2 (en) | 2004-04-30 | 2007-11-27 | Taiwan Semiconductor Manufacturing Co., Ltd | FinFET transistor device on SOI and method of fabrication |
US7087532B2 (en) | 2004-09-30 | 2006-08-08 | International Business Machines Corporation | Formation of controlled sublithographic structures |
KR100612419B1 (ko) * | 2004-10-19 | 2006-08-16 | 삼성전자주식회사 | 핀 트랜지스터 및 평판 트랜지스터를 갖는 반도체 소자 및그 형성 방법 |
KR100645053B1 (ko) * | 2004-12-28 | 2006-11-10 | 삼성전자주식회사 | 증가된 활성영역 폭을 가지는 반도체 소자 및 그 제조 방법 |
EP2041780B1 (en) | 2006-07-11 | 2012-02-01 | Nxp B.V. | Semiconductor devices and methods of manufacture thereof |
US7772048B2 (en) | 2007-02-23 | 2010-08-10 | Freescale Semiconductor, Inc. | Forming semiconductor fins using a sacrificial fin |
US7989355B2 (en) * | 2009-02-12 | 2011-08-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of pitch halving |
US9245805B2 (en) * | 2009-09-24 | 2016-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Germanium FinFETs with metal gates and stressors |
-
2012
- 2012-07-18 US US13/551,659 patent/US8617961B1/en active Active
-
2013
- 2013-07-04 CN CN201310278544.XA patent/CN103579007B/zh active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1839483A (zh) * | 2003-06-25 | 2006-09-27 | 国际商业机器公司 | 高密度finfet集成方案 |
Also Published As
Publication number | Publication date |
---|---|
CN103579007A (zh) | 2014-02-12 |
US8617961B1 (en) | 2013-12-31 |
US20140024198A1 (en) | 2014-01-23 |
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Effective date of registration: 20171109 Address after: Grand Cayman, Cayman Islands Patentee after: GLOBALFOUNDRIES INC. Address before: American New York Patentee before: Core USA second LLC Effective date of registration: 20171109 Address after: American New York Patentee after: Core USA second LLC Address before: New York grams of Armand Patentee before: International Business Machines Corp. |