CN113113359A - 半导体装置的制造方法 - Google Patents

半导体装置的制造方法 Download PDF

Info

Publication number
CN113113359A
CN113113359A CN202110179221.XA CN202110179221A CN113113359A CN 113113359 A CN113113359 A CN 113113359A CN 202110179221 A CN202110179221 A CN 202110179221A CN 113113359 A CN113113359 A CN 113113359A
Authority
CN
China
Prior art keywords
layer
gate
source
semiconductor
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110179221.XA
Other languages
English (en)
Inventor
陈世强
李威养
林家彬
彭远清
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US16/945,394 external-priority patent/US11374128B2/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN113113359A publication Critical patent/CN113113359A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
    • H01L29/4991—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material comprising an air gap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一种半导体装置的制造方法，包括提供具有基板与鳍片的结构。鳍片具有不同第一半导体材料与第二半导体材料的第一层与第二层。第一层与第二层交替堆叠于基板之上。上述结构还具有齿合鳍片通道区的栅极堆叠以及位于牺牲栅极堆叠侧壁上的栅极间隔物。半导体装置的制造方法还包括：蚀刻鳍片的源极/漏极(S/D)区以产生源极/漏极沟槽；部分地凹蚀于源极/漏极沟槽中露出的第二层，以于第一层的两邻近膜层之间产生间隙；以及于栅极间隔物、第一层与第二层的表面上沉积介电层。介电层部分地填充间隙而保留孔隙，孔隙夹设于第一层的两邻近膜层上的介电层之间。

Description

半导体装置的制造方法
技术领域
本发明实施例涉及一种半导体装置及其制造方法，特别是涉及一种纳米结构场效晶体管装置及其制造方法。
背景技术
电子产业对较小且快速的电子装置的需求不断增长，这些电子装置同时能够支持许多日益复杂且精密的功能。为了满足这些需求，集成电路产业中出现制造低成本、高性能与低功率的集成电路的持续趋势。至今，通过减少集成电路尺寸(例如，最小集成电路部件尺寸)而改善生产效率并降低相关成本，从而在很大的程度上实现了这些目标。然而，此微缩化也增加了集成电路制程的复杂度。因此，欲实现集成电路装置及其性能的持续演进需要在集成电路制程与技术方面具有相似的进展。
近来，为了改善栅极控制而导入多栅极装置。已观察到多栅极装置能够提升栅极-通道耦合、降低关闭电流以及/或减少短通道效应(short channel effects，SCEs)。一种这样的多栅极装置为全绕式栅极(gate-all-around，GAA)装置，其包括可部分或完全地延伸包覆通道区的栅极结构，以于至少两侧提供途径至通道区。全绕式栅极装置使集成电路技术得以大幅微缩化，维持栅极控制并减缓短通道效应，并同时无缝地与常规集成电路制程整合。随着全绕式栅极装置持续微缩化，当减少栅极电极与源极/漏极部件的寄生电容时产生了许多挑战。因此，虽然现有全绕式装置及其制造方法一般已足以满足其预期目的，但并非在所有方面都完全令人满意。
发明内容
本发明实施例提供一种半导体装置的制造方法。半导体装置的制造方法包括：提供具有基板与鳍片的结构，鳍片具有第一半导体材料的第一层及第二半导体材料的第二层，第一半导体材料与第二半导体材料不同，其中第一层与第二层交替堆叠于基板之上，结构还具有牺牲栅极堆叠及栅极间隔物，牺牲栅极堆叠齿合(engaging)鳍片的通道区，且栅极间隔物位于牺牲栅极堆叠的侧壁上；蚀刻鳍片的源极/漏极(S/D)区以产生源极/漏极沟槽；部分地凹蚀于源极/漏极沟槽中露出的第二层，以于第一层的两邻近膜层之间产生间隙(gap)；以及于栅极间隔物、第一层与第二层的表面上沉积介电层，其中介电层部分地填充间隙而保留孔隙，孔隙夹设于第一层的两邻近膜层上的介电层之间。
本发明实施例亦提供一种半导体装置的制造方法。半导体装置的制造方法包括：提供具有基板与鳍片的结构，鳍片具有交替堆叠的第一层与第二层，其中第一层包括第一半导体材料且第二层包括第二半导体材料，第一半导体材料与第二半导体材料不同；蚀刻鳍片的源极/漏极区以产生源极/漏极沟槽；利用等向性干式蚀刻制程部分地凹蚀于源极/漏极沟槽中露出的第二层，以于第一层的两邻近膜层之间产生至少一间隙；于第一层与第二层的表面上沉积介电层，其中介电层部分地填充间隙而保留孔隙，孔隙位于第一层的两邻近膜层上的介电层的两个部分之间；回蚀刻介电层，以露出源极/漏极沟槽中第一层的表面；以及从源极/漏极沟槽中露出的第一层的至少上述表面外延成长第三半导体材料，其中孔隙保留于第一层的两邻近膜层上的介电层的两个部分之间。
本发明实施例亦提供一种半导体装置。半导体装置包括：基板；两个源极/漏极部件，位于基板之上；半导体层，悬于基板之上并连接两个源极/漏极部件；第一介电层，设置于半导体层的两邻近膜层之间；以及气隙，位于第一介电层与其中一个源极/漏极部件之间。
附图说明
以下实施方式与所附图示一并阅读较容易理解本发明实施例。应强调的是，依据在业界的标准做法，各种特征并未按照比例绘制且仅用以说明例示。事实上，可任意地放大或缩小各种部件的尺寸，以清楚地表现出本发明实施例的特征。
图1A与图1B是根据本发明的各种实施方式的多栅极装置制造方法的流程图。
图2A是根据本发明的各种实施方式，多栅极装置在第1A与1B图中方法的制造阶段部分的透视图。
图2B与图3至图11是本发明的各种实施方式，多栅极装置在与图1A与图1B中方法相关的各种制造阶段部分的剖面图。
其中，附图标记说明如下：
10：方法
12，14，16，18，20，22，24，26，28，30，32：操作
100：装置
102：基板
103：鳍片
103a，103b：半导体层
104：隔离结构
105：源极/漏极沟槽
106：牺牲栅极堆叠
107：沟槽
108：源极/漏极部件
110：间隙
112：介电层/内间隔物部件
114：孔隙
116：接触蚀刻停止层
118：层间介电层
124：栅极间隔物
125：栅极沟槽
126：牺牲栅极介电层
127：牺牲栅极电极层
128，130：硬遮罩层
131：栅极电介层
132：功函数金属层
133：金属填充层
135：高介电常数金属栅极堆叠
A-A：线段
C1，C2：厚度
H0，H3：高度
H1，T：厚度
H2：厚度损失
L0，L1，L2，L3：长度
具体实施方式
以下公开提供了许多的实施例或范例，用于实施所提供的标的物的不同元件。各元件和其配置的具体范例描述如下，以简化本发明实施例的说明。当然，这些仅仅是范例，并非用以限定本发明实施例。举例而言，叙述中若提及第一元件形成在第二元件之上，可能包含第一和第二元件直接接触的实施例，也可能包含额外的元件形成在第一和第二元件之间，使得它们不直接接触的实施例。此外，本发明实施例可能在各种范例中重复元件符号以及/或字母。这样的重复是出于简明和清楚的目的，而其本身并不是用以表示所讨论的各种实施例及/或配置之间的关系。
再者，其中可能使用空间相对用词，例如“在……下方”、“在……之下”、“下方的”、“在……之上”、“上方的”等类似用词，是为了便于描述图示中一个(些)元件或部件与另一个(些)元件或部件之间的关系。空间相对用词意欲涵盖使用中或操作中的装置的不同方位，以及图示中所描述的方位。当装置被转向不同方位时(旋转90度或其他方位)，其中所使用的空间相对形容词也将依转向后的方位来解释。再者，以“约(about)”、“大约(approximately)”等类似用词描述一数字或一范围的数字时，除非另有指明，否则根据本发明所属技术领域中具有通常知识者的知识范围并参照本文所揭示的特定技术，这样的用词包含所述数字介于一定变化范围之内的数字(例如介于+-10％之内或是其他变化)。例如，“约5nm”一词可包括4.5nm至5.5nm、4.0nm至5.0nm等的尺寸范围。
本发明实施例总体上是关于一种半导体装置及其制造方法，且特别是关于在全绕式栅极装置中形成内间隔物，全绕式栅极装置如纳米片装置或纳米线装置。内间隔物提供于源极/漏极外延部件与高介电常数金属栅极(high-k metal gate，HKMG)之间。因此，内间隔物的材料会影响源极/漏极外延部件与高介电常数金属栅极之间的寄生电容。本发明实施例提供一种具有孔隙的内间隔物的形成制程，从而减少源极/漏极外延部件与高介电常数金属栅极之间的寄生电容。再者，内间隔物于通道释出制程时作为源极/漏极外延部件的保护层。
图1A与图1B是根据本发明的各种实施方式的多栅极装置100制造方法10的流程图。在一些实施例中，多栅极装置100包括全绕式栅极晶体管。图2A是根据本发明的一些实施方式，多栅极装置100在方法10的制造阶段部分的透视图。图2B与图3至图11是本发明的实施方式，多栅极装置100在与方法10相关的各种制造阶段沿着图2A线段A-A部分的剖面图。方法10包括操作12、14、16、18、20、22、24、26、28、30与32。本发明实施例设想到额外的处理步骤。可在方法10之前、期间与之后提供额外的操作步骤，且在方法10的额外实施例可挪动、取代或删除一些操作步骤。
多栅极装置100可包括于微处理器、存储器以及/或集成电路装置之中。在一些实施例中，多栅极装置100是集成电路芯片、系统单芯片(system on chip，SoC)的一部份，或是包括各种被动与主动微电子装置的一部份，各种被动与主动微电子装置如电阻器、电容器、电感器、二极管、p型场效晶体管、n型场效晶体管、金属氧化物半导体场效晶体管、鳍式场效晶体管、纳米片场效晶体管、纳米线场效晶体管、其他型态的多栅极场效晶体管、互补式金属氧化物半导体晶体管、双极性接面晶体管(bipolar junction transistor，BJT)、横向扩散金属氧化物半导体(laterally diffused MOS，LDMOS)晶体管、高电压晶体管、高频晶体管、其他合适的组件或前述的组合。在一些实施例中，多栅极装置100包括于存储器装置之中，存储器装置如静态随机存取存储器(static random access memory，SRAM)、非易失性随机存取存储器(non-volatile random access memory，NVRAM)、快闪存储器(flashmemory)、电子可抹除可编程只读存储器(electrically erasable programmable readonly memory，EEPROM)、电子可编程只读存储器(electrically programmable read onlymemory，EPROM)、其他合适的存储器型态或前述的组合。为了清楚起见，简化图2A-图2B及图3-图11以较易理解本发明实施例的发明概念。可在多栅极装置100中加入额外的部件，且在多栅极装置100其他的实施例中可取代、修改或删除下述的一些部件。以下配合方法10的实施例描述装置100的制造过程。
在操作12，方法10(图1A)提供装置100的初始结构。接着参照图2A、图2B，装置100包括基板102、从基板102延伸而出的鳍片103、位于基板102之上及鳍片103下部分之间的隔离结构104、鳍片103与隔离结构104之上的牺牲栅极堆叠106以及位于牺牲栅极堆叠106侧壁上的栅极间隔物124。牺牲栅极堆叠106各包括牺牲栅极介电层126、牺牲栅极电极层127及硬遮罩层128与130。鳍片103各包括半导体层103a与103b的堆叠。鳍片103的源极/漏极区于牺牲栅极堆叠106之间的沟槽107中露出。装置100的各种组件于下文进一步描述。
在此实施例中，基板102包括硅。例如。基板102为硅晶圆。或者或还甚者，基板102包括另一元素半导体，例如锗；化合物半导体，例如碳化硅、砷化镓、磷化镓、磷化铟、砷化铟及/或锑化铟；合金半导体，例如硅锗、磷砷化镓、砷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟、及/或磷砷化镓铟；或前述的组合。或者，基板102为绝缘体上覆半导体基板，例如绝缘体上覆硅(silicon-on-insulator，SOI)基板、绝缘体上覆硅锗(silicon germanium-on-insulator，SGOI)基板或绝缘体上覆锗(germanium-on-insulator，GOI)基板。可利用布植氧分离(separation by implantation of oxygen，SIMOX)、晶圆接合及/或其他合适的方法来制造绝缘体上覆半导体基板。取决于装置100的设计需求，基板102可包括各种掺杂区。例如，基板102可包括用于n型全绕式栅极晶体管的p型掺杂区，以及用于p型全绕式栅极晶体管的n型掺杂区。使用p型掺质掺杂p型掺杂区，p型掺质如硼、铟、其他p型掺质或前述的组合。使用n型掺质掺杂n型掺杂区，n型掺质如磷、砷、其他n型掺质或前述的组合。在一些实施中，基板102包括形成具有p型掺质与n型掺质组合的掺杂区。各种掺杂区可直接形成于基板102上以及/或基板102中，例如，提供p井区结构、n井区结构、双井区结构、抬升结构或前述的组合。可进行离子布植制程、扩散制程及/或其他合适的掺杂制程以形成各种掺杂区。
鳍片103各包括以交叉或交替组态垂直(例如，沿着z方向)堆叠的半导体层103a与半导体层103b。在一些实施例中，半导体层103a与半导体层103b以所示的交叉与交替组态逐层外延成长至达到所欲数量的半导体层。在所示的实施例中，鳍片103各包括三层半导体层103a与三层半导体层103b。然而，例如，取决于装置100所欲的通道数量，本发明实施例设想到鳍片103各包括还多或还少层半导体层的实施例。例如，在一些实施例中，鳍片103可各包括两层至十层半导体层103a及两层至十层半导体层103b。半导体层103a的组成与半导体层103b的组成不同，以于后续处理时达到蚀刻选择性及/或不同的氧化速率。例如，半导体层103a与103b可包括不同材料、不同组成原子百分比、不同组成重量百分比及/或其他不同的特性，以于蚀刻制程时达到所欲的蚀刻选择性，蚀刻制程如形成装置100通道区中悬式(suspended)通道层所进行的蚀刻制程。在此实施例中，半导体层103a包括硅，且半导体层103b包括具有与硅不同蚀刻选择性的硅锗。在一些实施例中，半导体层103a与103b可包括相同材料但不同原子百分比，以达到蚀刻选择性及/或不同的氧化速率。例如，半导体层103a与103b可包括硅锗，其中半导体层103a具有第一硅原子百分比及/或第一锗原子百分比，且半导体层103b具有不同的第二硅原子百分比及/或不同的第二锗原子百分比。本发明实施例设想到半导体层103a与103b包括任何组合的半导体材料，其可提供所欲的蚀刻选择性、所欲的氧化速率差异性及/或所欲的性能特性(例如，最大化电流的材料)，其包括本文所揭示的任何半导体材料。在一些实施例中，各层半导体层103a的厚度为约1nm至约10nm、各层半导体层103b的厚度为约1nm至约10nm，且两者厚度可相同或不同。
可利用任何合适的方法从半导体层(103a与103b)堆叠图案化鳍片103。例如，可使用包括双重图案化或多重图案化制程的一或多道光学微影(photolithography)制程图案化鳍片103。一般来说，双重图案化或多重图案化制程结合了微影制程与自对准制程，以创建出例如，比使用单一、直接微影制程所得的节距还小的图案。例如，在一实施例中，在基板之上形成牺牲层，并使用光学微影制程对其进行图案化。使用自对准制程在图案化的牺牲层旁边形成间隔物。之后去除牺牲层，然后可以使用剩余的间隔物或心轴(mandrel)作为遮罩元件以图案化鳍片103。例如，遮罩元件可用于在基板102之上或之中的半导体层之中蚀刻出凹口，以于基板102上保留鳍片103。蚀刻制程可包括干式蚀刻、湿式蚀刻、反应离子蚀刻(reactive ion etching，RIE)及/或其他合适的制程。例如，干式蚀刻制程可采用含氧气体、含氟气体(例如，CF4、SF6、CH2F2、CHF3及/或C2F6)、含氯气体(例如，Cl2、CHCl3、CCl4及/或BCl3)、含溴气体(例如，HBr及/或CHBr3)、含碘气体、其他合适的气体及/或等离子体及/或前述的组合。例如，湿式蚀刻可包括以稀释氢氟酸(diluted hydrofluoric acid，dHF)、氢氧化钾(KOH)溶液、氨、含氢氟酸(HF)溶液、硝酸(HNO3)及/或醋酸(CH3COOH)或其他合适的湿式蚀刻剂来进行蚀刻。形成鳍片103的许多其他方法实施例可能是合适的。
隔离结构104可包括氧化硅(SiO2)、氮化硅(Si3N4)、氮氧化硅(SiON)、掺氟硅酸盐玻璃(fluoride-doped silicate glass，FSG)、低介电常数介电材料及/或其他合适的绝缘材料。在一实施例中，于基板102中或上方蚀刻出沟槽(例如，鳍片103形成制程的一部份)、以绝缘材料填充沟槽，且对绝缘材料进行化学机械平坦化(chemical mechanicalplanarization，CMP)制程及/或回蚀刻制程而保留剩余的绝缘材料作为隔离结构104。其他型态的绝缘结构也可能是合适的，例如场氧化物与硅局部氧化(local oxidation ofsilicon，LOCOS)。隔离结构104可包括多层结构，例如于基板102与鳍片103的表面上具有一或多层衬层(liner，例如氮化硅)，且于一或多层趁层之上具有主隔离层(例如二氧化硅)。
牺牲栅极介电层126可包括介电材料，例如氧化硅(例如，SiO2)或氮氧化硅(例如，SiON)，且可利用化学氧化、热氧化、原子层沉积(atomic layer deposition，ALD)、化学气相沉积(chemical vapor deposition，CVD)及/或其他合适的方法形成牺牲栅极介电层126。牺牲栅极电极层127可包括多晶硅(polycrystalline silicon，poly-Si)或其他材料，且可利用合适的沉积制程如低压化学气相沉积(low-pressure CVD，LPCVD)及等离子体增强化学气相沉积(plasma-enhanced CVD，PECVD)形成牺牲栅极电极层127。硬遮罩层128可包括氮化硅或其他合适的介电材料，且可利用化学气相沉积或其他合适的方法形成硬遮罩层128。硬遮罩层130可包括氧化硅或其他合适的介电材料，且可利用化学气相沉积或其他合适的方法形成硬遮罩层130。可利用光学微影与蚀刻制程图案化各个膜层126、127、128与130。栅极间隔物124可包括介电材料，例如氧化硅、氮化硅、氮氧化硅、碳化硅、其他介电材料或前述之组合，且可包括一或多层材料。可通过于隔离结构104、鳍片103与牺牲栅极堆叠106之上沉积间隔物材料作为毯覆层(blanket)来形成栅极间隔物124。接着，利用非等向性(anisotropic)蚀刻制程蚀刻间隔物材料以露出隔离结构104、硬遮罩层130与鳍片103的顶表面。间隔物材料位于牺牲栅极堆叠106侧壁上的部分成为栅极间隔物124。邻近的栅极间隔物124提供开口107露出鳍片103位于装置100源极/漏极区中的部分。
在操作14，方法10(图1A)蚀刻鳍片103以形成源极/漏极沟槽105(图3)。操作14可包括一或多道光学微影制程与蚀刻制程。例如，光学微影制程可形成遮罩元件，遮罩元件覆盖装置100将不被蚀刻的区域。遮罩元件提供鳍片103被蚀刻穿过的开口。在一实施例中，如先前所讨论，蚀刻制程可包括干式蚀刻、湿式蚀刻、反应离子蚀刻及/或其他合适的制程。再者，可调谐蚀刻制程使其对鳍片103的材料具选择性，且不会对栅极间隔物124、硬遮罩层130与隔离结构104造成蚀刻(或极微的蚀刻)。半导体层103a与103b的各个表面由于蚀刻制程而于每个源极/漏极沟槽105中露出。
在操作16，方法10(图1A)凹蚀源极/漏极沟槽105之中的半导体层103b，因而如图4所示，于每两层邻近的半导体层103a之间及最底层的半导体层103a与基板102之间产生间隙110。详细而言，图4的右侧绘示出(以放大图呈现)于三个侧边被半导体层103a与103b围绕的其中一个间隙110。间隙110的顶侧与底侧为半导体层103a的表面且间隙110的左侧(或一些其他间隙110的右侧)为半导体层103b的表面。在此实施例中，间隙110是设计为具有长方形或实质上为长方形轮廓，将如稍后所讨论，其协助产生被内间隔物夹设的孔隙(void)。在间隙110的轮廓不是长方形或实质上为长方形(例如，为梯形或漏斗形)的方法中，可轻易地以内间隔物填充间隙110而不保留孔隙于其中，但这样对于本发明实施例是不合意的。如图4所示，间隙110具有总长度L1(沿着x方向)。间隙110的两端可具有略呈圆状的角。间隙110的中间部分(两端除外)具有长度L2(沿着x方向)。长度L1的选择是基于半导体层103a的长度L0、半导体层103b的厚度H1、栅极所欲的通道控制(例如，图11中的栅极135)以及栅极与源极/漏极(例如，图11中的源极/漏极108)之间可接受的耦合(或寄生)电容。在一些实施例中，长度L1介于约6.0nm至约10.0nm之间的范围。在一些实施例中，L1对L0的比例介于约0.05至约0.3之间的范围。若长度L1过长(例如大于10.0nm)或L1：L0的比例过大(例如大于0.3)，在一些情况下，半导体层103a的大部分会没有被栅极所包覆，且栅极的通道控制可能会遭受较差的性能。若长度L1过短(例如小于6.0nm)或L1：L0的比例过小(例如小于0.05)，在一些实施例中，栅极与源极/漏极耦合电容可能会不合意地过高，或者内间隔物(例如，图10中的内间隔物122)可能会过薄而在栅极取代时无法保护源极/漏极不受蚀刻制程影响。在一些实施例中，L1：H1的比例介于1.0至2.0之间的范围。若L1：H1的比例过小(例如小于1.0)，在一些情况下，间隙110可能较易被内间隔物所填充而不会保留孔隙于其中，但这样对于本发明实施例是不合意的。若L1：H1的比例过大(例如大于2.0)，在一些情况下，间隙110可能过于细长以致于内间隔物可能无法沉积于其中。在中间部分中，间隙110实质上为长方形的，亦即，间隙110的上表面与下表面(其为半导体层103a的表面)在中间部分中实质上相互平行(例如，介于±5度的变化之内)。在一些实施例中，在中间部分的左侧与右侧，间隙110可具有略呈圆状的角。在L1介于约6.0nm至约10.0nm之间的范围的实施例中，长度L2可介于约5.0nm至约8.5nm之间的范围。在一些实施例中，L2大于L1的50％，例如为L1的约50％至90％。若L2对L1的比例过小(例如小于50％)，间隙110可能会较易被内间隔物所填充而不会保留孔隙于其中，在一些实施例中，这样会不合意地增加栅极与源极/漏极耦合电容。再者，间隙110在中间部分具有高度H0。高度H0等于(H1+2xH2)，其中H1为半导体层103b的厚度，且H2为半导体层103a于操作16时的厚度损失。在一些实施例中，H1介于约5.0nm至约8.0nm之间的范围，且H2小于1.5nm，例如小于1.0nm。在一些实施例中，H0对H1的比例介于约1.6至1.0。在H2大于1.5nm或H0对H1的比例大于1.6的方法中，间隙110的轮廓可能会比较像梯形而非长方形，且间隙110可能会较易被内间隔物所填充而不会保留孔隙于其中，但这样对于本发明实施例是不合意的。
在各种实施例中，为了产生具有长方形或实质上长方形轮廓的间隙110，操作16进行调谐对半导体层103b的材料具有选择性的蚀刻制程，且其不会对栅极间隔物124、硬遮罩层130、隔离结构104与半导体层103a造成蚀刻(或极微的蚀刻)。可调谐各种蚀刻参数以达到半导体层103b的选择性蚀刻，例如蚀刻剂组成、蚀刻温度、蚀刻溶液浓度、蚀刻时间、蚀刻压力、电源功率(source power)、射频偏压、射频偏压功率(RF bias power)、蚀刻剂流速、其他合适的蚀刻参数或前述的组合。在此实施例中，操作16对半导体层103b进行使用含氟气体(例如，HF、F2、NF3、CF4、SF6、CH2F2、CHF3及/或C2F6)的等向性干式蚀刻制程(例如表面气体/自由基反应制程)，以选择性地蚀刻包括硅锗的半导体层103b。在一些实施例中，可调谐含氟气体对含氧气体(例如，O2)的比例、蚀刻温度及/或射频功率以选择性地蚀刻硅锗或硅。在此实施例中，蚀刻制程完成之后，操作16还对源极/漏极沟槽105中露出的表面进行清洗制程。清洗制程可包括对各个表面施加稀释清氟酸(d-HF)。以上所讨论的间隙110轮廓是蚀刻制程与清洗制程的共同结果。
在操作18，如图5所示，方法10(图1A)沿着装置100各个露出的表面沉积介电层112。详细而言，介电层112沉积于牺牲栅极堆叠106的顶表面上、栅极间隔物124的侧壁上以及半导体层103a与103b于源极/漏极沟槽105中露出的表面上。在各种实施例中，介电层112可包括与半导体层103b及栅极间隔物124不同的材料，以于后续蚀刻制程时达到所欲的蚀刻选择性。在一些实施例中，介电层112包括介电材料，其包括硅、氧、碳、氮、其他合适的材料或前述之组合(例如，氧化硅、氮化硅、氮氧化硅、碳化硅或碳氮氧化硅)。在一些实施例中，介电层112包括低介电常数介电材料。范例低介电常数介电材料包括掺氟硅酸盐玻璃、掺碳氧化硅、
Figure BDA0002940956710000111
(Black
Figure BDA0002940956710000112
应用材料，圣塔克拉拉，加利福尼亚)、干凝胶(xerogel)、气凝胶(aerogel)、非晶氟化碳、聚对二甲苯(parylene)、苯并环丁烯(benzocyclobutene，BCB)、SiLK(陶氏化学，密德兰，密西根)、聚酰亚胺(polyimide)、其他低介电常数介电材料或前述之组合。
如图5的放大局部图(图5的(b)部分)所示，沉积介电层112使其沿着半导体层103a与103b的表面具有均匀或实质上均匀的厚度T。在此实施例中，厚度T是设计在小于H0的一半(亦即，T<1/2*H0)，使得间隙110仅被介电层112部分地填充，而于两邻近的半导体层103a之间垂直地(沿着z方向)保留孔隙114(或气隙(air gap))。详细而言，孔隙114垂直地设置于两邻近半导体层103a上的介电层112之间。再者，孔隙114延伸至图4的间隙110的中间部分之中。如稍后将讨论的，孔隙114有助于减少装置100高介电常数金属栅极及/或源极/漏极部件中的寄生电容。为了达到实质上均匀的厚度T，此实施例中的操作18使用原子层沉积技术来沉积介电层112。使用原子层沉积技术，操作18可控制沉积原子层的数量，因而可控制总厚度T。本发明实施例设想到使用其他沉积技术来沉积介电层112使其具有均匀或实质上均匀的厚度T。在各种实施例中，厚度T可介于约3.0nm至6.0nm之间的范围，例如为约3.5nm至5.5nm之间。若T过大(例如，大于6.0nm)，在一些实施例中，可能会完全填充间隙110而没有保留孔隙于其中，这样会不合意地增加装置100栅极与源极/漏极部件之间的寄生电容。若T过小(例如，小于3.0nm)，膜层112可能会无法于后续的通道释出制程(亦即，移除半导体层103b的蚀刻制程)中承受蚀刻制程。如图5的放大局部图(图5的(c)部分)所示，在一些实施例中，孔隙114实质上为长方形。孔隙114的高度H3(沿着z方向)为(H0-2xT)。在一些实施例中，高度H3介于约0.5至1.5nm之间的范围。在一些实施例中，H3对T的比例(H3：T)是将各种因素纳入考量而设计，各种因素如栅极与源极/漏极部件之间可接受的耦合电容量，以及栅极取代与通道释出制程时内间隔物112的蚀刻抗性。具有较大的H3：T比例一般可能会导致较大的孔隙及较小的耦合电容，而具有较小的H3：T比例一般可能会导致较厚的内间隔物112、较大的蚀刻抗性以及栅极取代与通道释出制程时对源极/漏极部件较佳的保护。在一些实施例中，H3对T的比例(H3：T)是为了上述原因而设计在介于0.15至0.5之间的范围。若H3：T比例太小(例如小于0.15)，在一些情况下，栅极与源极/漏极部件之间的耦合电容可能会无法接受地过高。若H3对T的比例过大(例如大于0.5)，内间隔物112可能会过薄而无法于栅极取代与通道释出制程时保护源极/漏极部件。
在操作20，方法10(图1A)对介电层112进行回蚀刻制程。回蚀刻制程部分地移除介电层112。详细而言，如图6所示，从牺牲栅极堆叠106、栅极间隔物124与基板102的表面移除介电层112。在此实施例中，仅有介电层112位于间隙110中的部分(图4)仍保留在装置100。介电层112的剩余部分视为装置100的内间隔物112(或内间隔物部件112)。再者，如图6的放大局部图所示，内间隔物112部分地填充间隙110，且孔隙114保留设置于两邻近半导体层103a上的内间隔物部件112之间。在所示实施例中，回蚀刻制程放大(或侵蚀)孔隙114的外部部分(亦即，孔隙114远离半导体层103b的部分)。在一些实施例中，回蚀刻制程与蚀刻后清洗制程放大孔隙114一半以上的长度(沿着x方向)。在一些替代实施例中，孔隙114的外部部分没有被放大。在各种实施例中，回蚀刻制程可进行干式蚀刻、湿式蚀刻或反应离子蚀刻，可调谐使其对介电层112的材料具有选择性，且对半导体层103a、牺牲栅极堆叠106与栅极间隔物124造成极微的蚀刻(甚至没有造成蚀刻)。例如，回蚀刻制程可进行等向性湿式蚀刻制程。如以上所讨论，由于装置100的形貌，相较于介电层112于间隙110中的部分，等向性湿式蚀刻制程有效地从各个表面移除介电层112。半导体层102a与基板102的表面由于操作20而于源极/漏极沟槽105中露出。
在操作22，如图7所示，方法10(图1B)从半导体层103a与基板102于源极/漏极沟槽105中露出的表面外延成长源极/漏极部件108。外延制程可使用化学气相沉积技术(例如，气相外延及/或超高真空化学气相沉积)、分子束外延(molecular beam epitaxy)、其他合适的外延成长制程或前述的组合。外延制程可使用气态及/或液态前驱物(presursor)，其与基板102与半导体层103a的组成反应。方法10也可利用n型掺质及/或p型掺质掺杂外延源极/漏极部件108。在一些实施例中，对于n型晶体管，外延源极/漏极部件108包括硅，且可利用碳、磷、砷其他n型掺质或前述的组合掺杂外延源极/漏极部件108(例如，形成Si：C外延源极/漏极部件、Si：P外延源极/漏极部件或Si：C：P外延源极/漏极部件)。在一些实施例中，对于p型晶体管，外延源极/漏极部件108包括硅锗或锗，且可利用硼、其他p型掺质或前述的组合掺杂外延源极/漏极部件108(例如，形成Si：Ge：B外延源极/漏极部件)。在一些实施例中，外延源极/漏极部件108可包括多层外延半导体层，其中多层外延半导体层具有不同程度的掺质密度。再者，掺杂可为原位的(in-situ，亦即，于沉积时通过添加杂质至外延制程的原材料来掺杂)或异位的(ex-situ，例如，通过沉积制程之后进行布植制程来掺杂)。在一些实施例中，进行退火制程(annealing process，例如快速热退火(rapid thermal annealing，RTA)及/或激光退火)活化外延源极/漏极部件108中的掺质。在此实施例中，外延源极/漏极部件108可部分地填充孔隙114。然而，孔隙114的至少一些部分保留。图7于(a)部分绘示出装置100在此制造阶段的剖面图、于(b)部分绘示出膜层103a、103b、112与108的放大图以及于(c)部分还绘示出围绕孔隙114的膜层112与源极/漏极部件108的放大图。如图7的(c)部分所示，孔隙114的一部分保留于装置100中，且于三侧被内间隔物部件112围绕，且于一侧被外延源极/漏极部件108围绕。此外，在此实施例中，孔隙114的外部部分(亦即，远离半导体层103b的部分)被外延源极/漏极部件108填充。孔隙114的剩余部分沿着x方向具有长度L3，且沿着z方向具有高度H3。在此实施例中，孔隙114的剩余部分实质上为长方形，且在替代实施例中可为圆形或不规则形。高度H3是参照图5所讨论，且在一些实施例中，高度H3可介于约0.5至1.5nm之间的范围。在一些实施例中，如以上所讨论，H3对T的比例(H3：T)是设计在0.15至0.5之间的范围。长度L3是由长度L1(参照图4及相关内文)、厚度T(参照图5及相关内文)以及源极/漏极部件108至孔隙114之中的侵入程度(encroachment)所决定。在一些实施例中，长度L3可介于0.5nm至3nm之间的范围。在一些实施例中，L3对T的比例可介于0.1至1.0之间的范围。若L3：T的比例太小(例如小于0.1)，在一些情况下，孔隙114可能会相对过小(与内间隔物112的尺寸相比)，且栅极与源极/漏极部件108之间的耦合电容可能会不可接受地过高。若L3对T的比例太大(例如大于1.0)，内间隔物112可能会太薄而无法于栅极取代与通道释出制程时保护源极/漏极部件108。孔隙114的体积为高度H3与长度L3的函数。若H3与L3太小(例如小于以上讨论它们个别的下端数值)，在一些情况下，孔隙114的体积可能会过小而无法实现显著减少寄生电容。高度H3与长度L3的上端数值(例如分别为1.5nm与3nm)一般受到膜层103b与膜层112的尺寸以及源极/漏极部件108的侵入程度所限制。
操作24，方法10(图1B)于装置100之上形成接触蚀刻停止层(contact etch stoplayer，CESL)116与层间介电(inter-level dielectric，ILD)层118(图8)。如图8所示，接触蚀刻停止层116形成于源极/漏极部件108、牺牲栅极堆叠106及栅极间隔物124的侧壁之上。层间介电层118沉积于接触蚀刻停止层116之上。接触蚀刻停止层116可包括氮化硅、氮氧化硅、具有氧或碳元素的氮化硅及/或其他材料，且可利用化学气相沉积、物理气相沉积(physical vapor deposition，PVD)、原子层沉积或其他合适的方法形成接触蚀刻停止层116。在一实施例中，沿着以上讨论的各个表面沉积接触蚀刻停止层116直到实质上均匀的厚度。层间介电层118可包括四乙氧基硅烷(tetraethoxysilane，TEOS)氧化物、未掺杂硅酸盐玻璃或掺杂氧化硅，掺杂氧化硅如硼磷硅酸盐玻璃(borophosphocilicate glass，BPSG)、掺氟硅酸盐玻璃(fluoride-doped silicate glass，FSG)、磷硅酸盐玻璃(phosphocilicate glass，PSG)、掺硼硅酸盐玻璃(boron doped silicate glass，BSG)及/或其他合适的介电材料。可利用等离子体增强化学气相沉积、流动式化学气相沉积(flowable CVD，FCVD)或其他合适的方法形成层间介电层118。层间介电层118填充牺牲栅极堆叠106之间及源极/漏极部件108之间的各个沟槽。
在操作26，方法10(图1B)从装置100移除牺牲栅极堆叠106，因而形成栅极沟槽125(图9)。在一实施例中，操作26可对装置100进行化学机械平坦化制程，以露出牺牲栅极堆叠106的顶表面。接着，操作26进行一或多道蚀刻制程，以移除如图8所示包括硬遮罩层128与130、牺牲栅极电极层127及牺牲栅极介电层126的牺牲栅极堆叠106。蚀刻制程可包括干式蚀刻、湿式蚀刻、反应离子蚀刻、前述的组合或其他合适的蚀刻制程。调谐蚀刻制程使其对牺牲栅极堆叠106的材料具有选择性，而不会对层间介电层118、接触蚀刻停止层116、栅极间隔物124与鳍片103(包括半导体层103a与103b)造成蚀刻(或极微的蚀刻)。如图9所示，蚀刻制程于两侧的栅极间隔物124之间产生栅极沟槽125。栅极沟槽125露出鳍片103的通道区。
在操作28，方法10(图1B)从栅极沟槽125选择性地移除半导体层103b(图10)。在一些实施例中，此制程也称作为通道释出制程。在图10所示的实施例中，蚀刻制程选择性地蚀刻半导体层103b而没有对半导体层103a造成极微的蚀刻(甚至没有造成蚀刻)，且在一些实施例中，对栅极间隔物124及/或内间隔物部件112造成极微的蚀刻(甚至没有造成蚀刻)。可调谐各种蚀刻参数以达到半导体层103b的选择性蚀刻，例如蚀刻剂组成、蚀刻温度、蚀刻溶液浓度、蚀刻时间、蚀刻压力、电源功率、射频偏压、射频偏压功率、蚀刻剂流速、其他合适的蚀刻参数或前述之组合。蚀刻制程可为干式蚀刻制程、湿式蚀刻制程、其他合适的蚀刻制程或前述的组合。在一些实施例中，干式蚀刻制程(例如表面气体/自由基反应制程)使用含氟气体(例如，HF、F2、NF3、CF4、SF6、CH2F2、CHF3及/或C2F6)以选择性地蚀刻包括硅锗的半导体层103b。在一些实施例中，可调谐含氟气体对含氧气体(例如O2)的比例、蚀刻温度及/或射频功率以选择性地蚀刻硅或硅锗。在一些实施例中，湿式蚀刻制程使用包括氢氧化铵(NH4OH)与水(H2O)的蚀刻溶液以选择性地蚀刻半导体层103b。在一些实施例中，使用氢氯酸(HCl)的化学气相蚀刻制程选择性地蚀刻半导体层103b。内间隔物部件112由于蚀刻选择性而得以保护源极/漏极部件108不受蚀刻制程的影响。如图10中的局部放大图所示，在此实施例中，内间隔物部件112的一侧于栅极沟槽125中露出。内间隔物部件112的另一侧与源极/漏极部件108直接接触。内间隔物部件112与源极/漏极部件108围绕孔隙114。
半导体层103a因为操作28而悬于基板102之上，且于各个栅极沟槽125的两侧连接源极/漏极部件108。在一些实施例中，移除半导体层103b之后，进行蚀刻制程修饰半导体层103a的轮廓以达到所欲的尺寸及/或所欲的形状(例如，圆柱形(例如纳米线)、长方形(例如纳米柱(nanobar))、片形(例如纳米片)等)。取决于装置100的设计需求，本发明实施例还设想到半导体层103a具有次纳米(sub-nanometer)尺寸的实施例。
在操作30，方法10(图1B)于栅极沟槽125中形成高介电常数金属栅极堆叠135，其围绕每层半导体层103a(图11)。在一实施例中，高介电常数金属栅极堆叠135包括栅极介电层131、栅极介电层131之上的功函数金属层132以及功函数金属层132之上的金属填充层133。栅极介电层131可包括高介电常数材料，例如氧化铪、氧化锆、氧化镧、氧化钛、氧化钇、钛酸锶(strontium titanate)。可利用化学氧化、热氧化、原子层沉积、化学气相沉积及/或其他合适的方法形成栅极介电层131。在一些实施例中，高介电常数金属栅极堆叠135还包括栅极介电层131与半导体层103a之间的界面层。界面层可包括氧化硅、氮氧化硅或其他合适的材料。在一些实施例中，功函数金属层132包括n型或p型功函数层。例如，n型功函数层可包括具有足够低的有效功函数的金属，例如钛、铝、碳化钽、碳氮化钽、氮化钽硅或前述的组合。例如，p型功函数层可包括具有足够大的有效功函数的金属，例如氮化钛、氮化钽、钌、钼、钨、铂或前述的组合。可利用化学气相沉积、物理气相沉积、原子层沉积及/或其他合适的制程形成功函数金属层132。在一些实施例中，金属填充层133可包括铝、钨、钴、铜及/或其他合适的材料，且可利用化学气相沉积、物理气相沉积、电镀(plating)及/或其他合适的制程形成金属填充层133。
如图11中的局部放大图所示，在此实施例中，栅极介电层131设置于半导体层103a的两邻近膜层之间并与内间隔物部件112直接接触，且功函数金属层132设置紧邻于栅极介电层131。在一些实施例中，栅极介电层131与功函数金属层132之间可存在额外膜层，以及/或可存在被功函数金属层132围绕的额外膜层。在高介电常数金属栅极堆叠135包括如前文讨论的界面层的实施例中，界面层设置于栅极介电层131与内间隔物部件112之间(亦即，设置界面层使其与内间隔物部件112及半导体层103a的两邻近膜层直接接触)。位于栅极介电层131正上方或正下方的半导体层103a具有厚度C1(沿着z方向)。位于内间隔物部件112正上方或正下方的半导体层103a具有厚度C2(沿着z方向)。在各种实施例中，C1可与C2相同或不同。再者，内间隔物部件112与源极/漏极部件108直接接触之外的部分沿着半导体层103的两邻近膜层的表面具有实质上均匀的厚度。孔隙(或气隙)114被内间隔物部件112与源极/漏极部件108围绕。由于空气具有低介电常数(介电常数为1)，使得孔隙114减少高介电常数金属栅极堆叠135及/或源极/漏极部件108的寄生电容，进而提升装置100的操作速度。于此同时，可选择内间隔物112的材料以于通道释出制程时(参照操作28)提供较高的蚀刻选择性，进而保护源极/漏极部件108。即使介电常数略高于替代材料(但具有较低的蚀刻选择性)，孔隙114可补偿介电常数的差异。
在操作32，方法10(图1B)对装置100进行进一步的制程步骤。例如，方法10可蚀刻装置100源极/漏极区中的层间介电层118与接触蚀刻停止层116以形成露出源极/漏极部件108的接触孔(contact hole)、于源极/漏极部件108上形成硅化物部件、于硅化物部件上形成源极/漏极接触件、形成与高介电常数金属栅极堆叠135连接的栅极接触件以及形成内连线层。
虽然并非意图限制本发明，但本发明实施例提供下述的一或多种优点。第一，本发明实施例提供内间隔物与源极/漏极外延部件之间的孔隙。这样可减少栅极电极与源极/漏极电极的寄生电容，因而提升装置的操作速度。第二，本发明实施例提供调谐孔隙尺寸的方法，例如，通过控制鳍片堆叠中半导体层(例如，硅层与硅锗层)的厚度、控制凹蚀半导体层的制程条件以及控制沉积内间隔物介电层的制程条件。第三，可选择内间隔物材料以于通道释出制程时提供低蚀刻速率，进而保护源极/漏极外延部件不受蚀刻损耗。第四，本发明实施例可轻易地与现有半导体制程整合。
在一范例实施方式中，本发明实施例是关于一种半导体装置的制造方法，其包括：提供具有基板与鳍片的结构，鳍片具有第一半导体材料的第一层及第二半导体材料的第二层，第一半导体材料与第二半导体材料不同，其中第一层与第二层交替堆叠于基板之上，结构还具有牺牲栅极堆叠及栅极间隔物，牺牲栅极堆叠齿合鳍片的通道区，且栅极间隔物位于牺牲栅极堆叠的侧壁上。半导体的制造方法还包括：蚀刻鳍片的源极/漏极区以产生源极/漏极沟槽；部分地凹蚀于源极/漏极沟槽中露出的第二层，以于第一层的两邻近膜层之间产生间隙；以及于栅极间隔物、第一层与第二层的表面上沉积介电层，其中介电层部分地填充间隙而保留孔隙，孔隙夹设于第一层的两邻近膜层上的介电层之间。
在一实施例中，半导体的制造方法还包括对介电层进行回蚀刻制程，以露出源极/漏极沟槽中部份的第一层，其中孔隙的一部分保留夹设于第一层的两邻近膜层上的介电层之间。在又一实施例中，半导体的制造方法包括从第一层于源极/漏极沟槽中露出的部分外延成长第三半导体材料，其中孔隙的上述部分保留夹设于第一层的两邻近膜层上的介电层之间。在半导体的制造方法的还一些实施例中，孔隙被介电层与第三半导体材料所围绕。半导体的制造方法可还包括移除牺牲栅极堆叠以产生栅极沟槽，以及从栅极沟槽移除第二层，以露出栅极沟槽中的介电层。半导体的制造方法可还包括于栅极沟槽中形成高介电常数金属栅极堆叠。
在半导体的制造方法的一些实施例中，部分地凹蚀第二层的步骤包括等向性干式蚀刻制程，等向性干式蚀刻制程对第二半导体材料具有选择性。在一些实施例中，部分地凹蚀第二层的步骤还包括完成等向性干式蚀刻制程之后，实施使用稀释氢氟酸的清洗制程。在半导体的制造方法的一些实施例中，介电层是利用原子层沉积所沉积而成。
在另一范例实施方式中，本发明实施例是关于一种半导体装置的制造方法，其包括：提供具有基板与鳍片的结构，鳍片具有交替堆叠的第一层与第二层，其中第一层包括第一半导体材料且第二层包括第二半导体材料，第一半导体材料与第二半导体材料不同。半导体的制造方法还包括：蚀刻鳍片的源极/漏极区以产生源极/漏极沟槽；利用等向性干式蚀刻制程部分地凹蚀于源极/漏极沟槽中露出的第二层，以于第一层的两邻近膜层之间产生至少一间隙；于第一层与第二层的表面上沉积介电层，其中介电层部分地填充间隙而保留孔隙，孔隙位于第一层的两邻近膜层上的介电层的两个部分之间；回蚀刻介电层，以露出源极/漏极沟槽中第一层的表面；以及从源极/漏极沟槽中露出的第一层的至少上述表面外延成长第三半导体材料，其中孔隙保留于第一层的两邻近膜层上的介电层的两个部分之间。
在半导体的制造方法的一些实施例中，介电层包括低介电常数材料、氧化硅、氮化硅、氮氧化硅、碳化硅、碳氧化硅或碳氮氧化硅。在一些实施例中，介电层是利用原子层沉积所沉积而成，且介电层的厚度是控制在小于第二层的厚度的一半。
在一些实施例中，半导体的制造方法还包括于间隙之中沉积介电层的步骤之前，使用稀释氢氟酸清洗间隙。在结构还包括牺牲栅极堆叠与栅极间隔物层，牺牲栅极堆叠齿合鳍片的通道区，且栅极间隔物位于牺牲栅极堆叠的侧壁上的实施例中，半导体装置的制造方法还包括：于外延成长第三半导体材料的步骤之后，移除牺牲栅极堆叠以产生栅极沟槽；从栅极沟槽移除第二层，以露出栅极沟槽中的介电层；以及于栅极沟槽中形成高介电常数金属栅极堆叠，其中介电层与孔隙设置于高介电常数金属栅极堆叠与第三半导体材料之间。在半导体的制造方法的一些实施例中，部分地凹蚀第二层的步骤对间隙之上的第一层造成厚度损失，且厚度损失小于1.5nm。
在另一范例实施方式中，本发明实施例是关于一种半导体装置，其包括：基板；基板之上的两个源极/漏极部件；悬于基板之上的半导体层，其连接两个源极/漏极部件；设置于半导体层的两邻近膜层之间的第一介电层；以及位于第一介电层与其中一个源极/漏极部件之间的气隙。
在半导体装置的一些实施例中，气隙被第一介电层与其中一个源极/漏极部件所围绕。在一些实施例中，第一介电层沿着半导体层的两邻近膜层的表面上具有实质上均匀的厚度。
在一些实施例中，半导体装置还包括位于半导体层的两邻近膜层之间的高介电常数介电层，其中第一介电层与气隙设置于其中一个源极/漏极部件与高介电常数介电层之间。在还一实施例中，半导体装置包括位于半导体层的两邻近膜层之间的栅极金属层，其中高介电常数介电层设置于第一介电层与栅极金属层之间。
以上概述数个实施例的部件，以便在本发明所属技术领域中具有通常知识者可还易理解本发明实施例的观点。在本发明所属技术领域中具有通常知识者应理解，他们能以本发明实施例为基础，设计或修改其他制程和结构，以达到与在此介绍的实施例相同的目的及/或优势。在本发明所属技术领域中具有通常知识者也应理解到，此类等效的制程和结构并无悖离本发明的精神与范围，且他们能在不违背本发明的精神和范围之下，做各式各样的改变、取代和替换。

Claims (1)

1.一种半导体装置的制造方法，包括：
提供具有一基板与一鳍片的一结构，该鳍片具有一第一半导体材料的多个第一层及一第二半导体材料的多个第二层，该第一半导体材料与该第二半导体材料不同，其中所述第一层与所述第二层交替堆叠于该基板之上，该结构还具有一牺牲栅极堆叠及多个栅极间隔物，该牺牲栅极堆叠齿合该鳍片的一通道区，且所述栅极间隔物位于该牺牲栅极堆叠的侧壁上；
蚀刻该鳍片的一源极/漏极区以产生一源极/漏极沟槽；
部分地凹蚀于该源极/漏极沟槽中露出的所述第二层，以于所述第一层的两邻近膜层之间产生一间隙；以及
于所述栅极间隔物、所述第一层与所述第二层的表面上沉积一介电层，其中该介电层部分地填充该间隙而保留一孔隙，该孔隙夹设于所述第一层的该两邻近膜层上的该介电层之间。
CN202110179221.XA 2020-02-27 2021-02-07 半导体装置的制造方法 Pending CN113113359A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US202062982395P 2020-02-27 2020-02-27
US62/982,395 2020-02-27
US16/945,394 2020-07-31
US16/945,394 US11374128B2 (en) 2020-02-27 2020-07-31 Method and structure for air gap inner spacer in gate-all-around devices

Publications (1)

Publication Number Publication Date
CN113113359A true CN113113359A (zh) 2021-07-13

Family

ID=76709550

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110179221.XA Pending CN113113359A (zh) 2020-02-27 2021-02-07 半导体装置的制造方法

Country Status (2)

Country Link
US (2) US11855220B2 (zh)
CN (1) CN113113359A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023197202A1 (en) * 2022-04-13 2023-10-19 Huawei Technologies Co.,Ltd. Semiconductor structure for gate all around nanosheet device

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9245805B2 (en) 2009-09-24 2016-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Germanium FinFETs with metal gates and stressors
US8816444B2 (en) 2011-04-29 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. System and methods for converting planar design to FinFET design
US8962400B2 (en) 2011-07-07 2015-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. In-situ doping of arsenic for source and drain epitaxy
US8841701B2 (en) 2011-08-30 2014-09-23 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device having a channel defined in a diamond-like shape semiconductor structure
US9236267B2 (en) 2012-02-09 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Cut-mask patterning process for fin-like field effect transistor (FinFET) device
US8847293B2 (en) 2012-03-02 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Gate structure for semiconductor device
US8836016B2 (en) 2012-03-08 2014-09-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structures and methods with high mobility and high energy bandgap materials
US8785285B2 (en) 2012-03-08 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US8860148B2 (en) 2012-04-11 2014-10-14 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for FinFET integrated with capacitor
US8823065B2 (en) 2012-11-08 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US9105490B2 (en) 2012-09-27 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8772109B2 (en) 2012-10-24 2014-07-08 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for forming semiconductor contacts
US9236300B2 (en) 2012-11-30 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Contact plugs in SRAM cells and the method of forming the same
US8853025B2 (en) 2013-02-08 2014-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET/tri-gate channel doping for multiple threshold voltage tuning
US9093514B2 (en) 2013-03-06 2015-07-28 Taiwan Semiconductor Manufacturing Co., Ltd. Strained and uniform doping technique for FINFETs
US9136106B2 (en) 2013-12-19 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for integrated circuit patterning
US9520482B1 (en) 2015-11-13 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of cutting metal gate
KR102435521B1 (ko) * 2016-02-29 2022-08-23 삼성전자주식회사 반도체 소자
US10332986B2 (en) 2016-08-22 2019-06-25 International Business Machines Corporation Formation of inner spacer on nanosheet MOSFET
KR102399071B1 (ko) 2017-11-17 2022-05-17 삼성전자주식회사 반도체 장치
US10553696B2 (en) * 2017-11-21 2020-02-04 International Business Machines Corporation Full air-gap spacers for gate-all-around nanosheet field effect transistors
US10833169B1 (en) 2019-04-22 2020-11-10 Globalfoundries Inc. Metal gate for a field effect transistor and method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023197202A1 (en) * 2022-04-13 2023-10-19 Huawei Technologies Co.,Ltd. Semiconductor structure for gate all around nanosheet device

Also Published As

Publication number Publication date
US20240128376A1 (en) 2024-04-18
US20220336665A1 (en) 2022-10-20
US11855220B2 (en) 2023-12-26

Similar Documents

Publication Publication Date Title
US11302825B2 (en) Self-aligned spacers for multi-gate devices and method of fabrication thereof
US20220336220A1 (en) Method for metal gate cut and structure thereof
US11037826B2 (en) Semiconductor device having merged epitaxial features with arc-like bottom surface and method of making the same
US11923430B2 (en) Gate structure and patterning method for multiple threshold voltages
KR20190024539A (ko) 반도체 디바이스용 핀 구조체
US20210202735A1 (en) Inner Spacers for Gate-All-Around Semiconductor Devices
TWI828962B (zh) 半導體裝置及其形成方法
US20210375858A1 (en) Gate Isolation for Multigate Device
US20240128376A1 (en) Method and structure for air gap inner spacer in gate-all-around devices
TW202133446A (zh) 半導體裝置的製造方法
KR102470490B1 (ko) 핀형 전계효과 트랜지스터용 게이트 에어 스페이서
CN113539964A (zh) 制造半导体装置的方法
US11901236B2 (en) Semiconductor structure with gate-all-around devices and stacked FinFET devices
CN113539962A (zh) 集成电路装置及其制造方法
US20230335586A1 (en) Method and structure for gate-all-around devices
US20240186187A1 (en) Semiconductor structure with gate-all-around devices and stacked finfet devices
US20220367187A1 (en) Semiconductor Device and Method of Manufacture
TW202339278A (zh) 半導體裝置及其製造方法
TW202320162A (zh) 製造半導體裝置的方法
TW202326938A (zh) 半導體結構的製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination