CN106910705B - 具有浅沟槽隔离结构的器件及其制造方法 - Google Patents

具有浅沟槽隔离结构的器件及其制造方法 Download PDF

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CN106910705B
CN106910705B CN201510969869.1A CN201510969869A CN106910705B CN 106910705 B CN106910705 B CN 106910705B CN 201510969869 A CN201510969869 A CN 201510969869A CN 106910705 B CN106910705 B CN 106910705B
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dielectric layer
semiconductor substrate
opening
fins
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CN106910705A (zh
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN201510969869.1A priority Critical patent/CN106910705B/zh
Priority to US15/376,408 priority patent/US10418283B2/en
Priority to EP16204236.0A priority patent/EP3185286B1/en
Publication of CN106910705A publication Critical patent/CN106910705A/zh
Priority to US16/536,047 priority patent/US10832968B2/en
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Abstract

本发明公开了一种具有浅沟槽隔离结构的器件及其制造方法，该制造方法包括：提供半导体衬底，半导体衬底具有第一区域和第二区域，第一区域和第二区域上具有鳍片，鳍片顶部覆盖有硬掩膜层；在半导体衬底上形成第一介质层；在半导体衬底上形成具有第一开口的第一掩膜层，第一开口位于第一区域和第二区域之间；在第一介质层靠近第一开口顶部的部分注入改性离子，去除第一掩膜层；刻蚀第一介质层，在第一开口位置形成第一隔离区，以及在第一区域或第二区域中鳍片之间形成第二隔离区。本发明通过注入改性离子，降低了第一开口处第一介质层的刻蚀速率，使得形成的第一隔离区的厚度更大，改善了器件隔离效果，提高了器件性能。

Description

具有浅沟槽隔离结构的器件及其制造方法
技术领域
本发明涉及半导体工艺技术领域，尤其涉及一种具有浅沟槽隔离结构的器件及其制造方法。
背景技术
在FinFET(Fin Field-Effect Transistor，鳍式场效应晶体管)器件制造工艺中，通常采用STI(Shallow Trench Isolation，浅沟槽隔离)工艺对器件区域及晶体管进行隔离。为了达到更好的隔离效果，对逻辑单元之间的STI厚度要求较高，而各鳍片之间的STI厚度要求较低。然而在诸如14nm工艺的小尺寸器件制造中，器件中的晶体管密度大，用于定义NMOS(N-Mental-Oxide-Semiconductor，N型金属氧化物半导体)区域的NSR(NMOS SiRecess，NMOS硅槽)和用于定于PMOS(P-Mental-Oxide-Semiconductor，P型金属氧化物半导体)区域的PSR(PMOS Si Recess，PMOS硅槽)会出现重叠(Overlapping)，会引起各逻辑单元之间的STI被二次刻蚀，造成最终得到的逻辑单元之间STI厚度变薄，影响了器件的隔离效果。
以图1所示的SRAM(Static Random Access Memory，静态随机存储器)100为例，SRAM 100包括第一NMOS区域101、第一PMOS区域102和第二NMOS区域103，其中第一NMOS区域101包括晶体管PD1和PG1，第一PMOS区域102包括晶体管PU1和PU2。第一NMOS区域101的NSR与第一PMOS区域102的PSR发生重叠，重叠部分为第一重叠区域104。图2示出了图1中SRAM100沿A-A’方向的截面图，如图2所示，其中第一隔离区111为第一NMOS区域101和第一PMOS区域102之间的STI，第二隔离区112是各鳍片之间的STI，鳍片106和107为晶体管PD1的鳍片，鳍片108为晶体管PU1的鳍片，由于存在第一重叠区域104(图2未示出)，造成第一隔离区111被二次刻蚀，得到的第一隔离区111的厚度变薄，若第一隔离区111的厚度较薄，会使得随后对鳍片进行离子注入时，N+/P+离子通过第一隔离区111进入衬底，影响了器件的隔离效果和降低器件性能。因此提高逻辑单元之间STI的厚度成为一个重要的关注点。
发明内容
本发明的发明人发现了上述现有技术中存在问题，并因此针对上述问题中的至少一个问题提出了一种新的技术方案。
本发明的一个目的是提供一种具有浅沟槽隔离结构的器件及其制造方法。
根据本发明的一个方面，提供了一种具有浅沟槽隔离结构的器件制造方法，包括：
提供半导体衬底，半导体衬底具有第一区域和第二区域，第一区域和第二区域上具有鳍片，鳍片顶部覆盖有硬掩膜层；
在半导体衬底上形成第一介质层；
在半导体衬底上形成具有第一开口的第一掩膜层，第一开口位于第一区域和第二区域之间；
在第一介质层靠近第一开口顶部的部分注入改性离子，去除第一掩膜层；
刻蚀第一介质层，在第一开口位置形成第一隔离区，以及在第一区域或第二区域中鳍片之间形成第二隔离区。
可选的，第一隔离区厚度大于第二隔离区厚度。
可选的，在第一介质层靠近第一开口顶部的部分注入改性离子，去除第一掩膜层包括：采用离子注入工艺，将改性离子注入第一介质层靠近第一开口顶部的部分；去除第一掩膜层并退火。
可选的，改性离子为Si、N或C中的一种。
可选的，改性离子注入第一介质层靠近第一开口顶部的部分的厚度为800-1500埃。
可选的，在半导体衬底上形成第一介质层包括：在半导体衬底上形成第一介质层，第一介质层覆盖鳍片；化学机械平坦化第一介质层。
可选的，利用流体化学汽相淀积工艺在半导体衬底上形成第一介质层。
可选的，在化学机械平坦化第一介质层之后，刻蚀第一介质层，直至暴露硬掩膜层。
可选的，在半导体衬底上形成第一介质层的步骤之前包括：在半导体衬底和鳍片侧壁上形成线形氧化层。
可选的，在刻蚀第一介质层之后，去除硬掩膜层。
根据本发明的一个方面，提供了一种具有浅沟槽隔离结构的器件，包括：半导体衬底，半导体衬底具有第一区域和第二区域，第一区域和第二区域上具有鳍片；其中，
第一区域和第二区域之间形成有第一隔离区；
第一隔离区顶部具有改性离子；
第一区域或第二区域中鳍片之间形成有第二隔离区。
可选的，第一隔离区厚度大于第二隔离区厚度。
可选的，改性离子为Si、N或C中的一种。
可选的，改性离子在第一隔离区的厚度为800-1500埃。
可选的，半导体衬底和鳍片侧壁形成有线形氧化层。
本发明的一个优点在于，通过在第一介质层靠近第一开口顶部的部分注入改性离子，降低了第一开口处第一介质层的刻蚀速率，使得形成的第一隔离区的厚度更大，改善了器件隔离效果，提高了器件性能。
通过以下参照附图对本发明的示例性实施例的详细描述，本发明的其他特征及其优点将会变得清楚。
附图说明
构成说明书的一部分的附图描述了本发明的实施例，并且连同说明书一起用于解释本发明的原理。
参照附图，根据下面的详细描述，可以更加清楚地理解本发明，其中：
图1示意性地示出现有技术中具有浅沟槽隔离结构的器件的平面图。
图2示意性地示出现有技术中具有浅沟槽隔离结构的器件的截面图。
图3示出根据本发明的具有浅沟槽隔离结构的器件制造方法的一个实施例的流程图。
图4示出根据本发明的具有浅沟槽隔离结构的器件制造方法的另一个实施例的流程图。
图5A-图5I示意性地示出根据本发明的具有浅沟槽隔离结构的器件制造方法的一个实施例的各个阶段的截面图。
具体实施方式
现在将参照附图来详细描述本发明的各种示例性实施例。应注意到：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不限制本发明的范围。
同时，应当明白，为了便于描述，附图中所示出的各个部分的尺寸并不是按照实际的比例关系绘制的。
以下对至少一个示例性实施例的描述实际上仅仅是说明性的，决不作为对本发明及其应用或使用的任何限制。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为授权说明书的一部分。
在这里示出和讨论的所有示例中，任何具体值应被解释为仅仅是示例性的，而不是作为限制。因此，示例性实施例的其它示例可以具有不同的值。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步讨论。
图3示出根据本发明的具有浅沟槽隔离结构的器件制造方法的一个实施例的流程图。
如图3所示，在步骤302，提供半导体衬底，半导体衬底具有第一区域和第二区域，第一区域和第二区域上具有鳍片，鳍片顶部覆盖有硬掩膜层。第一区域和第二区域可以分别是NMOS区域和PMOS区域，在第一区域和第二区域上具有鳍片，鳍片顶部覆盖的硬掩膜层可以是氮化硅，或者本领域技术人员所知的其它硬掩膜层的材料。
步骤304，在半导体衬底上形成第一介质层。第一介质层可以由二氧化硅淀积形成。在一个实施例中，可以采用流体化学气相淀积工艺(Flowable Chemical VaporDeposition，FCVD)在半导体衬底上形成第一介质层覆盖鳍片，然后进行化学机械平坦化(Chemical-Mechanical Planarization，CMP)。之后刻蚀第一介质层，直至暴露硬掩膜层。
步骤306，在半导体衬底上形成具有第一开口的第一掩膜层，第一开口位于第一区域和第二区域之间。第一掩膜层可以是光致抗蚀剂，或者本领域技术人员所知的其它可作为掩膜层的材料。
步骤308，在第一介质层靠近第一开口顶部的部分注入改性离子，去除第一掩膜层。改性离子可以是Si、N或C中的一种，也可以是本领技术人员所知的其它可降低刻蚀速率的改性离子。在一个实施例中，采用离子注入工艺，将改性离子注入第一介质层靠近第一开口顶部的部分的厚度为800-1500埃，去除第一掩膜层并退火。
步骤310，刻蚀第一介质层，在第一开口位置形成第一隔离区，以及在第一区域或第二区域中鳍片之间形成第二隔离区。经刻蚀后，在第一开口位置形成第一隔离区，用于隔离第一区域和第二区域；在第一区域或第二区域中鳍片之间形成第二隔离区，用于隔离各NMOS或PMOS。在一个实施例中，得到的第一隔离区厚度大于第二隔离区厚度。
图3所示的实施例，通过在第一介质层靠近第一开口顶部的部分注入改性离子，降低了第一开口处第一介质层的刻蚀速率，使得形成的第一隔离区的厚度更大，改善了器件隔离效果，提高了器件性能。
图4示出根据本发明的具有浅沟槽隔离结构的器件制造方法的另一个实施例的流程图。其中步骤402-410与图3中步骤302-310相同或类似，在步骤402和步骤404之间，还包括步骤403，在半导体衬底和鳍片侧壁上形成线形氧化层，用于修复通过刻蚀形成鳍片过程中造成的损伤。
在步骤410之后还包括步骤412，去除硬掩膜层。
图4所示的实施例，通过在半导体衬底和鳍片侧壁上形成线形氧化层，修复了通过刻蚀形成鳍片过程中造成的损伤，进一步提高了器件的性能。
图5A-图5I示意性地示出根据本发明的具有浅沟槽隔离结构的器件制造方法的一个实施例的各个阶段的截面图。
如图5A所示，提供半导体衬底，半导体衬底具有第一区域501和第二区域502，第一区域501上具有鳍片503和鳍片504，第二区域502上具有鳍片505。第一区域501和第二区域502可以分别是NMOS区域和PMOS区域，鳍片503、504和505顶部覆盖有硬掩膜层506，硬掩膜层材料可以是SiN，或者本领域技术人员所知的其他硬掩膜层的材料。
可选的，如图5B所示，在第一区域501、第二区域502上和鳍片503、504、505的侧壁上形成线形氧化层507，用于修复通过刻蚀形成鳍片的过程中造成的损伤。形成的器件结构如图5B所示，在第一区域501、第二区域502以及鳍片503、504和505的侧壁上覆盖有线形氧化层507，鳍片503、504和505顶部覆盖有硬掩膜层506。
如图5C所示，在衬底上形成第一介质层508。第一介质层508可以由二氧化硅淀积形成，覆盖鳍片503、504和505并进行化学机械平坦化。形成的器件结构如图5C所示，第一介质层508在半导体衬底上，覆盖鳍片503、504和505以及硬掩膜层506。
可选的，可以采用FCVD工艺淀积第一介质层508。
如图5D所示，刻蚀第一介质层508，直至暴露硬掩膜层506。形成的器件结构如图5D所示，在第一介质层508之上暴露有硬掩膜层506。
如图5E所示，在衬底上形成具有第一开口510的第一掩膜层509，从而暴露第一区域501和第二区域502之间的第一介质层508。第一掩膜层509可以是光致抗蚀剂，或者本领域技术人员所知的其他可作为掩膜层的材料。形成的器件结构如图5E所示，第一掩膜层509覆盖在第一介质层508之上，并具有第一开口510。第一开口510位于第一区域501和第二区域502之间，暴露该区域的第一介质层508。
如图5F所示，在第一介质层508靠近第一开口510顶部的部分注入改性离子。例如，可以采用离子注入工艺，注入Si、N或C等改性离子中的一个，本领域技术人员所知的其它可降低刻蚀速率的改性离子。形成的器件结构如图5F所示，在第一介质层508靠近第一开口510顶部的部分注入有改性离子。
如图5G所示，去除第一掩膜层509并退火。形成的器件结构如图5G所示，得到的离子注入Si、N或C的厚度为800-1500埃。
如图5H所示，刻蚀第一介质层508，在第一开口510位置形成第一隔离区511，用于隔离第一区域501和第二区域502；在鳍片之间形成第二隔离区512，用于第一/第二区域中各NMOS/PMOS之间的隔离。其中，第一隔离区511厚度大于第二隔离区512。由于第一介质层508靠近第一开口510顶部的部分注入有改性离子，因此该区域刻蚀速率低于第一介质层508的其他区域。形成的器件结构如图5H所示，在第一区域501和第二区域502之间形成有第一隔离区511，各鳍片之间形成有第二隔离区512，其中第一隔离区511厚度大于第二隔离区512，各鳍片顶部覆盖有硬掩膜层506。
如图5I所示，去除硬掩膜层506。形成的器件结构如图5I所示，在第一区域501和第二区域502之间形成有第一隔离区511，各鳍片之间形成有第二隔离区512，其中第一隔离区511厚度大于第二隔离区512。之后，可以使用本领域技术人员所知的方法，对鳍片503、504和505进行N+/P+离子注入等步骤，完成器件的制作。
在图5A-5I所示的实施例中，通过在第一介质层508靠近第一开口510顶部的部分注入改性离子，降低了第一开口510处第一介质层508的刻蚀速率，使得形成的第一隔离区511的厚度更大，改善了器件隔离效果。得到的器件结构如5I所示，第一区域501和第二区域502之间形成有第一隔离区511，第一隔离区511顶部具有改性离子，第区域501和第二区域502上各鳍片之间形成有第二隔离区512，其中第一隔离区511厚度大于第二隔离区512的厚度，可选的，在衬底顶部和各鳍片侧壁覆盖有线形氧化层507。采用本公开的具有浅沟槽隔离结构的器件，能够在之后对鳍片进行离子注入的过程中，避免N+/P+离子通过第一隔离区511进入衬底，提高了器件性能。
至此，已经详细描述了根据本公开实施例的具有浅沟槽隔离结构的器件及其制造方法。为了避免遮蔽本公开的构思，没有描述本领域所公知的一些细节，本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。另外，本说明书公开所教导的各实施例可以自由组合。本领域的技术人员应该理解，可以对上面说明的实施例进行多种修改而不脱离如所附权利要求限定的本公开的精神和范围。

Claims (13)

1.一种具有浅沟槽隔离结构的器件制造方法，其特征在于，包括：
提供半导体衬底，所述半导体衬底具有第一区域和第二区域，所述第一区域和第二区域上具有鳍片，所述鳍片顶部覆盖有硬掩膜层；
在所述半导体衬底上形成第一介质层；
在所述半导体衬底上形成具有第一开口的第一掩膜层，所述第一开口位于所述第一区域和所述第二区域之间；
在所述第一介质层靠近所述第一开口顶部的部分注入改性离子，去除所述第一掩膜层；
刻蚀所述第一介质层，在所述第一开口位置形成第一隔离区，以及在所述第一区域或所述第二区域中所述鳍片之间形成第二隔离区；
其中，所述第一隔离区厚度大于所述第二隔离区厚度。
2.根据权利要求1所述的方法，其特征在于，在所述第一介质层靠近所述第一开口顶部的部分注入改性离子，去除所述第一掩膜层包括：
采用离子注入工艺，将改性离子注入所述第一介质层靠近所述第一开口顶部的部分；
去除所述第一掩膜层并退火。
3.根据权利要求2所述的方法，其特征在于，所述改性离子为Si、N或C中的一种。
4.根据权利要求3所述的方法，其特征在于，所述改性离子注入所述第一介质层靠近所述第一开口顶部的部分的厚度为800-1500埃。
5.根据权利要求1所述的方法，其特征在于，在所述半导体衬底上形成第一介质层包括：
在所述半导体衬底上形成第一介质层，所述第一介质层覆盖所述鳍片；
化学机械平坦化所述第一介质层。
6.根据权利要求5所述的方法，其特征在于，利用流体化学汽相淀积工艺在所述半导体衬底上形成第一介质层。
7.根据权利要求5所述的方法，其特征在于，在化学机械平坦化所述第一介质层之后，刻蚀所述第一介质层，直至暴露所述硬掩膜层。
8.根据权利要求1所述的方法，其特征在于，在所述半导体衬底上形成第一介质层的步骤之前包括：
在所述半导体衬底和所述鳍片侧壁上形成线形氧化层。
9.根据权利要求1-8任一所述的方法，其特征在于，在刻蚀所述第一介质层之后，去除所述硬掩膜层。
10.一种具有浅沟槽隔离结构的器件，其特征在于，包括半导体衬底，所述半导体衬底具有第一区域和第二区域，所述第一区域和第二区域上具有鳍片；其中，
所述第一区域和所述第二区域之间形成有第一隔离区；
所述第一隔离区顶部具有改性离子；
所述第一区域或所述第二区域中所述鳍片之间形成有第二隔离区；
所述第一隔离区厚度大于所述第二隔离区厚度。
11.根据权利要求10所述的器件，其特征在于，所述改性离子为Si、N或C中的一种。
12.根据权利要求11所述的器件，其特征在于，所述改性离子在第一隔离区的厚度为800-1500埃。
13.根据权利要求10所述的器件，其特征在于，所述半导体衬底和所述鳍片侧壁形成有线形氧化层。
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