US20150132966A1 - Method for forming a finfet structure - Google Patents
Method for forming a finfet structure Download PDFInfo
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- US20150132966A1 US20150132966A1 US14/583,813 US201414583813A US2015132966A1 US 20150132966 A1 US20150132966 A1 US 20150132966A1 US 201414583813 A US201414583813 A US 201414583813A US 2015132966 A1 US2015132966 A1 US 2015132966A1
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- 239000011241 protective layer Substances 0.000 claims abstract description 55
- 239000010410 layer Substances 0.000 claims abstract description 52
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 2
- 238000005530 etching Methods 0.000 description 18
- 230000005669 field effect Effects 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
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- 238000000231 atomic layer deposition Methods 0.000 description 2
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- 230000002708 enhancing effect Effects 0.000 description 2
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- 229910019142 PO4 Inorganic materials 0.000 description 1
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
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- 238000007254 oxidation reaction Methods 0.000 description 1
- NBIIXXVUZAFLBC-UHFFFAOYSA-K phosphate Chemical compound [O-]P([O-])([O-])=O NBIIXXVUZAFLBC-UHFFFAOYSA-K 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
Definitions
- the present invention relates generally to fin-type field effect transistors (FinFET) and more particularly to the method for forming an improved FinFET structure that includes multiple gate dielectric thicknesses.
- FinFET fin-type field effect transistors
- Semiconductor structure includes both passive semiconductor devices such as resistors, as well as active devices such as transistors and diodes. Field effect transistor devices are common transistor devices within semiconductor structures.
- Field effect transistor structure and device dimensions have been scaled effectively to increasingly smaller dimensions over the period of several decades.
- Various field effect transistor structures having desirable properties are known in the semiconductor fabrication art.
- One recent advance in transistor technology is the introduction of fin type field effect transistors that are known as FinFET.
- the method for forming individual FinFETs on one substrate comprises: first, a substrate having at least two fin structure is provided, and a first oxide layer is then formed on these two fin structures, next, parts of the first oxide layer, especially the portion that covers on one of the fin structure is then removed, afterwards, a second oxide layer is then formed on the exposed fin structure.
- a substrate having at least two fin structure is provided, and a first oxide layer is then formed on these two fin structures, next, parts of the first oxide layer, especially the portion that covers on one of the fin structure is then removed, afterwards, a second oxide layer is then formed on the exposed fin structure.
- the present invention provides a method for forming a FinFET structure, at least comprising the following steps: first, a substrate is provided, a first region and a second region are defined on the substrate, a first fin structure and a second fin structure are disposed on the substrate, within the first region and the second region respectively, a first oxide layer covering the first fin structure and the second fin structure, next a first protective layer and a second protective layer are entirely formed on the substrate and the first oxide layer in sequence, the second protective layer within the first region is removed, the first protective layer within the first region is then removed, afterwards, the first oxide layer covering the first fin structure and the second protective layer within the second region are removed simultaneously, and a second oxide layer is formed to cover the first fin structure.
- the features of the present invention further comprise a first protective layer and a second protective layer, which are made of different materials, for example, in the embodiment mentioned above.
- the first protective layer comprises silicon nitride
- the second protective layer comprises silicon oxide
- these two dielectric layers protect the oxide region disposed in the substrate and surrounding the fin structure from the damages occurring during the etching processes.
- the silicon nitride first protective layer has high selectivity with the first oxide layer disposed on the fin structure and the oxide region, so during the process for removing the silicon nitride first protective layer, the first oxide layer and the oxide region will not be ruined by the etching processes, thereby enhancing the yield and the performance of the FinFET.
- FIGS. 1-9 are schematic diagrams showing the manufacturing process for forming a FinFET structure according to one preferred embodiment of the present invention.
- FIGS. 1-9 are schematic diagrams showing the manufacturing process for forming a FinFET structure according to one preferred embodiment of the present invention.
- a substrate 10 is provided, such as a silicon substrate.
- the oxide region such as the shallow trench isolation (STI), is used to isolate different components on the substrate 10 .
- a first oxide layer 16 is disposed on the fin structures 12 , but does not cover the oxide region 14 . In other words, the oxide region 14 is exposed.
- STI shallow trench isolation
- first region A and a second region B which are defined on the substrate, the region A and region B comprising at least one fin structure 12 therein.
- devices with different oxide layer thicknesses will be formed in the region A and in the region B respectively, such as the low voltage (LV) devices, the memory, the core devices, electrostatic-sensitive device (ESD), IO devices or high voltage (HV) devices, and these devices have different oxide layer thicknesses.
- LV low voltage
- ESD electrostatic-sensitive device
- HV high voltage
- a first protective layer 18 and a second protective layer 20 are then formed in sequence, covering the first oxide layer 16 and the oxide region 14 .
- the first protective layer 18 comprises silicon nitride
- the second protective layer 20 comprises silicon oxide.
- the first protective layer 18 and the second protective layer 20 are preferably formed through an atomic layer deposition (ALD) process, but not limited thereto.
- a patterned photoresist layer 22 is formed on the second protective layer 20 within the second region B.
- an etching process (not shown) is then performed, to remove parts of the second protective layer 20 which are not covered by the photoresist layer 22 . In other words, only the second protective layer 20 within the first region A is removed. Afterwards, the patterned photoresist layer 22 is then removed.
- the etching process for removing the second protective layer 20 comprises a dilute hydrofluoric acid (DHF) containing cleaning process, a sulfuric acid-hydrogen peroxide mixture (SPM) containing cleaning process or a standard clean 1 (SC1) process, but not limited thereto.
- DHF dilute hydrofluoric acid
- SPM sulfuric acid-hydrogen peroxide mixture
- SC1 standard clean 1
- Another etching process is then performed to remove the first protective layer 18 within the first region A.
- the etching process uses the solvent such as phosphate (H3PO4) which has high selectivity to the silicon nitride and the silicon oxide.
- H3PO4 phosphate
- the first protective layer 18 mainly made of silicon nitride can easily be removed by the etching process, but the second protective layer 20 and the oxide region 14 mainly made of silicon oxide are hardly removed by the etching process, so the oxide region 14 disposed under the first protective layer 18 is not easily ruined by the etching process.
- An etching process (not shown) is performed, to remove the first oxide layer 16 disposed on the fin structure 12 within the region A, and the second protective layer 20 within the second region B simultaneously, so as to completely remove the first oxide layer 16 and to expose the fin structure 12 within the first region A. Since in this embodiment, both the first oxide layer 16 and the second protective layer 20 mainly comprise silicon oxide, they can be removed in a same etching process simultaneously. It is worth noting that, in order to avoid the oxide region 14 being damaged by the etching process, in this step, the etching process preferably selects a dry-etching process. Usually, a dry-etching process has a better performance in controlling the etching rate, so compared with a wet-etching process, a dry-etching process is a preferred choice to avoid the oxide region 14 from being damaged.
- the first protective layer 18 within the first region B is then removed, and as shown in FIG. 9 , a second oxide layer 24 is then formed to cover the exposed fin structure 12 within the first region A.
- the thickness of the first oxide layer 16 and the second oxide layer 24 are different.
- the first oxide layer 16 is thicker than the second oxide layer 24 , thereby achieving two individual FinFETs on one substrate 10 .
- a FinFET 1 and a FinFET 2 are a n-FET device and a p-FET device respectively, or selected from the group of the low voltage (LV) devices, the memory, the core devices, electrostatic-sensitive device (ESD), IO devices or high voltage (HV) devices, and these devices have different oxide layer thicknesses, having individual work functions.
- LV low voltage
- ESD electrostatic-sensitive device
- HV high voltage
- the second oxide layer 24 can be formed before the first protective layer 18 within the second region B is removed.
- the first protective layer 18 within the second region B may remain until the second oxide layer 24 is formed.
- This process should be contained in the scope of the present invention.
- preferably forming the second oxide layer 24 is the final process in order to avoid the second oxide layer 24 being exposed in air for a long time and influencing the performance of the FinFET caused by oxidation.
- the distinguishing feature of the present invention is the use of a first protective layer and a second protective layer, which are made of different materials.
- the first protective layer comprises silicon nitride
- the second protective layer comprises silicon oxide.
- These two dielectric layers protect the oxide region disposed in the substrate and surround the fin structure from the damages occurring during the etching processes.
- the silicon nitride first protective layer has high selectivity with the first oxide layer disposed on the fin structure and the oxide region, during the process for removing the silicon nitride first protective layer, the first oxide layer and the oxide region are not ruined by the etching processes, thereby enhancing the yield and the performance of the FinFET.
Abstract
A method for forming a FinFET structure includes providing a substrate, a first region and a second region being defined on the substrate, a first fin structure and a second fin structure being disposed on the substrate within the first region and the second region respectively. A first oxide layer cover the first fin structure and the second fin structure. Next a first protective layer and a second protective layer are entirely formed on the substrate and the first oxide layer in sequence, the second protective layer within the first region is removed, and the first protective layer within the first region is then removed. Afterwards, the first oxide layer covering the first fin structure and the second protective layer within the second region are removed simultaneously, and a second oxide layer is formed to cover the first fin structure.
Description
- This application is a divisional application of U.S. patent application Ser. No. 14/079,648 filed Nov. 14, 2013, which is herein incorporated by reference in its entirety.
- 1. Field of the Invention
- The present invention relates generally to fin-type field effect transistors (FinFET) and more particularly to the method for forming an improved FinFET structure that includes multiple gate dielectric thicknesses.
- 2. Description of the Prior Art
- Semiconductor structure includes both passive semiconductor devices such as resistors, as well as active devices such as transistors and diodes. Field effect transistor devices are common transistor devices within semiconductor structures.
- Field effect transistor structure and device dimensions have been scaled effectively to increasingly smaller dimensions over the period of several decades. Various field effect transistor structures having desirable properties are known in the semiconductor fabrication art. One recent advance in transistor technology is the introduction of fin type field effect transistors that are known as FinFET.
- In the conventional process, the method for forming individual FinFETs on one substrate comprises: first, a substrate having at least two fin structure is provided, and a first oxide layer is then formed on these two fin structures, next, parts of the first oxide layer, especially the portion that covers on one of the fin structure is then removed, afterwards, a second oxide layer is then formed on the exposed fin structure. However, since there is no other layer that is formed during the process, the fin structure or the isolating region surrounding each fin structure is easily damaged by the etching processes, influencing the yield and the performance of the FinFET.
- The present invention provides a method for forming a FinFET structure, at least comprising the following steps: first, a substrate is provided, a first region and a second region are defined on the substrate, a first fin structure and a second fin structure are disposed on the substrate, within the first region and the second region respectively, a first oxide layer covering the first fin structure and the second fin structure, next a first protective layer and a second protective layer are entirely formed on the substrate and the first oxide layer in sequence, the second protective layer within the first region is removed, the first protective layer within the first region is then removed, afterwards, the first oxide layer covering the first fin structure and the second protective layer within the second region are removed simultaneously, and a second oxide layer is formed to cover the first fin structure.
- The features of the present invention further comprise a first protective layer and a second protective layer, which are made of different materials, for example, in the embodiment mentioned above. The first protective layer comprises silicon nitride, and the second protective layer comprises silicon oxide, and these two dielectric layers protect the oxide region disposed in the substrate and surrounding the fin structure from the damages occurring during the etching processes. Besides, since the silicon nitride first protective layer has high selectivity with the first oxide layer disposed on the fin structure and the oxide region, so during the process for removing the silicon nitride first protective layer, the first oxide layer and the oxide region will not be ruined by the etching processes, thereby enhancing the yield and the performance of the FinFET.
- These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
-
FIGS. 1-9 are schematic diagrams showing the manufacturing process for forming a FinFET structure according to one preferred embodiment of the present invention. - To provide a better understanding of the present invention to users skilled in the technology of the present invention, preferred embodiments are detailed as follows. The preferred embodiments of the present invention are illustrated in the accompanying drawings with numbered elements to clarify the contents and effects to be achieved.
- Please note that the figures are only for illustration and the figures may not be to scale. The scale may be further modified according to different design considerations. When referring to the words “up” or “down” that describe the relationship between components in the text, it is well known in the art and should be clearly understood that these words refer to relative positions that can be inverted to obtain a similar structure, and these structures should therefore not be precluded from the scope of the claims in the present invention.
-
FIGS. 1-9 are schematic diagrams showing the manufacturing process for forming a FinFET structure according to one preferred embodiment of the present invention. As shown inFIG. 1 , first, asubstrate 10 is provided, such as a silicon substrate. There are at least twofin structures 12 on thesubstrate 10, and anoxide region 14, disposed on thesubstrate 10 and surrounding thefin structure 12. Usually, the oxide region such as the shallow trench isolation (STI), is used to isolate different components on thesubstrate 10. Afirst oxide layer 16 is disposed on thefin structures 12, but does not cover theoxide region 14. In other words, theoxide region 14 is exposed. In addition, there are two regions: a first region A and a second region B which are defined on the substrate, the region A and region B comprising at least onefin structure 12 therein. It is worth noting that in the following process, devices with different oxide layer thicknesses will be formed in the region A and in the region B respectively, such as the low voltage (LV) devices, the memory, the core devices, electrostatic-sensitive device (ESD), IO devices or high voltage (HV) devices, and these devices have different oxide layer thicknesses. - Please refer to
FIGS. 2-3 , a firstprotective layer 18 and a secondprotective layer 20 are then formed in sequence, covering thefirst oxide layer 16 and theoxide region 14. In this embodiment, the firstprotective layer 18 comprises silicon nitride, and the secondprotective layer 20 comprises silicon oxide. The firstprotective layer 18 and the secondprotective layer 20 are preferably formed through an atomic layer deposition (ALD) process, but not limited thereto. - Next, please refer to
FIGS. 4-5 . As shown inFIG. 4 , a patternedphotoresist layer 22 is formed on the secondprotective layer 20 within the second region B. As shown inFIG. 5 , an etching process (not shown) is then performed, to remove parts of the secondprotective layer 20 which are not covered by thephotoresist layer 22. In other words, only the secondprotective layer 20 within the first region A is removed. Afterwards, the patternedphotoresist layer 22 is then removed. In this embodiment, the etching process for removing the secondprotective layer 20 comprises a dilute hydrofluoric acid (DHF) containing cleaning process, a sulfuric acid-hydrogen peroxide mixture (SPM) containing cleaning process or a standard clean 1 (SC1) process, but not limited thereto. It is worth noting that, in this step, the firstprotective layer 18 still remains on theoxide region 14 and on thefirst oxide layer 16, helping protect thefirst oxide layer 16 and theoxide region 14 from damages occurring during the etching process. - Please refer to
FIG. 6 . Another etching process is then performed to remove the firstprotective layer 18 within the first region A. In this step, the etching process uses the solvent such as phosphate (H3PO4) which has high selectivity to the silicon nitride and the silicon oxide. In other words, only the firstprotective layer 18 mainly made of silicon nitride can easily be removed by the etching process, but the secondprotective layer 20 and theoxide region 14 mainly made of silicon oxide are hardly removed by the etching process, so theoxide region 14 disposed under the firstprotective layer 18 is not easily ruined by the etching process. - Please refer to
FIG. 7 . An etching process (not shown) is performed, to remove thefirst oxide layer 16 disposed on thefin structure 12 within the region A, and the secondprotective layer 20 within the second region B simultaneously, so as to completely remove thefirst oxide layer 16 and to expose thefin structure 12 within the first region A. Since in this embodiment, both thefirst oxide layer 16 and the secondprotective layer 20 mainly comprise silicon oxide, they can be removed in a same etching process simultaneously. It is worth noting that, in order to avoid theoxide region 14 being damaged by the etching process, in this step, the etching process preferably selects a dry-etching process. Usually, a dry-etching process has a better performance in controlling the etching rate, so compared with a wet-etching process, a dry-etching process is a preferred choice to avoid theoxide region 14 from being damaged. - Afterwards, referring to
FIGS. 8-9 , the firstprotective layer 18 within the first region B is then removed, and as shown inFIG. 9 , asecond oxide layer 24 is then formed to cover the exposedfin structure 12 within the first region A. It is worth noting that the thickness of thefirst oxide layer 16 and thesecond oxide layer 24 are different. Preferably, thefirst oxide layer 16 is thicker than thesecond oxide layer 24, thereby achieving two individual FinFETs on onesubstrate 10. For example, a FinFET 1 and aFinFET 2 are a n-FET device and a p-FET device respectively, or selected from the group of the low voltage (LV) devices, the memory, the core devices, electrostatic-sensitive device (ESD), IO devices or high voltage (HV) devices, and these devices have different oxide layer thicknesses, having individual work functions. - In another case of the present invention, after the second
protective layer 20 within the second region B is removed (corresponding toFIG. 7 ), thesecond oxide layer 24 can be formed before the firstprotective layer 18 within the second region B is removed. In other words, the firstprotective layer 18 within the second region B may remain until thesecond oxide layer 24 is formed. This process should be contained in the scope of the present invention. However, preferably forming thesecond oxide layer 24 is the final process in order to avoid thesecond oxide layer 24 being exposed in air for a long time and influencing the performance of the FinFET caused by oxidation. - In summary, the distinguishing feature of the present invention is the use of a first protective layer and a second protective layer, which are made of different materials. For example, in the embodiment mentioned above, the first protective layer comprises silicon nitride, and the second protective layer comprises silicon oxide. These two dielectric layers protect the oxide region disposed in the substrate and surround the fin structure from the damages occurring during the etching processes. Besides, since the silicon nitride first protective layer has high selectivity with the first oxide layer disposed on the fin structure and the oxide region, during the process for removing the silicon nitride first protective layer, the first oxide layer and the oxide region are not ruined by the etching processes, thereby enhancing the yield and the performance of the FinFET.
- Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims (8)
1. A method for forming a FinFET structure, at least comprising the following steps:
providing a substrate, a first region and a second region being defined on the substrate, a first fin structure and a second fin structure being disposed on the substrate within the first region and the second region respectively, a first oxide layer covering the first fin structure and the second fin structure;
forming a first protective layer and a second protective layer entirely on the substrate and the first oxide layer in sequence;
removing the second protective layer within the first region;
removing the first protective layer within the first region;
removing the first oxide layer covering the first fin structure and the second protective layer within the second region;
removing the first protective layer within the second region after the second protective layer within the second region is removed; and
forming a second oxide layer covering the first fin structure, wherein the second oxide layer is formed before the first protective layer within the second region is removed.
2. The method of claim 1 , wherein the first oxide layer is thicker than the second oxide layer.
3. The method of claim 1 , wherein the first oxide layer covering the first fin structure and the second protective layer within the second region are removed simultaneously.
4. The method of claim 1 , wherein the first protective layer comprises a silicon nitride layer.
5. The method of claim 1 , wherein the second protective layer comprises a silicon oxide layer.
6. The method of claim 1 , further comprising forming an oxide region disposed in the substrate, surrounding the first fin structure and the second fin structure.
7. The method of claim 1 , wherein the surface of the first fin structure is exposed after the first oxide layer is removed from the first fin structure.
8. The method of claim 1 , wherein the method for removing the first oxide layer covering the first fin structure and the second protective layer within the second region comprises a dry-etching process and a wet-etching process.
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US14/079,648 US8951884B1 (en) | 2013-11-14 | 2013-11-14 | Method for forming a FinFET structure |
US14/583,813 US20150132966A1 (en) | 2013-11-14 | 2014-12-29 | Method for forming a finfet structure |
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Cited By (3)
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CN108122842A (en) * | 2016-11-30 | 2018-06-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
US20200176459A1 (en) * | 2018-12-03 | 2020-06-04 | Silicon Storage Technology, Inc. | Split Gate Non-volatile Memory Cells With FINFET Structure And HKMG Memory And Logic Gates, And Method Of Making Same |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8951884B1 (en) * | 2013-11-14 | 2015-02-10 | United Microelectronics Corp. | Method for forming a FinFET structure |
US9418899B1 (en) * | 2015-02-02 | 2016-08-16 | Globalfoundries Inc. | Method of multi-WF for multi-Vt and thin sidewall deposition by implantation for gate-last planar CMOS and FinFET technology |
US10153210B1 (en) * | 2017-06-09 | 2018-12-11 | United Microelectronics Corp. | Semiconductor device and method for fabricating the same |
CN109411415B (en) * | 2018-09-07 | 2021-04-30 | 上海集成电路研发中心有限公司 | Method for forming semiconductor structure |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8951884B1 (en) * | 2013-11-14 | 2015-02-10 | United Microelectronics Corp. | Method for forming a FinFET structure |
Family Cites Families (75)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2947818B2 (en) | 1988-07-27 | 1999-09-13 | 株式会社日立製作所 | Method of filling in fine hole with metal and cvd device for executing same |
US6043138A (en) | 1996-09-16 | 2000-03-28 | Advanced Micro Devices, Inc. | Multi-step polysilicon deposition process for boron penetration inhibition |
US6063698A (en) | 1997-06-30 | 2000-05-16 | Motorola, Inc. | Method for manufacturing a high dielectric constant gate oxide for use in semiconductor integrated circuits |
US6166417A (en) | 1998-06-30 | 2000-12-26 | Intel Corporation | Complementary metal gates and a process for implementation |
US6251761B1 (en) | 1998-11-24 | 2001-06-26 | Texas Instruments Incorporated | Process for polycrystalline silicon gates and high-K dielectric compatibility |
US6380104B1 (en) | 2000-08-10 | 2002-04-30 | Taiwan Semiconductor Manufacturing Company | Method for forming composite gate dielectric layer equivalent to silicon oxide gate dielectric layer |
US6967351B2 (en) | 2001-12-04 | 2005-11-22 | International Business Machines Corporation | Finfet SRAM cell using low mobility plane for cell stability and method for forming |
US6656852B2 (en) | 2001-12-06 | 2003-12-02 | Texas Instruments Incorporated | Method for the selective removal of high-k dielectrics |
US6696345B2 (en) | 2002-01-07 | 2004-02-24 | Intel Corporation | Metal-gate electrode for CMOS transistor applications |
US6492216B1 (en) | 2002-02-07 | 2002-12-10 | Taiwan Semiconductor Manufacturing Company | Method of forming a transistor with a strained channel |
US6818553B1 (en) | 2002-05-15 | 2004-11-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Etching process for high-k gate dielectrics |
US6642066B1 (en) | 2002-05-15 | 2003-11-04 | Advanced Micro Devices, Inc. | Integrated process for depositing layer of high-K dielectric with in-situ control of K value and thickness of high-K dielectric layer |
US20040007561A1 (en) | 2002-07-12 | 2004-01-15 | Applied Materials, Inc. | Method for plasma etching of high-K dielectric materials |
US6762483B1 (en) | 2003-01-23 | 2004-07-13 | Advanced Micro Devices, Inc. | Narrow fin FinFET |
JP4536333B2 (en) | 2003-04-03 | 2010-09-01 | 忠弘 大見 | Semiconductor device and manufacturing method thereof |
TWI231994B (en) | 2003-04-04 | 2005-05-01 | Univ Nat Taiwan | Strained Si FinFET |
US6841484B2 (en) | 2003-04-17 | 2005-01-11 | Chentsau Ying | Method of fabricating a magneto-resistive random access memory (MRAM) device |
US20040212025A1 (en) | 2003-04-28 | 2004-10-28 | Wilman Tsai | High k oxide |
US6911383B2 (en) | 2003-06-26 | 2005-06-28 | International Business Machines Corporation | Hybrid planar and finFET CMOS devices |
US7030430B2 (en) | 2003-08-15 | 2006-04-18 | Intel Corporation | Transition metal alloys for use as a gate electrode and devices incorporating these alloys |
US6818517B1 (en) | 2003-08-29 | 2004-11-16 | Asm International N.V. | Methods of depositing two or more layers on a substrate in situ |
US6921711B2 (en) | 2003-09-09 | 2005-07-26 | International Business Machines Corporation | Method for forming metal replacement gate of high performance |
JP2005086024A (en) | 2003-09-09 | 2005-03-31 | Toshiba Corp | Semiconductor device and method for manufacturing same |
US7135361B2 (en) | 2003-12-11 | 2006-11-14 | Texas Instruments Incorporated | Method for fabricating transistor gate structures and gate dielectrics thereof |
US7160767B2 (en) | 2003-12-18 | 2007-01-09 | Intel Corporation | Method for making a semiconductor device that includes a metal gate electrode |
US7012027B2 (en) | 2004-01-27 | 2006-03-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Zirconium oxide and hafnium oxide etching using halogen containing chemicals |
US20050202624A1 (en) | 2004-03-12 | 2005-09-15 | Infineon Technologies North America Corp. | Plasma ion implantation system |
US7115947B2 (en) | 2004-03-18 | 2006-10-03 | International Business Machines Corporation | Multiple dielectric finfet structure and method |
US7397090B2 (en) | 2004-06-10 | 2008-07-08 | Agency For Science, Technology And Research | Gate electrode architecture for improved work function tuning and method of manufacture |
US7157378B2 (en) | 2004-07-06 | 2007-01-02 | Intel Corporation | Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode |
US7138680B2 (en) | 2004-09-14 | 2006-11-21 | Infineon Technologies Ag | Memory device with floating gate stack |
US7126199B2 (en) | 2004-09-27 | 2006-10-24 | Intel Corporation | Multilayer metal gate electrode |
US7361958B2 (en) | 2004-09-30 | 2008-04-22 | Intel Corporation | Nonplanar transistors with metal gate electrodes |
US7384880B2 (en) | 2004-10-12 | 2008-06-10 | Intel Corporation | Method for making a semiconductor device having a high-k gate dielectric |
TWI237867B (en) | 2004-10-29 | 2005-08-11 | Taiwan Semiconductor Mfg | Method of improving to deposit dielectric |
US20060099830A1 (en) | 2004-11-05 | 2006-05-11 | Varian Semiconductor Equipment Associates, Inc. | Plasma implantation using halogenated dopant species to limit deposition of surface layers |
US7381608B2 (en) | 2004-12-07 | 2008-06-03 | Intel Corporation | Method for making a semiconductor device with a high-k gate dielectric and a metal gate electrode |
US7220647B2 (en) | 2005-02-02 | 2007-05-22 | United Microelectronics Corp. | Method of cleaning wafer and method of manufacturing gate structure |
US20060211259A1 (en) | 2005-03-21 | 2006-09-21 | Maes Jan W | Silicon oxide cap over high dielectric constant films |
US7091551B1 (en) | 2005-04-13 | 2006-08-15 | International Business Machines Corporation | Four-bit FinFET NVRAM memory device |
US7488656B2 (en) | 2005-04-29 | 2009-02-10 | International Business Machines Corporation | Removal of charged defects from metal oxide-gate stacks |
US7501336B2 (en) | 2005-06-21 | 2009-03-10 | Intel Corporation | Metal gate device with reduced oxidation of a high-k gate dielectric |
US7569443B2 (en) | 2005-06-21 | 2009-08-04 | Intel Corporation | Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate |
US7247887B2 (en) | 2005-07-01 | 2007-07-24 | Synopsys, Inc. | Segmented channel MOS transistor |
US7352034B2 (en) | 2005-08-25 | 2008-04-01 | International Business Machines Corporation | Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures |
US7371649B2 (en) | 2005-09-13 | 2008-05-13 | United Microelectronics Corp. | Method of forming carbon-containing silicon nitride layer |
US7435640B2 (en) | 2005-11-08 | 2008-10-14 | United Microelectronics Corp. | Method of fabricating gate structure |
US7309626B2 (en) | 2005-11-15 | 2007-12-18 | International Business Machines Corporation | Quasi self-aligned source/drain FinFET process |
US7547947B2 (en) | 2005-11-15 | 2009-06-16 | International Business Machines Corporation | SRAM cell |
US7462538B2 (en) * | 2005-11-15 | 2008-12-09 | Infineon Technologies Ag | Methods of manufacturing multiple gate CMOS transistors having different gate dielectric materials |
US7824990B2 (en) | 2005-12-05 | 2010-11-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-metal-oxide high-K gate dielectrics |
DE102006001680B3 (en) | 2006-01-12 | 2007-08-09 | Infineon Technologies Ag | Manufacturing method for a FinFET transistor arrangement and corresponding FinFET transistor arrangement |
EP2013900A1 (en) | 2006-04-26 | 2009-01-14 | Koninklijke Philips Electronics N.V. | Non-volatile memory device |
US7601648B2 (en) | 2006-07-31 | 2009-10-13 | Applied Materials, Inc. | Method for fabricating an integrated gate dielectric layer for field effect transistors |
US7531399B2 (en) | 2006-09-15 | 2009-05-12 | Taiwan Semiconductor Manufacturing Company | Semiconductor devices and methods with bilayer dielectrics |
US7569857B2 (en) | 2006-09-29 | 2009-08-04 | Intel Corporation | Dual crystal orientation circuit devices on the same substrate |
US7470570B2 (en) | 2006-11-14 | 2008-12-30 | International Business Machines Corporation | Process for fabrication of FinFETs |
US7968952B2 (en) | 2006-12-29 | 2011-06-28 | Intel Corporation | Stressed barrier plug slot contact structure for transistor performance enhancement |
US7732874B2 (en) | 2007-08-30 | 2010-06-08 | International Business Machines Corporation | FinFET structure using differing gate dielectric materials and gate electrode materials |
JP2009059882A (en) | 2007-08-31 | 2009-03-19 | Nec Electronics Corp | Semiconductor device |
US7659157B2 (en) | 2007-09-25 | 2010-02-09 | International Business Machines Corporation | Dual metal gate finFETs with single or dual high-K gate dielectric |
US20090124097A1 (en) | 2007-11-09 | 2009-05-14 | International Business Machines Corporation | Method of forming narrow fins in finfet devices with reduced spacing therebetween |
US8030709B2 (en) | 2007-12-12 | 2011-10-04 | International Business Machines Corporation | Metal gate stack and semiconductor gate stack for CMOS devices |
US8987092B2 (en) | 2008-04-28 | 2015-03-24 | Spansion Llc | Methods for fabricating memory cells having fin structures with semicircular top surfaces and rounded top corners and edges |
US8048723B2 (en) | 2008-12-05 | 2011-11-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Germanium FinFETs having dielectric punch-through stoppers |
US8268729B2 (en) | 2008-08-21 | 2012-09-18 | International Business Machines Corporation | Smooth and vertical semiconductor fin structure |
US20100062592A1 (en) | 2008-09-09 | 2010-03-11 | Tokyo Electron Limited | Method for forming gate spacers for semiconductor devices |
US7927943B2 (en) | 2008-09-12 | 2011-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for tuning a work function of high-k metal gate devices |
US7915112B2 (en) | 2008-09-23 | 2011-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal gate stress film for mobility enhancement in FinFET device |
US9711373B2 (en) | 2008-09-22 | 2017-07-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating a gate dielectric for high-k metal gate devices |
US7871915B2 (en) | 2008-09-26 | 2011-01-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming metal gates in a gate last process |
US8367515B2 (en) * | 2008-10-06 | 2013-02-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid shallow trench isolation for high-k metal gate device improvement |
US20100167506A1 (en) | 2008-12-31 | 2010-07-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Inductive plasma doping |
US20100219481A1 (en) | 2009-01-09 | 2010-09-02 | Imec | Method for manufacturing a dual work function semiconductor device and the semiconductor device made thereof |
US7910467B2 (en) | 2009-01-16 | 2011-03-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for treating layers of a gate stack |
-
2013
- 2013-11-14 US US14/079,648 patent/US8951884B1/en active Active
-
2014
- 2014-12-29 US US14/583,813 patent/US20150132966A1/en not_active Abandoned
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8951884B1 (en) * | 2013-11-14 | 2015-02-10 | United Microelectronics Corp. | Method for forming a FinFET structure |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106409902A (en) * | 2015-07-31 | 2017-02-15 | 台湾积体电路制造股份有限公司 | Method of forming FinFET gate oxide |
US20170263751A1 (en) * | 2015-07-31 | 2017-09-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of Forming FinFET Gate Oxide |
US10103267B2 (en) * | 2015-07-31 | 2018-10-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming FinFET gate oxide |
CN108122842A (en) * | 2016-11-30 | 2018-06-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
US20200176459A1 (en) * | 2018-12-03 | 2020-06-04 | Silicon Storage Technology, Inc. | Split Gate Non-volatile Memory Cells With FINFET Structure And HKMG Memory And Logic Gates, And Method Of Making Same |
US10937794B2 (en) * | 2018-12-03 | 2021-03-02 | Silicon Storage Technology, Inc. | Split gate non-volatile memory cells with FinFET structure and HKMG memory and logic gates, and method of making same |
KR20210062076A (en) * | 2018-12-03 | 2021-05-28 | 실리콘 스토리지 테크놀로지 인크 | Separated gate nonvolatile memory cells and HKMG memory and logic gates having a FINFET structure, and a method of manufacturing the same |
JP2022511012A (en) * | 2018-12-03 | 2022-01-28 | シリコン ストーリッジ テクノロージー インコーポレイテッド | A split gate non-volatile memory cell having a FinFET structure, an HKMG memory and a logic gate, and a method for manufacturing the same. |
KR102582829B1 (en) * | 2018-12-03 | 2023-09-25 | 실리콘 스토리지 테크놀로지 인크 | Separated gate non-volatile memory cells and HKMG memory and logic gates with FINFET structure, and method of manufacturing the same |
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