CN108122842A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN108122842A CN108122842A CN201611082510.3A CN201611082510A CN108122842A CN 108122842 A CN108122842 A CN 108122842A CN 201611082510 A CN201611082510 A CN 201611082510A CN 108122842 A CN108122842 A CN 108122842A
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- 238000000034 method Methods 0.000 title claims abstract description 74
- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 56
- 238000000926 separation method Methods 0.000 claims abstract description 51
- 230000003647 oxidation Effects 0.000 claims abstract description 27
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 27
- 239000000463 material Substances 0.000 claims description 33
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 26
- 230000015572 biosynthetic process Effects 0.000 claims description 13
- 239000000377 silicon dioxide Substances 0.000 claims description 13
- 239000003989 dielectric material Substances 0.000 claims description 10
- 125000006850 spacer group Chemical group 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 238000011065 in-situ storage Methods 0.000 claims description 7
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 claims description 6
- 229910052753 mercury Inorganic materials 0.000 claims description 6
- 238000005137 deposition process Methods 0.000 claims description 5
- 238000002955 isolation Methods 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 238000000576 coating method Methods 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 238000000151 deposition Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 230000005669 field effect Effects 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000006227 byproduct Substances 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 239000012530 fluid Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- LPXPTNMVRIOKMN-UHFFFAOYSA-M sodium nitrite Chemical compound [Na+].[O-]N=O LPXPTNMVRIOKMN-UHFFFAOYSA-M 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
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- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
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- 239000007788 liquid Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Formation Of Insulating Films (AREA)
Abstract
A kind of semiconductor structure and forming method thereof, wherein method includes：Substrate is provided, the substrate includes external zones and core space, has the first fin on the substrate of external zones, has the second fin on the substrate of core space；Separation layer is formed in the substrate surface, the surface of the separation layer is less than first fin and the top surface of the second fin, and the separation layer covers the partial sidewall surface of first fin and the second fin；First oxide layer is formed using side wall and top surface of the oxidation technology in first fin；The second oxide layer is formed in the described first oxidation layer surface and the second fin side wall and top surface.The semiconductor structure pattern that is formed is good, performance is stablized.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, to a kind of semiconductor structure and forming method thereof.
Background technology
Main devices in integrated circuit especially super large-scale integration are Metal-oxide-semicondutor (metal
Oxide semiconductor, MOS) field-effect transistor, abbreviation MOS transistor.Since MOS transistor is by invention,
Physical dimension is constantly reducing always.In prepared by MOS transistor device and circuit, most challenging be Complementary metal-
Oxidc-Semiconductor (Complementary Metal-Oxide-Semiconductor, CMOS) transistor device.In CMOS
During transistor size constantly reduces, the gate oxide thickness that is made of silica (or silicon oxynitride) reduce cause compared with
High grid leakage current.For this purpose, the solution proposed is, using metal gates and high-k (K) gate dielectric layer
Substitute traditional heavily doped polysilicon grid and silica (or silicon oxynitride) gate dielectric layer.
But the performance of CMOS transistor that the prior art is formed is unstable, reliability is poor.
The content of the invention
The technical problem to be solved by the present invention is to provide a kind of semiconductor structures and forming method thereof, can improve semiconductor junction
Structure performance.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of forming method of semiconductor structure, including：It provides
Substrate, the substrate include external zones and core space, and external zones has the first fin, and core space has second area's fin；Institute
It states substrate surface and forms separation layer, the surface of the separation layer is less than the top surface of first fin and the second fin, and
The separation layer covers the partial sidewall surface of first fin and the second fin；Using oxidation technology in first fin
Side wall and top surface formed the first oxide layer；At the described first oxidation layer surface and fin side wall and the top of core space
Form the second oxide layer.
Optionally, the material of first oxide layer is：Silica.
Optionally, the thickness of first oxide layer is：10 angstroms~20 angstroms.
Optionally, the formation process of first oxide layer includes：Moisture-generation process in situ；The original position steam generation
Technological parameter includes：Temperature is：900 degrees Celsius~1100 degrees Celsius, pressure is：The millimetres of mercury of 0.1 millimetres of mercury~100, H2
Volume flow be：The standard liter/min of 0.2 standard liter/min~20, O2Volume flow be：It marks 5 standard liter/mins~100
Accurate liter/min, the time：5 seconds~300 seconds.
Optionally, the material of second oxide layer is：Silica.
Optionally, second oxidated layer thickness is：5 angstroms~20 angstroms.
Optionally, forming the technique of second oxide layer includes：Atom layer deposition process.
Optionally, further include：After the separation layer is formed, before the first oxide layer is formed, in second fin
The side wall and top surface in portion form the 3rd oxide layer.
Optionally, the step of forming three oxide layer includes：In first fin and second fin portion surface
Form the 3rd oxide-film；Etching removes the 3rd oxide-film of first fin portion surface, forms the 3rd oxide layer.
Optionally, the material of the 3rd oxide layer is：Silica.
Optionally, it is in the thickness of the 3rd oxide layer：10 angstroms~30 angstroms.
Optionally, the forming step of the separation layer includes：Isolation material is formed on substrate, the first fin and the second fin
The bed of material, the surface of the spacer material layer are higher than or are flush to the top of first fin and the second fin；Etch removal portion
Divide the spacer material layer, and expose the side wall and top surface of the first fin of part and the second fin, form separation layer.
Optionally, the forming method of first fin and the second fin includes：Initial substrate is provided；In the initial lining
The part surface at bottom forms mask layer；Using the mask layer as mask, the initial substrate is etched, forms substrate, the first fin
With the second fin.
Optionally, further include：After second oxide layer is formed, in the side wall of first fin and top table
The side wall and top surface of face and the second fin are developed across the dummy gate structure in first fin and the second fin；
The dummy gate structure includes pseudo- gate dielectric layer and the dummy gate layer on pseudo- gate dielectric layer；In separation layer, the first fin
Dielectric layer is formed with the surface of the second fin, the surface of the dielectric layer exposes the pseudo- grid of first fin and the second fin
The surface of pole structure；The dummy gate layer is removed, pseudo- grid opening is formed in the dielectric layer；It is formed in the pseudo- grid opening
Gate structure.
Optionally, the dummy gate structure includes：Positioned at the pseudo- grid opening sidewalls and the gate dielectric layer of lower surface, with
And the grid layer positioned at gate dielectric layer surface；The material of the gate dielectric layer is high K dielectric material；The material of the grid layer is
Metal.
Optionally, formed after pseudo- grid opening, before forming gate structure in the pseudo- grid opening, further included：Removal
Second oxide layer of core space.
Correspondingly, the present invention also provides it is a kind of using the above method formed a kind of semiconductor structure, including:Substrate, institute
Stating substrate includes external zones and core space, has the first fin on the substrate of external zones, has the second fin on the substrate of core space
Portion；Separation layer on the substrate, the surface of the separation layer is less than first fin and the top table of the second fin
Face, and the separation layer covers the partial sidewall surface of first fin and the second fin；Positioned at the side of first fin
Wall and first oxide layer at top；The second oxidation positioned at the described first oxidation layer surface and the second fin side wall and top
Layer.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that：
In the forming method for the semiconductor structure that technical solution of the present invention provides, the first oxygen is formed on the surface of the first fin
After changing layer, the second oxide layer, first oxide layer and the second oxide layer conduct are formed on the surface of first oxide layer
Pseudo- gate dielectric layer in external zones dummy gate structure.Firstly, since external zones operating voltage is larger, therefore the puppet needed for external zones
The thickness of gate oxide is thicker, and the overall thickness of first oxide layer and the second oxide layer disclosure satisfy that external zones oxide coating process
The needs of thickness.Secondly, first oxide layer is formed using oxidation technology, and first oxidated layer thickness compares the first oxygen
Change layer and the second oxide layer overall thickness is relatively thin, therefore formed using oxidation technology during first oxide layer to the first fin
Consumption it is less.Since the process for forming first oxide layer is less to the consumption of the first fin, first fin is avoided
Over-dimension reduce, then be conducive to avoid that electric leakage or short-channel effect occur in the first fin.Therefore, partly led with what is formed
Body structure and morphology is good, and manufactured device performance is stablized.
In the semiconductor structure that technical solution of the present invention provides, positioned at the side wall of first fin and first oxygen at top
Change layer and the second oxide layer in the first oxide layer as the pseudo- gate dielectric layer in the external zones dummy gate structure.Institute
The overall thickness for stating the first oxide layer and the second oxide layer disclosure satisfy that the needs of external zones oxide coating process thickness.The semiconductor
Structural behaviour is stablized.
Description of the drawings
Fig. 1 to Fig. 2 is a kind of structure diagram of each step of the forming method of semiconductor structure；
Fig. 3 to Figure 10 is the structure diagram of each step of one embodiment of forming method of semiconductor structure of the present invention.
Specific embodiment
The forming method of semiconductor structure there are problems, such as：The semiconductor structure poor-performing of formation.
In conjunction with a kind of forming method of semiconductor structure, analyze semiconductor structure performance that the forming method formed compared with
The reason for poor：
Fig. 1 to Fig. 2 is a kind of structure diagram of each step of the forming method of semiconductor structure.
It please refers to Fig.1, substrate 100 is provided, the substrate 100 has external zones 101 and core space 102；In the periphery
The first fin 111 is formed in area 101, the second fin 112 is formed in the core space 102；It is formed on 100 surface of substrate
Separation layer 103, the surface of the separation layer 103 are less than the top surface of 111 and second fin 112 of the first fin, and institute
State the partial sidewall surface that separation layer 103 covers 111 and second fin 112 of the first fin.
It please refers to Fig.2, is formed in the substrate 100, (as shown in Figure 1) side wall of the first fin 111 and top surface
Oxide layer 104.
It is formed after the oxide layer 104, further included：In the side wall of first fin 111 and top surface, Yi Ji
The side wall and top surface of two fins 112 are developed across the dummy gate structure of 111 and second fin 112 of the first fin；Institute
Stating dummy gate structure includes pseudo- gate dielectric layer and the dummy gate layer on pseudo- gate dielectric layer；In separation layer 103, the first fin
111 and second fin 112 surface formed dielectric layer, the surface of the dielectric layer exposes first fin 111 and second
The surface of the dummy gate structure of fin 112；It removes the dummy gate layer in the dummy gate structure and forms pseudo- grid opening；In the puppet
Gate structure is formed in grid opening.
The oxide layer 104 is formed by side wall and top surface of the oxidation technology in first fin 111, as rear
The continuous pseudo- gate dielectric layer formed in 101 dummy gate structure of external zones.However, the operating voltage of external zones 101 is larger, it is necessary to described
The thickness of oxide layer 104 is thicker, therefore, the oxide layer 104 during formation to the consumption of first fin 111 compared with
Greatly.Because forming the 3rd fin 113 by oxidation consumption, short-channel effect easily occurs first fin 111 for the 3rd fin 113
And electric leakage.
To solve the technical problem, the present invention provides a kind of forming method of semiconductor structure, including：Lining is provided
Bottom, the substrate include external zones and core space, and external zones has the first fin, and core space has the second fin；In the lining
Bottom surface forms separation layer, and the surface of the separation layer is less than the top surface of first fin and the second fin, and described
Separation layer covers the partial sidewall surface of first fin and the second fin；Using oxidation technology in the side of first fin
Wall and top surface form the first oxide layer；Second is formed in the described first oxidation layer surface and the second fin side wall and top
Oxide layer.
In the method, after forming the first oxide layer on the surface of the first fin, on the surface of first oxide layer
The second oxide layer is formed, first oxide layer and the second oxide layer are as the pseudo- gate dielectric layer in external zones dummy gate structure.
Firstly, since external zones operating voltage is larger, therefore the thickness of the pseudo- gate oxide needed for external zones is thicker, first oxidation
The overall thickness of layer and the second oxide layer disclosure satisfy that the needs of external zones oxide coating process thickness.Secondly, first oxide layer
It is formed using oxidation technology, and first oxidated layer thickness is relatively thin compared to the first oxide layer and the second oxide layer overall thickness, therefore
It is formed using oxidation technology less to the consumption of the first fin during first oxide layer.Due to forming first oxygen
It is less to the consumption of the first fin to change the process of layer, the over-dimension of first fin is avoided to reduce, then is conducive to avoid the
Electric leakage or short-channel effect occur in one fin.Therefore, with good, the manufactured device of the semiconductor structure pattern formed
It can stablize.
It is understandable for above-mentioned purpose, feature and advantageous effect of the invention is enable to become apparent, below in conjunction with the accompanying drawings to this
The specific embodiment of invention is described in detail.
Fig. 3 to Figure 10 is the structure diagram of each step of one embodiment of forming method of semiconductor structure of the present invention.
It please refers to Fig.3, substrate 200 is provided, the substrate 200 includes external zones 201 and core space 202, the lining of external zones
On bottom 200 there is the first fin 203, there is the second fin 204 on the substrate 200 of core space 202；On 200 surface of substrate
Separation layer 205 is formed, the surface of the separation layer 205 is less than the top surface of 203 and second fin 204 of the first fin,
And the separation layer 205 covers the partial sidewall surface of 203 and second fin 204 of the first fin.
In the present embodiment, the substrate 200 is silicon substrate.In other embodiments, the substrate can also be that germanium serves as a contrast
The Semiconductor substrates such as bottom, silicon-Germanium substrate, silicon-on-insulator substrate or germanium on insulator.
In the present embodiment, the fin formula field effect transistor that the external zones 201 is formed is used to form imput output circuit,
The fin formula field effect transistor that the core space 202 is formed is used to form the core devices of integrated circuit.Therefore, the periphery
The density for the first fin 203 that area 201 is formed is smaller, and the work of fin formula field effect transistor that external zones 201 is formed
Voltage is larger.And the density for the second fin 204 that the core space 202 is formed is larger, and the core space 202 is formed
The operating voltage of fin formula field effect transistor is smaller.
In the present embodiment, the material of first fin 203 and second fin 204 is：Silicon.In other embodiment
In, the material of first fin and second fin can also be germanium, SiGe, III-group Ⅴ element compound, carborundum or
Diamond.
In the present embodiment, the forming step of the substrate 200, the first fin 203 and the second fin 204 includes：It provides just
Beginning substrate；Mask layer is formed in the part surface of the initial substrate；Using the mask layer as mask, the initial lining is etched
Bottom forms substrate 200, the first fin 203 and the second fin 204.
The forming step of the separation layer 205 includes：It is formed on substrate 200, the first fin 203 and the second fin 204
Spacer material layer, the surface of the spacer material layer are higher than or are flush to the top of 203 and second fin 204 of the first fin
Portion；The etching removal part spacer material layer, and expose side wall and the top of part the first fin 203 and the second fin 204
Portion surface forms separation layer 205.
205 formation process of separation layer is chemical vapor deposition method, and the chemical vapor deposition method includes：Fluid
Chemical vapor deposition (FCVD, Flowable Chemical Vapor Deposition) technique, plasma enhanced chemical gas
Phase depositing operation.In the present embodiment, the isolation film formed using the fluid chemistry gas-phase deposition is easy to be packed into first
In isolated groove between fin 203 and between the second fin 204, formed 205 even compact of separation layer can be made,
Isolation performance is good.
The flatening process is CMP process.
The material of the separation layer 205 is silica, silicon nitride, silicon oxynitride, low-K dielectric material, ultralow K dielectric materials
In one or more combinations.The K value scopes of the low-K dielectric material are：K is more than 2.5 and is less than 3.9.The super low-K dielectric material
The K value scopes of material are：K is less than 2.5.
It is follow-up that first oxide layer is formed using side wall and top surface of the oxidation technology in first fin 203.At this
In embodiment, after the separation layer 205 is formed, before the first oxide layer is subsequently formed, in second fin 204
Side wall and top surface form the 3rd oxide layer.
It please refers to Fig.4, after the separation layer 205 is formed, in the side wall of second fin 204 and top surface shape
Into the 3rd oxide layer 206.
The material of 3rd oxide layer 206 includes：Silica；The thickness of 3rd oxide layer 206 is：10 angstroms~30
Angstrom；The forming method of 3rd oxide layer 206 includes：Using atom layer deposition process, in first fin 203 and second
204 side wall of fin and top surface form the 3rd oxide-film；Remove the 3rd oxygen of 203 side wall of the first fin and top surface
Change film, form the 3rd oxide layer 206.
The formation process of 3rd oxide-film is atom layer deposition process.In other embodiment, the shape of the 3rd oxide-film
Can also be chemical vapor deposition method or physical gas-phase deposition into technique.
The reason for three oxide-film for removing 203 side wall of the first fin and top surface, is：The core space
Operating voltage is smaller than the operating voltage of external zones 201, therefore, is formed at 204 side wall of the second fin of core space and top surface
3rd oxide-film is not suitable for 203 side wall of the first fin of external zones and top surface, therefore, after the 3rd oxide-film is formed,
The 3rd oxide-film of removal external zones 201 is needed, so that subsequent technique forms the oxide layer suitable for 203 surface of the first fin.
The step of three oxide-film for removing 203 side wall of the first fin and top surface, includes：In the external zones
201 the 3rd oxidation film surface forms graph layer (not marked in figure), and the graph layer, which has, exposes the external zones 201
The opening of 3rd oxide-film；Using the graph layer as mask, the 3rd oxide-film of etching removal external zones is until expose described
Until first fin 203.
Fig. 5 is refer to, the first oxide layer is formed using side wall and top surface of the oxidation technology in first fin 203
207。
First oxide layer 207 and the second oxide layer being subsequently formed are situated between as the pseudo- grid in external zones dummy gate structure
Matter layer.
The material of first oxide layer 207 is：Silica, the thickness of first oxide layer 207 are：10 angstroms~20
Angstrom.If the thickness of first oxide layer 207 is too thick, it is right during first oxide layer 207 to be formed using oxidation technology
The consumption of first fin 203 is more, and then first fin 203 is made to generate defect, easily leaks electricity；If first oxide layer
203 thickness is too thin, although less to the consumption of the first fin 203 during oxidation technology is formed, described first
The thickness of oxide layer 203 is too thin cannot to meet process requirements.
In the present embodiment, the formation process of first oxide layer 207 is：Moisture-generation process (In Situ in situ
Steam Generation,ISSG).The parameter of the original position moisture-generation process includes：Temperature is：900 degrees Celsius~1100
Degree Celsius, pressure is：The millimetres of mercury of 0.1 millimetres of mercury~100, H2Volume flow be：The standard of 0.2 standard liter/min~20
Liter/min, O2Volume flow be：The standard liter/min of 5 standard liter/mins~100, time is：5 seconds~300 seconds.
The advantage of the moisture-generation process in situ is selected to be：While dimensions of semiconductor devices scaled down,
For operating voltage but without correspondingly scaled down, this allows for the electric field strength increase in relatively thin pseudo- gate dielectric layer so that
Pseudo- gate dielectric layer is easily breakdown and leaks electricity.Using first oxide 207 of the moisture-generation process generation in situ
Uniformity is preferable, and first oxide layer 207 and the second oxide layer for being subsequently formed are as in external zones dummy gate structure
Pseudo- gate dielectric layer, so as to significantly improve the performance of pseudo- gate dielectric layer.
It refer to Fig. 6 and Fig. 7, Fig. 7 is cross-sectional view along AA ' directions of external zones 201 in Fig. 6, Yi Jihe
Cross-sectional view of the heart district 202 along BB ' directions, in first oxide layer 207 and 204 side wall of the second fin and
Top forms surface and forms the second oxide layer 208.
The material of second oxide layer 208 is：Silica.
The formation process of second oxide layer 208 is atom layer deposition process.In other embodiment, the second oxide layer
Formation process can also be chemical vapor deposition method or physical gas-phase deposition.
The thickness of second oxide layer 208 is：5 angstroms~20 angstroms.
Fig. 7 is refer to, second oxide layer 208 is used as with first oxide layer 207 and is subsequently formed external zones puppet grid
Pseudo- gate dielectric layer 209 in the structure of pole.Second oxide layer 208 is used as with the 3rd oxide layer 206 and is subsequently formed core
Pseudo- gate dielectric layer 210 in area's dummy gate structure.
The sum of thickness of second oxide layer 208 and first oxide layer 207 is 25 angstroms~50 angstroms.
Pseudo- gate dielectric layer in the dummy gate structure that the external zones is formed is using the second oxide layer 208 and described the
The double-layer structure of one oxide layer 207, the overall thickness of 208 and first oxide layer 207 of the second oxide layer disclosure satisfy that external zones
The requirement of oxide coating process thickness.Also, the first oxide layer 207 is formed using oxidation technology so that first oxide layer 207
It is preferable with the contact interface of the first fin 203.In addition, the thickness of the first oxide layer 207 is compared to second oxide layer 208 and the
The overall thickness of one oxide layer 207 is relatively thin, therefore less to the consumption of the first fin 203 during oxidation technology is formed, from
And make that the semiconductor topography to be formed is good, performance is stablized.
It should be noted that Fig. 8 to Figure 10 shown in follow-up is to carry out manufacturing process based on cross-section structure shown in Fig. 7
Schematic diagram.
Fig. 8 is refer to, in 205 surface of separation layer, the side wall of the first fin 203 and top surface shape described in external zones 201
Into the external zones dummy gate structure 212 for being across first fin 203；In 205 surface of separation layer, described in core space 202
The side wall and top surface of two fins 204 are developed across in the core space dummy gate structure 214 of second fin 204.
The formation process of the external zones dummy gate structure 212 includes：In 205 surface of separation layer, the first fin 203
Side wall and top surface form external zones puppet gate dielectric layer 209；Periphery is formed on 209 surface of external zones puppet gate dielectric layer
Area's dummy gate layer 211；External zones puppet gate dielectric layer 209 and external zones dummy gate layer 211 described in etched portions, until exposure periphery
205 surface of separation layer in area, the side wall and top surface of the first fin 203, are developed across in 203 dummy gate structure of the first fin
212。
The external zones dummy gate structure 212 includes：External zones puppet gate dielectric layer 209 and positioned at the pseudo- gate medium
External zones dummy gate layer 211 on layer 209.
The external zones puppet gate dielectric layer 209 includes first oxide layer 207 and second oxide layer 208.
It is developed across in 205 surface of separation layer, the side wall of the second fin 204 and top surface described in core space 202 in institute
State the core space dummy gate structure 214 of the second fin 204.
The formation process of the core space dummy gate structure 214 includes：In 205 surface of separation layer described in core space, second
The side wall and top surface of fin 204 form core space puppet gate dielectric layer 210；On 210 surface of core space puppet gate dielectric layer
Form core space dummy gate layer 213；Core space puppet gate dielectric layer 210 and core space dummy gate layer 213 described in etched portions, until
205 surface of separation layer of exposure core space, the side wall and top surface of the second fin 204 are developed across pseudo- in the second fin 204
Gate structure 214.
The core space dummy gate structure 214 includes：Core space puppet gate dielectric layer 210 and positioned at the pseudo- gate medium
The core space dummy gate layer 213 on 210 surface of layer.
The core space puppet gate dielectric layer 210 includes second oxide layer 208 and the 3rd oxide layer 206.
The material of the dummy gate layer 211 of the external zones and the core space dummy gate layer 213 is polysilicon, due to described
Polysilicon is easily formed and is easily removed, therefore the external zones dummy gate layer 211 and the shape of core space dummy gate layer 213 formed
Looks are good, and are not likely to produce excessive by-product after removal external zones dummy gate layer 211 and core space dummy gate layer 213.
Please continue to refer to Fig. 8, external zones source is formed in 203 both sides of the first fin of 212 both sides of external zones dummy gate structure
Drain region 215；Core space source-drain area 216 is formed in 204 both sides of the second fin of 214 both sides of core space dummy gate structure.
The forming step of the external zones source-drain area 215 and core space source-drain area 216 includes：Etched portions external zones puppet grid
Pole structure 212, the first fin 203 and core space dummy gate structure 214, the second fin 204, in the first fin 203 and second
204 both sides of fin form opening；Source-drain area material layer, the source are formed in the opening using selective epitaxial depositing operation
The material of drain region material layer is silicon, SiGe or carborundum；Using doping process in situ in the source-drain area material layer doped p-type
Ion or N-type ion form external zones source-drain area 215 in external zones 201, and core space source-drain area is formed in core space 202
216。
Refer to Fig. 9, after the external zones source-drain area 215 and core space source-drain area 216 is formed, separation layer 205,
The surface of first fin 203 and the second fin 204 forms dielectric layer 217, and the surface of the dielectric layer 217 exposes the periphery
The surface of area's dummy gate structure 212 and the dummy gate structure of the core space 214.
The dielectric layer 217 is used to isolate adjacent external zones dummy gate structure 212 and the core space dummy gate structure
214.The material of the dielectric layer 217 is silica, in silicon nitride, silicon oxynitride, low-K dielectric material, ultralow K dielectric materials
One or more combination.The K value scopes of the low-K dielectric material are：K is more than 2.5 and is less than 3.9.The ultralow K dielectric materials
K value scopes are：K is less than 2.5.
The formation process of the dielectric layer 217 includes：The side wall of separation layer 205, the first fin 203 and the second fin 204
Medium is formed with 214 top surface of dummy gate structure on surface, the external zones dummy gate structure 212 and the core space
Film；The external zones deielectric-coating is planarized until exposing the pseudo- grid of the external zones dummy gate structure 212 and the core space
Until 214 top surface of pole structure, the dielectric layer 217 is formed.In the present embodiment, the flatening process is thrown for chemical machinery
Light technique.
0 is please referred to Fig.1, removes the external zones dummy gate layer 211, external zones is formed in the dielectric layer 217 of external zones
Opening 218, removal core space dummy gate layer 213, forms opening in the dielectric layer 217 of the core space, and the external zones is opened
218 bottoms of mouth and open bottom expose 208 top surface of the second oxide layer.
In the present embodiment, the second oxide layer 208 for removing 218 bottoms of the opening is further included, forms core space opening
219。
The technique of the external zones dummy gate layer 211 and the core space dummy gate layer 213 is removed as dry etching, wet method
The combination of etching or dry etching and wet etching.In the present embodiment, the external zones puppet is removed using wet-etching technology
Grid layer 211 and the core space dummy gate layer 213, the by-product that the wet-etching technology generates is less, and the wet method is carved
The etching liquid of erosion is salpeter solution or sodium nitrite solution.
After forming the external zones opening 218 and the core space opening 219, further include：In the external zones opening 218
With the gate structure being developed across in the core space opening 219 on first fin 203 and second fin 204.
To sum up, in the present embodiment, in order to reduce the consumption during thermal oxide is formed to first fin,
Technical solution of the present invention is proposed in the first fin.Surface formed the first oxide layer.Afterwards, in first oxide layer.Table
Face forms the second oxide layer., first oxide layer.With the second oxide layer.It is situated between as the pseudo- grid in external zones dummy gate structure
Matter layer.Firstly, since external zones.Operating voltage is larger, therefore external zones.The thickness of required pseudo- gate oxide is thicker, described
First oxide layer.With the second oxide layer.Overall thickness disclosure satisfy that the needs of external zones oxide coating process thickness.Secondly, it is described
First oxide layer.It is formed using oxidation technology, and first oxide layer.Thickness compares the first oxide layer.With the second oxide layer.
Overall thickness is relatively thin, therefore forms first oxide layer using oxidation technology.During to the first fin.Consumption it is less.By
In formation first oxide layer.Process to the first fin.Consumption it is less, avoid first fin.Over-dimension
Reduce, be then conducive to avoid the first fin.It is interior that electric leakage or short-channel effect occurs.Therefore, to make the semiconductor structure to be formed
Pattern is good, and manufactured device performance is stablized.
Correspondingly, the embodiment of the present invention also provides a kind of semiconductor structure formed using the above method, figure refer to
6, including：
Substrate 200, the substrate 200 include external zones 201 and core space 202, have on the substrate 200 of external zones 201
First fin 203 has the second fin 204 on the substrate 200 of core space 202；
Separation layer 205 on the substrate 200, the surface of the separation layer 205 are less than 203 He of the first fin
The top surface of second fin 204, and the separation layer 205 covers the part side of 203 and second fin 204 of the first fin
Wall surface；
Positioned at the side wall of first fin 203 and first oxide layer 207 at top；
The second oxide layer 208 positioned at 207 surface of the first oxide layer and 204 side wall of the second fin and top.
To sum up, in the present embodiment, positioned at the side wall of first fin 203 and first oxide layer 207 at top and
The second oxide layer 208 in the first oxide layer 207 is as the pseudo- gate dielectric layer in 201 dummy gate structure of external zones.
The overall thickness of first oxide layer, 207 and second oxide layer 208 disclosure satisfy that the need of 201 oxide coating process thickness of external zones
It will.The semiconductor structure performance is stablized.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the scope of restriction.
Claims (17)
1. a kind of forming method of semiconductor structure, which is characterized in that including：
Substrate is provided, the substrate includes external zones and core space, has the first fin, the lining of core space on the substrate of external zones
There is the second fin on bottom；
Separation layer is formed in the substrate surface, the surface of the separation layer is less than the top of first fin and the second fin
Surface, and the separation layer covers the partial sidewall surface of first fin and the second fin；
First oxide layer is formed using side wall and top surface of the oxidation technology in first fin；
The second oxide layer is formed in the described first oxidation layer surface and the second fin side wall and top.
2. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material of first oxide layer
For：Silica.
3. the forming method of semiconductor structure as described in claim 1, which is characterized in that the thickness of first oxide layer
For：10 angstroms~20 angstroms.
4. the forming method of semiconductor structure as described in claim 1, which is characterized in that the formation work of first oxide layer
Skill includes：Moisture-generation process in situ；The original position moisture-generation process parameter includes：Temperature is：900 degrees Celsius~1100 take the photograph
Family name's degree, pressure are：The millimetres of mercury of 0.1 millimetres of mercury~100, H2Volume flow be：The standard liter of 0.2 standard liter/min~20/
Minute, O2Volume flow be：The standard liter/min of 5 standard liter/mins~100, time is：5 seconds~300 seconds.
5. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material of second oxide layer
For：Silica.
6. the forming method of semiconductor structure as described in claim 1, which is characterized in that second oxidated layer thickness is：5
Angstrom~20 angstroms.
7. the forming method of semiconductor structure as described in claim 1, which is characterized in that form the work of second oxide layer
Skill includes：Atom layer deposition process.
8. the forming method of semiconductor structure as described in claim 1, which is characterized in that further include：Forming the isolation
After layer, before the first oxide layer is formed, the 3rd oxide layer is formed in the side wall and top surface of second fin.
9. the forming method of semiconductor structure as claimed in claim 8, which is characterized in that form the step of the 3rd oxide layer
Suddenly include：The 3rd oxide-film is formed in first fin and second fin portion surface；Etching removes the first fin table
3rd oxide-film in face forms the 3rd oxide layer.
10. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material of the 3rd oxide layer
For：Silica.
11. the forming method of semiconductor structure as described in claim 1, which is characterized in that the thickness of the 3rd oxide layer
For：10 angstroms~30 angstroms.
12. the forming method of semiconductor structure as described in claim 1, which is characterized in that the forming step of the separation layer
Including：Spacer material layer is formed on substrate, the first fin and the second fin, the surface of the spacer material layer is higher than or flushes
In the top of first fin and the second fin；The etching removal part spacer material layer, and expose the first fin of part
Portion and the side wall and top surface of the second fin form separation layer.
13. the forming method of semiconductor structure as described in claim 1, which is characterized in that first fin and the second fin
The forming step in portion includes：Initial substrate is provided；Mask layer is formed in the part surface of the initial substrate；With the mask layer
For mask, the initial substrate is etched, forms substrate, the first fin and the second fin.
14. the forming method of semiconductor structure as described in claim 1, which is characterized in that further include：Forming described second
After oxide layer, horizontal stroke is formed in the side wall of first fin and the side wall and top surface of top surface and the second fin
Across the dummy gate structure of first fin and the second fin；Dummy gate structure includes pseudo- gate dielectric layer and is situated between positioned at pseudo- grid
Dummy gate layer on matter layer；Dielectric layer, the surface of the dielectric layer are formed on the surface of separation layer, the first fin and the second fin
Expose the surface of the dummy gate structure of first fin and the second fin；The dummy gate layer is removed, in the dielectric layer
It is interior to form pseudo- grid opening；Gate structure is formed in the pseudo- grid opening.
15. the forming method of semiconductor structure as claimed in claim 14, which is characterized in that the dummy gate structure includes：
Positioned at the gate dielectric layer and the grid layer positioned at gate dielectric layer surface of the pseudo- grid opening sidewalls and lower surface；The grid
The material of dielectric layer is high K dielectric material；The material of the grid layer is metal.
16. the forming method of semiconductor structure as claimed in claim 14, which is characterized in that it is formed after pseudo- grid opening,
It is formed before gate structure, further included in the puppet grid opening：Remove the second oxide layer of core space.
It is 17. a kind of using the semiconductor structure formed such as any one of claim 1 to 16 method, which is characterized in that
Substrate, the substrate include external zones and core space, have the first fin on the substrate of external zones, on the substrate of core space
With the second fin；
Separation layer on the substrate, the surface of the separation layer is less than first fin and the top table of the second fin
Face, and the separation layer covers the partial sidewall surface of first fin and the second fin；
Positioned at the side wall of first fin and first oxide layer at top；
Positioned at the described first oxidation layer surface and second oxide layer at the second fin side wall and top.
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