US20080020544A1 - Method for Forming Wall Oxide Layer and Isolation Layer in Flash Memory Device - Google Patents
Method for Forming Wall Oxide Layer and Isolation Layer in Flash Memory Device Download PDFInfo
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- US20080020544A1 US20080020544A1 US11/833,056 US83305607A US2008020544A1 US 20080020544 A1 US20080020544 A1 US 20080020544A1 US 83305607 A US83305607 A US 83305607A US 2008020544 A1 US2008020544 A1 US 2008020544A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76221—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO with a plurality of successive local oxidation steps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Definitions
- Methods for forming wall oxide films and isolation films for flash memory devices are disclosed. More specifically, a disclosed method for forming wall oxide films prevents a “dislocation” phenomenon where a sidewall within the trench is broken due to thermal stress caused by an oxidization process performed after the trench is formed. A method of forming an isolation film in the flash memory device using the same is also disclosed.
- an isolation film is formed by means of a shallow trench isolation (STI) process in order to electrically isolate neighboring elements (for example, cells and transistors).
- a STI process is performed by forming a pad oxide film and a pad nitride film on a substrate, performing a trench etch process to form trenches in the substrate, and then depositing an insulating film so that the trenches are buried or filled, thus forming an isolation film.
- the STI process includes a wall oxidization process, which is performed on the sidewall within the trenches in order to compensate for damage to the sidewalls of the trenches, which are damaged by the trench etch process or to control the area of the active region, after the trench etch process is performed.
- Wall oxide films are formed on the sidewalls of the trenches by this wall oxidization process.
- the wall oxidization process is carried out in a furnace, a high thermal stress is caused, and a dislocation phenomenon in which the silicon sidewall portion is broken at the top/bottom regions of the trenches is generated.
- This dislocation phenomenon generates a path along which the leakage current flows, and thus causes device characteristics to degrade.
- the dislocation phenomenon causes defects to occur in an active region as well as the source and drain regions.
- a method for forming wall oxide films for a flash memory device in which a dislocation phenomenon is avoided where sidewalls within trenches are broken due to an oxidization process performed after formation of the trenches. The resulting device characteristics are therefore improved.
- a method of forming an isolation film in the flash memory device using the same is also disclosed.
- One disclosed method for forming wall oxide films in a flash memory device comprises providing a semiconductor substrate in which trenches are formed, and performing an oxidization process in a gas atmosphere of H 2 and O 2 in an ISSG oxidization mode, thus forming wall oxide films on sidewalls of the trenches.
- Another disclosed method for forming an isolation film in a flash memory device comprises providing a semiconductor substrate in which a pad oxide film is formed, depositing a pad nitride film on the pad oxide film, etching the pad nitride film and the pad oxide film, and at the same time, recessing some of the top of the semiconductor substrate to form first trenches, forming spacers on the sidewalls of the first trenches, performing a first oxidization process in a ISSG oxidization mode in a gas atmosphere of H 2 and O 2 , thus oxidizing the top of the semiconductor substrate which is exposed through the spacers, etching the semiconductor substrate deeper than the first trenches to form second trenches, performing a second oxidization process in a ISSG oxidization mode in a gas atmosphere of H 2 and O 2 , thereby forming wall oxide films on the sidewalls of the second trenches, and forming an isolation film to bury or fill the second trenches.
- FIGS. 1 to 10 are cross-sectional views for explaining a disclosed method for forming wall oxide films of a flash memory device and a method for forming an isolation film;
- FIG. 11 is a TEM (Transmission Electron Microscope) showing the wall oxide films formed by the method illustrated in FIGS. 1-10 ;
- FIGS. 12 and 13 are TEM photographs showing wall oxide films formed by a furnace process.
- FIGS. 1 to 10 are cross-sectional views for explaining a disclosed method for forming a wall oxide films of a flash memory device and a method for forming an isolation film according to a preferred embodiment.
- a NAND flash memory device will be described as an example.
- “cell” indicates a cell region in which a memory cell is formed
- “HV” indicates a high voltage region in which a high voltage transistor for driving the memory cell is formed
- “LV” indicates a low voltage region in which a low voltage transistor is formed.
- the pre-treatment cleaning process can include cleaning the semiconductor substrate 10 using diluted HF (DHF) (for example, HF solution in which H 2 0 is diluted in the ratio of 50:1) and then cleaning it using a solution in which SC-1 NH 4 OH/H 2 O 2 /H 2 O solution is mixed in a given ratio, or cleaning the semiconductor substrate 10 using BOE (Buffer Oxide Etchant) (for example, a mixing solution of HF and NH 4 F in which H 2 O is diluted in the ratio of 100:1 or 300:1 [the ratio of HF to NH 4 F is 1:4 to 1:7]) and then cleaning it using SC-1.
- DHF diluted HF
- BOE Buffer Oxide Etchant
- a screen oxide film (not shown) is formed on the semiconductor substrate 10 .
- the screen oxide film serves to prevent the surface of the semiconductor substrate 10 from being damaged in well during the threshold voltage ion implant processes, which are performed subsequently.
- the well can be composed of a Triple N (TN)-well) and a P-well.
- the TN-well is formed by the ion implant process using phosphorus (P) and the P-well is formed by the ion implant process using boron (B).
- a threshold voltage ion implant process is performed on the semiconductor substrate 10 .
- an oxide film 11 is then formed on the semiconductor substrate 10 .
- the oxide film 11 is formed with a greater thickness in the high voltage region HV than in the cell region Cell and the low voltage region LV.
- a wet oxidization process is first performed to form a thin oxide film on the entire surface including the cell region Cell, the low voltage region LV and the high voltage region HV.
- a wet oxidization process is then performed again using a mask through which the high voltage region HV is opened, thus thickly forming the oxide film 11 in the high voltage region HV.
- This oxide film 11 can be formed by performing a wet oxidization process at a temperature ranging from 750° C. to 800° C. and then performing an annealing process using N 2 at a temperature ranging from 900° C. to 910° C.
- a cleaning process can be performed at least once using DHF and SC-1 while the above process steps are performed.
- the oxide film 11 formed in the cell region Cell is called a ‘pad oxide film 11 a ’
- the oxide film 11 formed in the low voltage region LV is called a ‘low voltage gate oxide film 11 b ’
- the oxide film 11 formed in the high voltage region HV is called a ‘high voltage gate oxide film 11 c’.
- a pad nitride film 12 is deposited on the entire surface including the pad oxide film 11 a , the low voltage gate oxide film 11 b and the high voltage gate oxide film 11 c .
- the pad nitride film 12 can be deposited by low-pressure CVD (LPCVD). In this time, the pad nitride film 12 is deposited with a thickness in the range of 500 ⁇ to 600 ⁇ preferably about 550 ⁇ .
- a hard mask is then deposited on the pad nitride film 12 in order to perform a subsequent trench etch process.
- the hard mask is formed to have the stack structure of a DCS-HTO (DiChloroSilane (SiH 2 Cl 2 )-high temperature oxide) film 13 and a SiON film 14 .
- the DCS-HTO film 13 serves to prevent the pad nitride film 12 from being damaged, and is deposited 250 to 350 ⁇ , preferably about 300 ⁇ .
- the SiON film 14 is deposited with a thickness in the range of 550 to 650 ⁇ , preferably about 600 ⁇ .
- a polishing process is performed in a CMP mode in order to polish the entire surface including the hard mask while reducing the step between the cell region Cell and the high voltage region HV.
- the polishing process can be performed in a blanket or etch-back mode, if needed.
- a photoresist is coated on the entire surface including the hard mask.
- An exposure process and a development process using a photo mask are then sequentially performed to form a photoresist pattern (not shown).
- an etch process using the photoresist pattern as an etch mask is performed to pattern the hard mask.
- the photoresist pattern is then stripped though a strip process.
- etch process using the patterned hard mask as an etch mask is then performed to etch the pad nitride film 12 and the oxide film 11 .
- the etch process is preferably performed so that some of the top of the semiconductor substrate 10 is recessed.
- First trenches 15 which are formed by the recessed some of the semiconductor substrate 10 , are formed by the etch process.
- an insulating film 16 for spacers is deposited along the step on the entire surface in which the first trenches 15 are formed.
- the insulating film 16 for spacers can be formed using a middle temperature oxide (MTO) film.
- MTO middle temperature oxide
- the insulating film 16 for the spacers can be formed by using any one of TEOS (Tetra Ethyle Ortho Silicate), BPSG (Boron Phosphorus Silicate Glass), SOG (Spin On Glass) and USG (Un-doped Silicate Glass).
- a blanket etch process is performed anisotropically to form spacers 16 a on the sidewalls of the first trenches 15 .
- the blanket etch process can be performed in a blanket mode.
- the spacers 16 a are formed on the sidewalls of the hard mask, the pad nitride film 12 , the oxide film 11 and some of the top of the semiconductor substrate 10 through this blanket etch process.
- an in-situ steam generation (ISSG) oxidization process is performed on the semiconductor substrate 10 that is exposed between the spacers 16 a .
- the ISSG oxidization process is performed with a gas atmosphere of H 2 and O 2 .
- the reason why the ISSG oxidization process is performed is for making rounded a top edge portion of each of second trenches (see “ 17 ” in FIG. 8 ), which are formed in a subsequent trench etch process.
- a trench etch process is performed to etch the semiconductor substrate 10 that is exposed, thus forming the second trenches 17 that are deeper than the first trenches 15 .
- a plurality of the second trenches 17 are formed in the cell region Cell, the low voltage region LV and the high voltage region HV, respectively.
- the second trenches 17 is preferably formed in a depth which can provide an isolation property so that the memory cells and/or the transistors can be electrically isolated.
- the top edge portions “A” of the second trenches 17 which are coupled to the bottoms of the spacers 16 a , have a rounded shape by means of the ISSG oxidization process performed in FIG. 7 .
- an ISSG oxidization process is performed on the first trenches 15 and the second trenches 17 to form the wall oxide films 18 on the sidewalls of the second trenches 17 .
- the wall oxide films 18 are formed with a thickness of about 15 to 30 ⁇ .
- the ISSG oxidization process is performed at a temperature ranging 850° C. to 1000° C. and a pressure ranging from 1 to 10 torr in the gas atmosphere of H 2 and O 2 .
- the gas atmosphere that includes H 2 and O 2 is set to be an O 2 -rich gas atmosphere. That is, the amount of O 2 is higher than that of H 2 .
- the mixing ratio of O 2 can be set to 33% to 60%, and the mixing ratio of H 2 can be se to 0.5% to 33%. Higher amounts of O 2 are used because O 2 has a great influence upon the oxidation rate. If the ISSG oxidization process is performed at in the gas atmosphere of H 2 and O 2 , it can be expressed into the following chemical equation A; H 2 +O 2 ⁇ H 2 O+ 0 +OH (A)
- Equation (A) the O and OH radicals generated by reaction of H 2 and O 2 controls the oxidation rate.
- the ISSG oxidization process performed to form the wall oxide films 18 can reduce a crystal orientation effect compared to a typical furnace process.
- a profile of the wall oxide films 18 at the top edge portions of the second trenches 17 will be described in the case where the wall oxide films 18 are formed by a thermal process (using a furnace apparatus) and the case where the wall oxide films 18 are formed by the ISSG oxidization method as in a preferred embodiment.
- FIG. 11 shows a wall oxide film B formed by the ISSG process, which is performed at a temperature of about 1050° C., according to a preferred embodiment.
- FIG. 12 shows a wall oxide film C formed by a dry furnace process, which is performed at a temperature of about 1100° C. in a gas atmosphere of O 2 using a furnace apparatus.
- FIG. 13 shows a wall oxide film D formed by a wet furnace process, which is performed at a temperature of about 950° C. using a furnace.
- the wall oxide film B formed by the ISSG oxidization process according to a preferred embodiment has a good profile characteristic at the top edge of the trench compared to the wall oxide films C and D formed using the furnace apparatus.
- the ISSG oxidization process according to a preferred embodiment can be performed at a lower temperature than that performed in the furnace. It is thus possible to reduce thermal stress.
- the ISSG process for forming the wall oxide films 18 can be performed after the spacers 16 a are removed using a cleaning process using DHF (or BOE) and SC-1, if necessary.
- an insulating film 19 for an isolation film is formed on the entire surface including the wall oxide films 18 .
- the insulating film 19 is formed using a high density plasma (HDP) oxide film.
- the insulating film 19 is preferably gap-filled so that voids are not generated in the first and second trenches 15 and 17 .
- the insulating film 19 can be deposited with a thickness of about 4000 ⁇ to 10000 ⁇ .
- a polishing process is then performed to polish the entire top surface of the insulating film 19 .
- the polishing process is a CMP process, but it can be performed so that the hard mask is recessed to a given thickness or the hard mask is completely removed to a point where some of the pad nitride film 12 is recessed.
- a cleaning process is applied to the polished entire surface.
- the cleaning process can be performed using DHF and SC-1 so as to compensate portions damaged in the polishing process or remove unnecessary materials, etc. which exist on the entire surface.
- an etch process using phosphoric acid (H 3 PO 4 ) is performed to completely remove the hard mask and/or the pad nitride film 12 which remain after the polishing process.
- the etch process is preferably performed using the oxide film 11 as an etch stopper so that the semiconductor substrate 10 is not damaged.
- the isolation films are formed in the cell region Cell, the low voltage region LV and the high voltage region HV.
- an ISSG oxidization process is performed to form wall oxide films on sidewalls of the trenches. It prohibits facets from being formed at top and bottom edge portions of the trenches. Thus, the top edges of the trenches are rounded. Furthermore, the ISSG oxidization process is performed at low temperature for a relatively short time. Therefore, stress due to an oxidization process for a long time is reduced and a dislocation phenomenon is thus prevented from occurring.
Abstract
Methods for forming wall oxide films in flash memory devices and methods for forming isolation films. After trenches are formed in the substrate, an ISSG (In-Situ Steam Generation) oxidization process is performed to form wall oxide films on sidewalls of the trenches. This process prohibits formation of facets at the top and bottom edge portions of the trenches. Thus, the top edges of the trenches are rounded. Furthermore, the ISSG oxidization process is performed at a low temperature for a relatively short time. Therefore, thermal stress due to carrying out an oxidization process for a long time is reduced and a dislocation phenomenon is thus prevented from occurring.
Description
- This is a divisional of U.S. application Ser. No. 11/016,436 filed Dec. 17, 2004, the entire disclosure of which is incorporated by reference.
- 1. Technical Field
- Methods for forming wall oxide films and isolation films for flash memory devices are disclosed. More specifically, a disclosed method for forming wall oxide films prevents a “dislocation” phenomenon where a sidewall within the trench is broken due to thermal stress caused by an oxidization process performed after the trench is formed. A method of forming an isolation film in the flash memory device using the same is also disclosed.
- 2. Description of the Related Art
- Recently, there is an increased demand for flash memory devices which can be electrically programmed and erased and which do not need a refresh function that data is rewritten in a given period. “Program” refers to an operation for writing data into memory cells, and erase refers to an operation for erasing data written into memory cells. Furthermore, research into higher-integration technology of memory devices has been actively conducted in order to develop memory devices with large capacities.
- In a flash memory device, an isolation film is formed by means of a shallow trench isolation (STI) process in order to electrically isolate neighboring elements (for example, cells and transistors). Typically, a STI process is performed by forming a pad oxide film and a pad nitride film on a substrate, performing a trench etch process to form trenches in the substrate, and then depositing an insulating film so that the trenches are buried or filled, thus forming an isolation film.
- The STI process includes a wall oxidization process, which is performed on the sidewall within the trenches in order to compensate for damage to the sidewalls of the trenches, which are damaged by the trench etch process or to control the area of the active region, after the trench etch process is performed. Wall oxide films are formed on the sidewalls of the trenches by this wall oxidization process.
- Generally, the wall oxidization process is carried out in a furnace, a high thermal stress is caused, and a dislocation phenomenon in which the silicon sidewall portion is broken at the top/bottom regions of the trenches is generated. This dislocation phenomenon generates a path along which the leakage current flows, and thus causes device characteristics to degrade. Furthermore, in an ion implant process for forming subsequent source and drain regions, the dislocation phenomenon causes defects to occur in an active region as well as the source and drain regions.
- Accordingly, in view of the above problems, a method for forming wall oxide films for a flash memory device is disclosed in which a dislocation phenomenon is avoided where sidewalls within trenches are broken due to an oxidization process performed after formation of the trenches. The resulting device characteristics are therefore improved. A method of forming an isolation film in the flash memory device using the same is also disclosed.
- One disclosed method for forming wall oxide films in a flash memory device comprises providing a semiconductor substrate in which trenches are formed, and performing an oxidization process in a gas atmosphere of H2 and O2 in an ISSG oxidization mode, thus forming wall oxide films on sidewalls of the trenches.
- Another disclosed method for forming an isolation film in a flash memory device, comprises providing a semiconductor substrate in which a pad oxide film is formed, depositing a pad nitride film on the pad oxide film, etching the pad nitride film and the pad oxide film, and at the same time, recessing some of the top of the semiconductor substrate to form first trenches, forming spacers on the sidewalls of the first trenches, performing a first oxidization process in a ISSG oxidization mode in a gas atmosphere of H2 and O2, thus oxidizing the top of the semiconductor substrate which is exposed through the spacers, etching the semiconductor substrate deeper than the first trenches to form second trenches, performing a second oxidization process in a ISSG oxidization mode in a gas atmosphere of H2 and O2, thereby forming wall oxide films on the sidewalls of the second trenches, and forming an isolation film to bury or fill the second trenches.
- FIGS. 1 to 10 are cross-sectional views for explaining a disclosed method for forming wall oxide films of a flash memory device and a method for forming an isolation film;
-
FIG. 11 is a TEM (Transmission Electron Microscope) showing the wall oxide films formed by the method illustrated inFIGS. 1-10 ; and -
FIGS. 12 and 13 are TEM photographs showing wall oxide films formed by a furnace process. - FIGS. 1 to 10 are cross-sectional views for explaining a disclosed method for forming a wall oxide films of a flash memory device and a method for forming an isolation film according to a preferred embodiment. A NAND flash memory device will be described as an example. Meanwhile, in FIGS. 1 to 10, “cell” indicates a cell region in which a memory cell is formed, “HV” indicates a high voltage region in which a high voltage transistor for driving the memory cell is formed, and “LV” indicates a low voltage region in which a low voltage transistor is formed.
- Referring to
FIG. 1 , asemiconductor substrate 10 on which a pre-treatment cleaning process are been performed is provided. The pre-treatment cleaning process can include cleaning thesemiconductor substrate 10 using diluted HF (DHF) (for example, HF solution in whichH 20 is diluted in the ratio of 50:1) and then cleaning it using a solution in which SC-1 NH4OH/H2O2/H2O solution is mixed in a given ratio, or cleaning thesemiconductor substrate 10 using BOE (Buffer Oxide Etchant) (for example, a mixing solution of HF and NH4F in which H2O is diluted in the ratio of 100:1 or 300:1 [the ratio of HF to NH4F is 1:4 to 1:7]) and then cleaning it using SC-1. - Thereafter, a screen oxide film (not shown) is formed on the
semiconductor substrate 10. The screen oxide film serves to prevent the surface of thesemiconductor substrate 10 from being damaged in well during the threshold voltage ion implant processes, which are performed subsequently. - An ion implant process is then performed within the
semiconductor substrate 10, thus forming a well (not shown). If thesemiconductor substrate 10 is a P-type substrate, the well can be composed of a Triple N (TN)-well) and a P-well. The TN-well is formed by the ion implant process using phosphorus (P) and the P-well is formed by the ion implant process using boron (B). - In order to form a channel, a threshold voltage ion implant process is performed on the
semiconductor substrate 10. Then, anoxide film 11 is then formed on thesemiconductor substrate 10. In this time, theoxide film 11 is formed with a greater thickness in the high voltage region HV than in the cell region Cell and the low voltage region LV. - For example, a wet oxidization process is first performed to form a thin oxide film on the entire surface including the cell region Cell, the low voltage region LV and the high voltage region HV. A wet oxidization process is then performed again using a mask through which the high voltage region HV is opened, thus thickly forming the
oxide film 11 in the high voltage region HV. Thisoxide film 11 can be formed by performing a wet oxidization process at a temperature ranging from 750° C. to 800° C. and then performing an annealing process using N2 at a temperature ranging from 900° C. to 910° C. - Meanwhile, although not described in the above description, a cleaning process can be performed at least once using DHF and SC-1 while the above process steps are performed.
- For convenience, hereinafter, the
oxide film 11 formed in the cell region Cell is called a ‘pad oxide film 11 a’, theoxide film 11 formed in the low voltage region LV is called a ‘low voltage gate oxide film 11 b’, and theoxide film 11 formed in the high voltage region HV is called a ‘high voltage gate oxide film 11 c’. - Referring to
FIG. 2 , apad nitride film 12 is deposited on the entire surface including the pad oxide film 11 a, the low voltage gate oxide film 11 b and the high voltage gate oxide film 11 c. Thepad nitride film 12 can be deposited by low-pressure CVD (LPCVD). In this time, thepad nitride film 12 is deposited with a thickness in the range of 500 Å to 600 Å preferably about 550 Å. - A hard mask is then deposited on the
pad nitride film 12 in order to perform a subsequent trench etch process. In this time, the hard mask is formed to have the stack structure of a DCS-HTO (DiChloroSilane (SiH2Cl2)-high temperature oxide)film 13 and a SiONfilm 14. The DCS-HTOfilm 13 serves to prevent thepad nitride film 12 from being damaged, and is deposited 250 to 350 Å, preferably about 300 Å. Furthermore, the SiONfilm 14 is deposited with a thickness in the range of 550 to 650 Å, preferably about 600 Å. - Referring to
FIG. 3 , a polishing process is performed in a CMP mode in order to polish the entire surface including the hard mask while reducing the step between the cell region Cell and the high voltage region HV. At this time, the polishing process can be performed in a blanket or etch-back mode, if needed. - Referring to
FIG. 4 , a photoresist is coated on the entire surface including the hard mask. An exposure process and a development process using a photo mask are then sequentially performed to form a photoresist pattern (not shown). - Thereafter, an etch process using the photoresist pattern as an etch mask is performed to pattern the hard mask. The photoresist pattern is then stripped though a strip process.
- An etch process using the patterned hard mask as an etch mask is then performed to etch the
pad nitride film 12 and theoxide film 11. At this time, the etch process is preferably performed so that some of the top of thesemiconductor substrate 10 is recessed.First trenches 15, which are formed by the recessed some of thesemiconductor substrate 10, are formed by the etch process. - Referring to
FIG. 5 , an insulatingfilm 16 for spacers is deposited along the step on the entire surface in which thefirst trenches 15 are formed. At this time, the insulatingfilm 16 for spacers can be formed using a middle temperature oxide (MTO) film. Also, the insulatingfilm 16 for the spacers can be formed by using any one of TEOS (Tetra Ethyle Ortho Silicate), BPSG (Boron Phosphorus Silicate Glass), SOG (Spin On Glass) and USG (Un-doped Silicate Glass). - Referring to
FIG. 6 , a blanket etch process is performed anisotropically to formspacers 16 a on the sidewalls of thefirst trenches 15. At this time, the blanket etch process can be performed in a blanket mode. Thespacers 16 a are formed on the sidewalls of the hard mask, thepad nitride film 12, theoxide film 11 and some of the top of thesemiconductor substrate 10 through this blanket etch process. - Referring to
FIG. 7 , an in-situ steam generation (ISSG) oxidization process is performed on thesemiconductor substrate 10 that is exposed between thespacers 16 a. The ISSG oxidization process is performed with a gas atmosphere of H2 and O2. The reason why the ISSG oxidization process is performed is for making rounded a top edge portion of each of second trenches (see “17” inFIG. 8 ), which are formed in a subsequent trench etch process. - Referring to
FIG. 8 , a trench etch process is performed to etch thesemiconductor substrate 10 that is exposed, thus forming thesecond trenches 17 that are deeper than thefirst trenches 15. A plurality of thesecond trenches 17 are formed in the cell region Cell, the low voltage region LV and the high voltage region HV, respectively. At this time, thesecond trenches 17 is preferably formed in a depth which can provide an isolation property so that the memory cells and/or the transistors can be electrically isolated. - Meanwhile, after the trench etch process, the top edge portions “A” of the
second trenches 17, which are coupled to the bottoms of thespacers 16 a, have a rounded shape by means of the ISSG oxidization process performed inFIG. 7 . - Referring to
FIG. 9 , an ISSG oxidization process is performed on thefirst trenches 15 and thesecond trenches 17 to form thewall oxide films 18 on the sidewalls of thesecond trenches 17. At this time, thewall oxide films 18 are formed with a thickness of about 15 to 30 Å. Furthermore, the ISSG oxidization process is performed at a temperature ranging 850° C. to 1000° C. and a pressure ranging from 1 to 10 torr in the gas atmosphere of H2 and O2. Furthermore, in the ISSG oxidization process, the gas atmosphere that includes H2 and O2 is set to be an O2-rich gas atmosphere. That is, the amount of O2 is higher than that of H2. Preferably, in the entire mixing ratio, the mixing ratio of O2 can be set to 33% to 60%, and the mixing ratio of H2 can be se to 0.5% to 33%. Higher amounts of O2 are used because O2 has a great influence upon the oxidation rate. If the ISSG oxidization process is performed at in the gas atmosphere of H2 and O2, it can be expressed into the following chemical equation A;
H2+O2→H2O+0+OH (A) - In equation (A), the O and OH radicals generated by reaction of H2 and O2 controls the oxidation rate.
- The ISSG oxidization process performed to form the
wall oxide films 18 can reduce a crystal orientation effect compared to a typical furnace process. - Meanwhile, a profile of the
wall oxide films 18 at the top edge portions of thesecond trenches 17 will be described in the case where thewall oxide films 18 are formed by a thermal process (using a furnace apparatus) and the case where thewall oxide films 18 are formed by the ISSG oxidization method as in a preferred embodiment. -
FIG. 11 shows a wall oxide film B formed by the ISSG process, which is performed at a temperature of about 1050° C., according to a preferred embodiment.FIG. 12 shows a wall oxide film C formed by a dry furnace process, which is performed at a temperature of about 1100° C. in a gas atmosphere of O2 using a furnace apparatus.FIG. 13 shows a wall oxide film D formed by a wet furnace process, which is performed at a temperature of about 950° C. using a furnace. - From FIGS. 11 to 13, it can be seen that the wall oxide film B formed by the ISSG oxidization process according to a preferred embodiment has a good profile characteristic at the top edge of the trench compared to the wall oxide films C and D formed using the furnace apparatus. Of course, the ISSG oxidization process according to a preferred embodiment can be performed at a lower temperature than that performed in the furnace. It is thus possible to reduce thermal stress.
- Meanwhile, the ISSG process for forming the
wall oxide films 18 can be performed after thespacers 16 a are removed using a cleaning process using DHF (or BOE) and SC-1, if necessary. - Referring to
FIG. 10 , an insulatingfilm 19 for an isolation film is formed on the entire surface including thewall oxide films 18. At this time, the insulatingfilm 19 is formed using a high density plasma (HDP) oxide film. At this time, the insulatingfilm 19 is preferably gap-filled so that voids are not generated in the first andsecond trenches film 19 can be deposited with a thickness of about 4000 Å to 10000 Å. - A polishing process is then performed to polish the entire top surface of the insulating
film 19. At this time, the polishing process is a CMP process, but it can be performed so that the hard mask is recessed to a given thickness or the hard mask is completely removed to a point where some of thepad nitride film 12 is recessed. - A cleaning process is applied to the polished entire surface. In this time, the cleaning process can be performed using DHF and SC-1 so as to compensate portions damaged in the polishing process or remove unnecessary materials, etc. which exist on the entire surface.
- Thereafter, although not shown in the drawings, an etch process using phosphoric acid (H3PO4) is performed to completely remove the hard mask and/or the
pad nitride film 12 which remain after the polishing process. At this time, the etch process is preferably performed using theoxide film 11 as an etch stopper so that thesemiconductor substrate 10 is not damaged. - Next, in order to control the effective field thickness (EFT) of the insulating
film 19 to a thickness of about 50 Å to 150 Å, a cleaning process using DHF and SC-1 can be effected. Thereby, the isolation films are formed in the cell region Cell, the low voltage region LV and the high voltage region HV. - As described above, after trenches are formed, an ISSG oxidization process is performed to form wall oxide films on sidewalls of the trenches. It prohibits facets from being formed at top and bottom edge portions of the trenches. Thus, the top edges of the trenches are rounded. Furthermore, the ISSG oxidization process is performed at low temperature for a relatively short time. Therefore, stress due to an oxidization process for a long time is reduced and a dislocation phenomenon is thus prevented from occurring.
- Although the foregoing description has been made with reference to the preferred embodiments, it is to be understood that changes and modifications of the disclosed methods may be made by the ordinary skilled in the art without departing from the spirit and scope of the appended claims.
Claims (7)
1. A method for forming wall oxide films in a flash memory device, comprising:
providing a semiconductor substrate in which trenches are formed; and
performing an oxidization process in a gas atmosphere comprising H2 and O2 in an ISSG oxidization mode, thus forming wall oxide films on sidewalls of the trenches.
2. The method according to claim 1 , wherein the ISSG oxidization mode is performed at a temperature ranging from 850° C. to 1000° C.
3. The method according to claim 2 , wherein the ISSG oxidization mode is performed at a pressure ranging from 1 torr to 10 torr.
4. The method according to claim 1 , wherein the gas atmosphere of H2 and O2 includes more O2 than H2.
5. The method according to claim 4 , wherein in the gas atmosphere comprising H2 and O2 has a mixing ratio of O2 ranging from 33% to 60%.
6. The method according to claim 4 , wherein in the gas atmosphere comprising H2 and O2 has of mixing ratio of H2 ranging from 0.5% to 33%.
7. The method according to claim 1 , wherein the wall oxide films are formed with a thickness ranging from 15 Å to 30 Å.
Priority Applications (1)
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US11/833,056 US20080020544A1 (en) | 2004-10-06 | 2007-08-02 | Method for Forming Wall Oxide Layer and Isolation Layer in Flash Memory Device |
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KR2004-0079505 | 2004-10-06 | ||
KR1020040079505A KR100650846B1 (en) | 2004-10-06 | 2004-10-06 | Method for forming isolation layer in flash memory device |
US11/016,436 US7279394B2 (en) | 2004-10-06 | 2004-12-17 | Method for forming wall oxide layer and isolation layer in flash memory device |
US11/833,056 US20080020544A1 (en) | 2004-10-06 | 2007-08-02 | Method for Forming Wall Oxide Layer and Isolation Layer in Flash Memory Device |
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US11/016,436 Expired - Fee Related US7279394B2 (en) | 2004-10-06 | 2004-12-17 | Method for forming wall oxide layer and isolation layer in flash memory device |
US11/833,056 Abandoned US20080020544A1 (en) | 2004-10-06 | 2007-08-02 | Method for Forming Wall Oxide Layer and Isolation Layer in Flash Memory Device |
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JP (1) | JP2006108605A (en) |
KR (1) | KR100650846B1 (en) |
CN (1) | CN100403525C (en) |
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CN108122842A (en) * | 2016-11-30 | 2018-06-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
WO2020131208A1 (en) * | 2018-12-20 | 2020-06-25 | Applied Materials, Inc. | Memory cell fabrication for 3d nand applications |
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KR100657088B1 (en) * | 2004-12-30 | 2006-12-12 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
KR100629606B1 (en) * | 2004-12-31 | 2006-09-27 | 동부일렉트로닉스 주식회사 | Method for improving the gate oxidation quality of high voltage device area |
TWI240989B (en) * | 2005-01-17 | 2005-10-01 | Powerchip Semiconductor Corp | Method for forming trench gate dielectric layer |
US20060223267A1 (en) * | 2005-03-31 | 2006-10-05 | Stefan Machill | Method of production of charge-trapping memory devices |
KR100733446B1 (en) * | 2005-11-16 | 2007-06-29 | 주식회사 하이닉스반도체 | Method for fabricating the same of semiconductor device with recess gate of flask shape |
KR100799151B1 (en) * | 2006-06-29 | 2008-01-29 | 주식회사 하이닉스반도체 | Method for forming isolation layer of flash memory device |
KR100726093B1 (en) * | 2006-07-28 | 2007-06-08 | 동부일렉트로닉스 주식회사 | Mathode of manufacturing semiconductor device |
KR100790296B1 (en) * | 2006-12-04 | 2008-01-02 | 주식회사 하이닉스반도체 | Method of manufacturing a flash memory device |
KR100933812B1 (en) * | 2007-07-02 | 2009-12-24 | 주식회사 하이닉스반도체 | Manufacturing method of semiconductor device |
JP4886801B2 (en) * | 2009-03-02 | 2012-02-29 | 株式会社東芝 | Manufacturing method of semiconductor device |
JP2010283199A (en) * | 2009-06-05 | 2010-12-16 | Oki Semiconductor Co Ltd | Method for manufacturing semiconductor device |
CN109950246A (en) * | 2017-12-21 | 2019-06-28 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
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- 2004-12-15 DE DE102004060669A patent/DE102004060669A1/en not_active Withdrawn
- 2004-12-17 US US11/016,436 patent/US7279394B2/en not_active Expired - Fee Related
- 2004-12-21 JP JP2004369027A patent/JP2006108605A/en active Pending
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TW200612514A (en) | 2006-04-16 |
TWI293494B (en) | 2008-02-11 |
US7279394B2 (en) | 2007-10-09 |
DE102004060669A1 (en) | 2006-04-06 |
DE102004060669A8 (en) | 2006-08-10 |
KR100650846B1 (en) | 2006-11-27 |
KR20060030651A (en) | 2006-04-11 |
CN1758428A (en) | 2006-04-12 |
JP2006108605A (en) | 2006-04-20 |
US20060073661A1 (en) | 2006-04-06 |
CN100403525C (en) | 2008-07-16 |
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