CN104779170A - Forming method of fin field effect transistor - Google Patents
Forming method of fin field effect transistor Download PDFInfo
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- CN104779170A CN104779170A CN201510198894.4A CN201510198894A CN104779170A CN 104779170 A CN104779170 A CN 104779170A CN 201510198894 A CN201510198894 A CN 201510198894A CN 104779170 A CN104779170 A CN 104779170A
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- 230000005669 field effect Effects 0.000 title claims abstract description 41
- 238000000034 method Methods 0.000 title claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000011159 matrix material Substances 0.000 claims abstract description 17
- 239000011248 coating agent Substances 0.000 claims description 42
- 238000000576 coating method Methods 0.000 claims description 42
- 239000000463 material Substances 0.000 claims description 39
- 230000015572 biosynthetic process Effects 0.000 claims description 20
- 238000005516 engineering process Methods 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 7
- 239000000126 substance Substances 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 229910004140 HfO Inorganic materials 0.000 claims description 4
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 4
- 238000005240 physical vapour deposition Methods 0.000 claims description 4
- 229910021332 silicide Inorganic materials 0.000 claims description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 claims description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000000407 epitaxy Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 description 10
- 238000011982 device technology Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a forming method of a fin field effect transistor. The method comprises the following steps: forming a fin field effect transistor matrix on a substrate, and forming a source, a drain, a first fin channel region and a second fin channel region, wherein the first fin channel region and the second fin channel region are positioned between the source and the drain; forming a first oxide layer, and covering the matrix; removing the first oxide layer on the side of the second fin channel region; forming a second oxide layer, and covering the matrix; forming a grid structure stretching across the first fin channel region and the second fin channel region, and removing the oxide layer from a region except the bottom of the grid structure; separating the grid structure between the first fin channel region and the second fin channel region to form a first grid structure and a second grid structure, so that one fin field effect transistor device can work under two different working voltages, and different device performances can be obtained.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing technology field, more specifically, relate to a kind of formation method of the fin formula field effect transistor that can work under two kinds of operating voltages.
Background technology
Semiconductor integrated circuit (IC) industry experienced by and develops rapidly.In the evolution of IC, usually increase functional density (i.e. the quantity of the interconnect devices of each chip area), and reduce physical dimension (minimum device namely using manufacturing process to manufacture or interconnection line).The raising of IC performance is mainly realized with the speed improving it by the size constantly reducing integrated circuit (IC)-components.This scaled technological advantage is to improve production efficiency and reduces correlative charges.Meanwhile, this scaled technique too increases process and manufactures the complexity of IC.
It is generally acknowledged, through great efforts, CMOS technology is still likely advanced to 20 nanometers even 10 nm technology node, but after 20 nanometer nodes, traditional planar CMOS technology further develops being difficult to.In recent years, in the middle of proposed various new technologies, multiple-grid MOS device technology is considered to the technology being hopeful most to be applied after sub-20 nanometer nodes.This is because compared with tradition list gate device, multi-gate device has stronger short channel rejection ability, better subthreshold behavior, higher driving force and higher current densities can be brought.
In the process of seeking higher device density, higher performance and lower expense, along with the sustainable development of IC technique is to nanometer technology process node, in order to overcome the drive current density of short-channel effect and raising unit are, some manufacturers have started how to consider from planar CMOS transistor to the transition problem of three-dimensional fin formula field effect transistor (FinFET) device architecture.FinFET is a kind of multiple-grid MOS device, this structure owing to having more grid-control area, narrower raceway groove depleted region and have very outstanding short channel control and very high drive current.Compared with planar transistor, FinFET owing to improving the control to raceway groove, thus reduces short-channel effect.
Challenge in manufacturing and designing has promoted the development of FinFET.At present, FinFET can be realized by the planar CMOS process of routine because of its self-alignment structure, thus becomes most promising multi-gate device, and has appeared in the application in 20nm technology generation.But, although the method for existing FinFET and manufacture FinFET meets its expection object substantially, be not can both be entirely satisfactory in all respects.
Along with the development of integrated circuit, device size is more and more less, and integrated level is more and more higher.Meanwhile, people also become more and more higher to the requirement of device, and people more wish to realize multiple different performance requirement on same device.At present, the traditional manufacturing technique of FinFET carries out integral manufacturing on substrate, and form consistent structure.Make a device only have an operating voltage thus, thus service behaviour just seems more single.
Summary of the invention
The object of the invention is to the above-mentioned defect overcoming prior art existence, a kind of formation method of fin formula field effect transistor is provided, work under making to can be implemented in two kinds of different operating voltages on same fin formula field effect transistor device, and different device performances can be obtained.
For achieving the above object, technical scheme of the present invention is as follows:
A formation method for fin formula field effect transistor, comprises the following steps:
Step S01: provide semi-conductive substrate, forms fin formula field effect transistor matrix over the substrate, comprises the source region and drain region that are formed and be oppositely arranged, and first, second fin-shaped channel district side by side between described source region and drain region;
Step S02: form one first oxide skin(coating) over the substrate, covers described fin formula field effect transistor matrix;
Step S03: between first, second fin-shaped channel district described, removes described first oxide skin(coating) of described second side, fin-shaped channel district;
Step S04: form one second oxide skin(coating) over the substrate, covers described fin formula field effect transistor matrix;
Step S05: formation one across the grid in first, second fin-shaped channel district described, and removes described gate bottom with the described oxide skin(coating) of exterior domain, then, forms sidewall in described grid both sides;
Step S06: described grid and sidewall are separated, to form first, second grid structure between first, second fin-shaped channel district described.
Preferably, described fin formula field effect transistor basis material is formed by epitaxy technology over the substrate.
Preferably, described fin formula field effect transistor basis material is monocrystalline silicon, germanium silicon or carbon silicon.
Preferably, first, second oxide skin(coating) described is formed by original position moisture-generation process, ald or chemical meteorology deposition over the substrate.
Preferably, first, second oxide skin(coating) material described is SiO
2, SiON or HfO
2.
Preferably, in step S05, described grid material is the polysilicon gate material formed by chemical meteorology deposition.
Preferably, described side-wall material is by least one deck silica or silicon nitride are formed.
Preferably, in step S05, described grid material is formed by physical vapor deposition.
Preferably, described grid material is metal or metal silicide.
Preferably, in step S06, the method that described grid and sidewall are separated between first, second fin-shaped channel district described comprises: first removed the grid between first, second fin-shaped channel district described and side-wall material by dry etching mode, then removes the described oxide skin(coating) material of its corresponding bottom by wet processing mode.
As can be seen from technique scheme, the present invention by forming the oxide skin(coating) of different-thickness respectively on first, second fin-shaped channel plot structure, can realize making different raceway grooves obtain different conducting voltage, work under making to can be implemented in two kinds of different operating voltages on same fin formula field effect transistor device; And can make device can difference according to demand, between first, second fin-shaped channel district, carry out the adjustment setting of voltage, to obtain different device performances.
Accompanying drawing explanation
Fig. 1 is the flow chart of the formation method of a kind of fin formula field effect transistor of the present invention;
Fig. 2 ~ Fig. 9 is the device technology structural representation that a preferred embodiment of the present invention is formed according to the method for Fig. 1.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail.
It should be noted that, in following embodiment, when describing embodiments of the present invention in detail, in order to clearly represent structure of the present invention so that explanation, special to the structure in accompanying drawing not according to general scale, and carried out partial enlargement, distortion and simplify processes, therefore, should avoid being understood in this, as limitation of the invention.
In following the specific embodiment of the present invention, refer to Fig. 1, Fig. 1 is the flow chart of the formation method of a kind of fin formula field effect transistor of the present invention; Meanwhile, incorporated by reference to consulting Fig. 2 ~ Fig. 9, Fig. 2 ~ Fig. 9 is the device technology structural representation that a preferred embodiment of the present invention is formed according to the method for Fig. 1.As shown in Figure 1, the formation method of a kind of fin formula field effect transistor of the present invention, comprises the following steps:
As shown in frame 01, step S01: provide semi-conductive substrate, forms fin formula field effect transistor matrix over the substrate, comprises the source region and drain region that are formed and be oppositely arranged, and first, second fin-shaped channel district side by side between described source region and drain region.
Refer to Fig. 2, Fig. 2 be fin formula field effect transistor matrix overlook direction schematic diagram.Substrate 1 of the present invention is chosen as silicon chip or SOI (silicon-on-insulator) substrate of monocrystalline.For SOI technology, but be not limited to SOI technology, first, the existing known technology of industry can be adopted, SOI substrate 1 adopts such as growth technology to form fin formula field effect transistor (FinFET) base material layer; As an optional execution mode, described FinFET basis material can select the semi-conducting materials such as monocrystalline silicon, germanium silicon or carbon silicon; Then, by carrying out the coating of photoresist, exposure and development, carry out graphically to described FinFET basis material; Then, the source region 2 and drain region 5 that are oppositely arranged in diagram FinFET matrix is formed by etching, and first, second fin-shaped channel district 3,4 (first, second Fin3, the 4) structure side by side between described source region 2 and drain region 5.
As shown in frame 02, step S02: form one first oxide skin(coating) over the substrate, covers described fin formula field effect transistor matrix.
Refer to Fig. 3, Fig. 3 be first, second Fin3,4 cross-wise direction cutaway view.Next, deposited overall one first oxide skin(coating) 6 on described substrate 1, covers (comprising source region 2, drain region 5 and first, second Fin3,4) by described FinFET matrix.As an optional execution mode, described substrate 1 forms described first oxide skin(coating) 6 by original position moisture-generation process (ISSG), ald (ALD) or chemical meteorology deposition (CVD).Further alternatively, described first oxide skin(coating) material can select SiO
2, SiON or HfO
2deng oxide material.
As shown in frame 03, step S03: between first, second fin-shaped channel district described, removes described first oxide skin(coating) of described second side, fin-shaped channel district.
Refer to Fig. 4, Fig. 4 be equally first, second Fin3,4 cross-wise direction cutaway view.Next, from between first, second fin-shaped channel district 3,4, such as be chosen at the centre position in first, second fin-shaped channel district 3,4 described, the described first oxide skin(coating) material of described second side, fin-shaped channel district 4 is removed, make still to be coated with the first oxide skin(coating) 6 in the first side, fin-shaped channel district 3, and the second side, fin-shaped channel district 4 will not have the first oxide skin(coating) to cover.As an optional execution mode, wet processing (WET clean) can be adopted to remove the described first oxide skin(coating) material of the second side, fin-shaped channel district 4 covering.
As shown in frame 04, step S04: form one second oxide skin(coating) over the substrate, covers described fin formula field effect transistor matrix.
Refer to Fig. 5, Fig. 5 be equally first, second Fin3,4 cross-wise direction cutaway view.Next, deposited overall one second oxide skin(coating) 7 again on described substrate 1, covers described FinFET matrix.As an optional execution mode, described substrate 1 forms described second oxide skin(coating) 7 by original position moisture-generation process (ISSG), ald (ALD) or chemical meteorology deposition (CVD).Further alternatively, described second oxide skin(coating) material can select SiO
2, SiON or HfO
2deng oxide material.As can be seen from Figure 5, after second oxide skin(coating) 7 deposits, in described first side, fin-shaped channel district 3, oxide skin(coating) (comprising first, second oxide skin(coating) 6, the 7) gross thickness of surrounding described first fin-shaped channel district 3 will be greater than in described second side, fin-shaped channel district 4, surround oxide skin(coating) (only including the second oxide skin(coating) 7) thickness in described second fin-shaped channel district 4.After FinFET manufacture completes, the difference of this two places oxide layer thicknesses, can realize making first, second different fin-shaped channel districts 3,4 to obtain different conducting voltage, work under making to can be implemented in two kinds of different operating voltages in same FinFET.
As shown in frame 05, step S05: formation one across the grid in first, second fin-shaped channel district described, and removes described gate bottom with the described oxide skin(coating) of exterior domain, then, forms sidewall in described grid both sides.
Refer to Fig. 6, Fig. 6 be fin formula field effect transistor matrix overlook direction schematic diagram.Next, the existing known technology of industry can be adopted, first, second fin-shaped channel district 3,4 forms grid 8.As an optional execution mode, described grid material can be the polysilicon gate material formed by chemical meteorology deposition (CVD); Then, adopt photoetching process, carry out the coating of photoresist, exposure and development, carry out graphically to described polysilicon gate material layer, and remove unnecessary polysilicon segment by etch process, form across and surround the polysilicon gate 8 in first, second fin-shaped channel district 3,4 described.As another optional execution mode, described grid material also can be the metal or metal silicide gate material that are formed by physical vapor deposition (PVD), and forms across and surround metal or the metal silicide gate 8 in first, second fin-shaped channel district described further.Then, described gate bottom is removed with the described oxide skin(coating) of exterior domain (comprising first, second oxide skin(coating)).As an optional execution mode, wet processing (WET clean) can be adopted to remove gate bottom with the described oxide skin(coating) material of exterior domain.Then, as shown in Figure 7, the existing known technology of industry can be adopted, form sidewall 9 in described grid 8 both sides.Described side-wall material can by least one deck silica or silicon nitride are formed.
As shown in frame 06, step S06: described grid and sidewall are separated, to form first, second grid structure between first, second fin-shaped channel district described.
Finally, refer to Fig. 8 and Fig. 9, Fig. 9 is the device profile structural representation formed in the step S06 corresponding with Fig. 8 vertical view.Next, grid described in can first being removed by such as dry etching (Dry etch) mode between first, second fin-shaped channel district 3,4 and side-wall material, the described oxide skin(coating) material bottom this part of grid pole and side-wall material correspondence is removed again by such as wet processing (WET clean) mode, described grid 8 and sidewall 9 are separated between first, second fin-shaped channel district 3,4 described, form first, second grid structure 8-1,8-2.When separated grid structure, the gap keeping necessity between first, second grid structure 8-1,8-2 formed should be made, and ensure to make all with the first and second oxide skin(coating)s 6,7 bottom first grid structure 8-1, without the first oxide skin(coating) 6 bottom second grid structure 8-2.
Next, the manufacture of FinFET subsequent technique can be proceeded.
When using the FinFET formed as stated above, when voltage is lower, by voltage-drop loading on the 2nd Fin4 with relatively thin oxide layer, the 2nd Fin4 conducting can be made; When voltage is higher, by voltage-drop loading having on the Fin3 compared with thick oxide layers, a Fin3 conducting can be made.Thus utilize that the present invention can realize making first, second Fin3,4 different raceway grooves obtain different conducting voltage, work under making to can be implemented in two kinds of different operating voltages on same fin formula field effect transistor device.
Meanwhile, FinFET difference according to demand can also carry out adjustment setting, to obtain different device performances.Such as, according to different voltage, can select to load on different Fin, realize the work under different voltage; Also can, under same operating voltage, select voltage-drop loading to obtain different device performances on different Fin; Can also be that the Fin3 side device loading high break-over voltage is used as protection device; when voltage exceedes certain value; the voltage loaded is switched on a Fin3 of high break-over voltage by the 2nd Fin4 of low conducting voltage, and the 2nd Fin4 of low conducting voltage can be prevented breakdown.
Above-describedly be only the preferred embodiments of the present invention; described embodiment is also not used to limit scope of patent protection of the present invention; therefore the equivalent structure that every utilization specification of the present invention and accompanying drawing content are done changes, and in like manner all should be included in protection scope of the present invention.
Claims (10)
1. a formation method for fin formula field effect transistor, is characterized in that, comprise the following steps:
Step S01: provide semi-conductive substrate, forms fin formula field effect transistor matrix over the substrate, comprises the source region and drain region that are formed and be oppositely arranged, and first, second fin-shaped channel district side by side between described source region and drain region;
Step S02: form one first oxide skin(coating) over the substrate, covers described fin formula field effect transistor matrix;
Step S03: between first, second fin-shaped channel district described, removes described first oxide skin(coating) of described second side, fin-shaped channel district;
Step S04: form one second oxide skin(coating) over the substrate, covers described fin formula field effect transistor matrix;
Step S05: formation one across the grid in first, second fin-shaped channel district described, and removes described gate bottom with the described oxide skin(coating) of exterior domain, then, forms sidewall in described grid both sides;
Step S06: described grid and sidewall are separated, to form first, second grid structure between first, second fin-shaped channel district described.
2. the formation method of fin formula field effect transistor according to claim 1, is characterized in that, forms described fin formula field effect transistor basis material over the substrate by epitaxy technology.
3. the formation method of fin formula field effect transistor according to claim 1 and 2, is characterized in that, described fin formula field effect transistor basis material is monocrystalline silicon, germanium silicon or carbon silicon.
4. the formation method of fin formula field effect transistor according to claim 1, is characterized in that, forms first, second oxide skin(coating) described over the substrate by original position moisture-generation process, ald or chemical meteorology deposition.
5. the formation method of the fin formula field effect transistor according to claim 1 or 4, is characterized in that, first, second oxide skin(coating) material described is SiO
2, SiON or HfO
2.
6. the formation method of fin formula field effect transistor according to claim 1, is characterized in that, in step S05, described grid material is the polysilicon gate material formed by chemical meteorology deposition.
7. the formation method of fin formula field effect transistor according to claim 1, is characterized in that, described side-wall material is by least one deck silica or silicon nitride are formed.
8. the formation method of fin formula field effect transistor according to claim 1, is characterized in that, in step S05, described grid material is formed by physical vapor deposition.
9. the formation method of the fin formula field effect transistor according to claim 1 or 8, is characterized in that, described grid material is metal or metal silicide.
10. the formation method of fin formula field effect transistor according to claim 1, it is characterized in that, in step S06, the method that described grid and sidewall are separated between first, second fin-shaped channel district described comprises: first removed the grid between first, second fin-shaped channel district described and side-wall material by dry etching mode, then removes the described oxide skin(coating) material of its corresponding bottom by wet processing mode.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108122842A (en) * | 2016-11-30 | 2018-06-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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| CN102956702A (en) * | 2011-08-31 | 2013-03-06 | 中国科学院微电子研究所 | Semiconductor apparatus and manufacturing method thereof |
| CN104160507A (en) * | 2011-12-28 | 2014-11-19 | 英特尔公司 | Methods of integrating multiple gate dielectric transistors on a tri-gate (finfet) process |
| US20140327089A1 (en) * | 2013-01-08 | 2014-11-06 | Globalfoundries Inc. | Finfet devices having recessed liner materials to define different fin heights |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108122842A (en) * | 2016-11-30 | 2018-06-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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