CN104779169A - Manufacturing method of double-working-voltage FinFET structure device - Google Patents
Manufacturing method of double-working-voltage FinFET structure device Download PDFInfo
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- CN104779169A CN104779169A CN201510198893.XA CN201510198893A CN104779169A CN 104779169 A CN104779169 A CN 104779169A CN 201510198893 A CN201510198893 A CN 201510198893A CN 104779169 A CN104779169 A CN 104779169A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 42
- 239000000463 material Substances 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000011159 matrix material Substances 0.000 claims abstract description 11
- 239000011248 coating agent Substances 0.000 claims description 22
- 238000000576 coating method Methods 0.000 claims description 22
- 239000004065 semiconductor Substances 0.000 claims description 18
- 238000005516 engineering process Methods 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 6
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 238000005240 physical vapour deposition Methods 0.000 claims description 4
- 229910021332 silicide Inorganic materials 0.000 claims description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 4
- 229910004140 HfO Inorganic materials 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 claims description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 238000000407 epitaxy Methods 0.000 claims description 2
- 238000011982 device technology Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a manufacturing method of a double-working-voltage FinFET structure device. The method comprises the following steps: forming a FinFET matrix on a substrate, and forming a source, a drain, a first Fin structure and a second Fin structure, wherein the first Fin structure and the second Fin structure are positioned between the source and the drain; performing inverted doping, opposite to doping for the source and the drain, on the second Fin structure; forming an oxide layer on the substrate, and covering the FinFET matrix; forming a grid stretching across the first Fin structure and the second Fin structure, removing the oxide layer from an area except the bottom of the grid, and then forming sidewalls on two sides of the grid; removing grid and sidewall materials between the first Fin structure and the second Fin structure and the oxide layer at the bottom, and forming a first grid structure and a second grid structure, so that one FinFET device can work under two different working voltages, and different device performance can be obtained.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing technology field, more specifically, relate to a kind of manufacture method of the FinFET structure device that can work under two kinds of operating voltages.
Background technology
Semiconductor integrated circuit (IC) industry experienced by and develops rapidly.In the evolution of IC, usually increase functional density (i.e. the quantity of the interconnect devices of each chip area), and reduce physical dimension (minimum device namely using manufacturing process to manufacture or interconnection line).The raising of IC performance is mainly realized with the speed improving it by the size constantly reducing integrated circuit (IC)-components.This scaled technological advantage is to improve production efficiency and reduces correlative charges.Meanwhile, this scaled technique too increases process and manufactures the complexity of IC.
It is generally acknowledged, through great efforts, CMOS technology is still likely advanced to 20 nanometers even 10 nm technology node, but after 20 nanometer nodes, traditional planar CMOS technology further develops being difficult to.In recent years, in the middle of proposed various new technologies, multiple-grid MOS device technology is considered to the technology being hopeful most to be applied after sub-20 nanometer nodes.This is because compared with tradition list gate device, multi-gate device has stronger short channel rejection ability, better subthreshold behavior, higher driving force and higher current densities can be brought.
In the process of seeking higher device density, higher performance and lower expense, along with the sustainable development of IC technique is to nanometer technology process node, in order to overcome the drive current density of short-channel effect and raising unit are, some manufacturers have started how to consider from planar CMOS transistor to the transition problem of three-dimensional FinFET (fin formula field effect transistor) device architecture.FinFET is a kind of multiple-grid MOS device, this structure owing to having more grid-control area, narrower raceway groove depleted region and have very outstanding short channel control and very high drive current.Compared with planar transistor, FinFET owing to improving the control to raceway groove, thus reduces short-channel effect.
Challenge in manufacturing and designing has promoted the development of FinFET.At present, FinFET can be realized by the planar CMOS process of routine because of its self-alignment structure, thus becomes most promising multi-gate device, and has appeared in the application in 20nm technology generation.But, although the method for existing FinFET and manufacture FinFET meets its expection object substantially, be not can both be entirely satisfactory in all respects.
Along with the development of integrated circuit, device size is more and more less, and integrated level is more and more higher.Meanwhile, people also become more and more higher to the requirement of device, and people more wish to realize multiple different performance requirement on same device.At present, the traditional manufacturing technique of FinFET carries out integral manufacturing on substrate, and form consistent structure.Make a device only have an operating voltage thus, thus service behaviour just seems more single.
Summary of the invention
The object of the invention is to the above-mentioned defect overcoming prior art existence, the manufacture method of a kind of pair of operating voltage FinFET structure device is provided, work under making to can be implemented in two kinds of different operating voltages on same FinFET structure device, and different device performances can be obtained.
For achieving the above object, technical scheme of the present invention is as follows:
A manufacture method for pair operating voltage FinFET structure device, comprises the following steps:
Step S01: provide semi-conductive substrate, forms semi-conductor layer over the substrate;
Step S02: semiconductor layer described in patterning, forms FinFET matrix, comprises the source region and drain region that are formed and be oppositely arranged, and first, second Fin structure side by side between described source region and drain region;
Step S03: the transoid contrary with source region and drain region is carried out to described 2nd Fin structure and adulterates;
Step S04: form monoxide layer over the substrate, covers described FinFET matrix;
Step S05: formation one across the grid of first, second Fin structure described, and removes described gate bottom with the described oxide skin(coating) of exterior domain, then, forms sidewall in described grid both sides;
Step S06: the grid described in removing between first, second Fin structure and the oxide skin(coating) of side-wall material and bottom thereof, forms first, second grid structure with corresponding in first, second Fin structure described.
Preferably, described semiconductor layer is formed by epitaxy technology over the substrate.
Preferably, described semiconductor layer material is monocrystalline silicon, germanium silicon or carbon silicon.
Preferably, by the method for ion implantation, transoid doping is carried out to described 2nd Fin structure.
Preferably, described oxide skin(coating) is formed by original position moisture-generation process, ald or chemical meteorology deposition over the substrate.
Preferably, described oxide skin(coating) material is SiO
2, SiON or HfO
2.
Preferably, described grid material is the polysilicon gate material formed by chemical meteorology deposition.
Preferably, described side-wall material is by least one deck silica or silicon nitride are formed.
Preferably, described grid material is the metal or metal silicide gate material that are formed by physical vapor deposition.
Preferably, in step S06, the method of the grid described in removing between first, second Fin structure and the oxide skin(coating) of side-wall material and bottom thereof comprises: the grid described in first being removed by dry etching mode between first, second Fin structure and side-wall material, then is removed the described oxide skin(coating) material of its corresponding bottom by wet processing mode.
As can be seen from technique scheme, the present invention adulterates by carrying out the transoid contrary with source region and drain region to the 2nd Fin structure, can realize making the different raceway grooves of first, second Fin structure to obtain different conducting voltage, work under making to can be implemented in two kinds of different operating voltages on same FinFET structure device; And can make device can difference according to demand, between first, second Fin structure, carry out the adjustment setting of voltage, to obtain different device performances.
Accompanying drawing explanation
Fig. 1 is the flow chart of the manufacture method of the present invention's a kind of pair of operating voltage FinFET structure device;
Fig. 2 ~ Fig. 9 is the device technology structural representation that a preferred embodiment of the present invention is formed according to the method for Fig. 1.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail.
It should be noted that, in following embodiment, when describing embodiments of the present invention in detail, in order to clearly represent structure of the present invention so that explanation, special to the structure in accompanying drawing not according to general scale, and carried out partial enlargement, distortion and simplify processes, therefore, should avoid being understood in this, as limitation of the invention.
In following the specific embodiment of the present invention, refer to Fig. 1, Fig. 1 is the flow chart of the manufacture method of the present invention's a kind of pair of operating voltage FinFET structure device; Meanwhile, incorporated by reference to consulting Fig. 2 ~ Fig. 9, Fig. 2 ~ Fig. 9 is the device technology structural representation that a preferred embodiment of the present invention is formed according to the method for Fig. 1.As shown in Figure 1, the manufacture method of a kind of pair of operating voltage FinFET structure device of the present invention, comprises the following steps:
As shown in frame 01, step S01: provide semi-conductive substrate, forms semi-conductor layer over the substrate.
Refer to Fig. 2, Fig. 2 be formed semiconductor layer overlook direction schematic diagram.Substrate 1 of the present invention is chosen as silicon chip or SOI (silicon-on-insulator) substrate of monocrystalline.For SOI technology, but be not limited to SOI technology, first, the existing known technology of industry can be adopted, SOI substrate 1 adopts such as growth technology to form semi-conductor layer 2.As an optional execution mode, described semiconductor layer material can select the semi-conducting materials such as monocrystalline silicon, germanium silicon or carbon silicon.
As shown in frame 02, step S02: semiconductor layer described in patterning, forms FinFET matrix, comprises the source region and drain region that are formed and be oppositely arranged, and first, second Fin structure side by side between described source region and drain region.
Refer to Fig. 3.Next, by carrying out the coating of photoresist, exposure and development, patterning is carried out to described semiconductor layer 2; Then, illustrated FinFET matrix is formed by etch process, FinFET matrix has the source region 3 and drain region 6 that are oppositely arranged, and first, second Fin structure 4,5 (first, second fin-shaped semiconductor structure 4,5) side by side between described source region 3 and drain region 6.
As shown in frame 03, step S03: the transoid contrary with source region and drain region is carried out to described 2nd Fin structure and adulterates.
Refer to Fig. 4.Next, by the method for such as ion implantation, the transoid contrary with drain region 6 with source region 3 is carried out to the 2nd Fin structure 5 and adulterates.Need not adulterate to a Fin structure 4.After FinFET manufacture completes, first, second Fin structure 4,5 difference of whether adulterating herein, can realize making first, second different Fin structures 4,5 to obtain different conducting voltage, work under making to can be implemented in two kinds of different operating voltages in same FinFET.
As shown in frame 04, step S04: form monoxide layer over the substrate, covers described FinFET matrix.
Refer to Fig. 5, Fig. 5 is the cross-wise direction cutaway view forming oxide skin(coating).Next, deposited overall monoxide layer 7 on described substrate 1, covers described FinFET matrix.As an optional execution mode, described substrate 1 forms described oxide skin(coating) 7 by original position moisture-generation process (ISSG), ald (ALD) or chemical meteorology deposition (CVD).Further alternatively, described oxide skin(coating) material can select SiO
2, SiON or HfO
2deng oxide material, the invention is not restricted to these materials.
As shown in frame 05, step S05: formation one across the grid of first, second Fin structure described, and removes described gate bottom with the described oxide skin(coating) of exterior domain, then, forms sidewall in described grid both sides.
Refer to Fig. 6.Next, the existing known technology of industry can be adopted, first, second Fin structure 4,5 forms grid 8.As an optional execution mode, described grid material can be the polysilicon gate material formed by chemical meteorology deposition (CVD); Then, adopt photoetching process, carry out the coating of photoresist, exposure and development, carry out graphically to described polysilicon gate material layer, and remove unnecessary polysilicon segment by etch process, form across and surround the polysilicon gate 8 of first, second Fin structure 4,5 described.As another optional execution mode, described grid material also can be the metal or metal silicide gate material that are formed by physical vapor deposition (PVD), and forms across and surround metal or the metal silicide gate 8 of first, second Fin structure 4,5 described further.Then, the described oxide skin(coating) 7 with exterior domain bottom described grid 8 is removed.As an optional execution mode, wet processing (WET clean) can be adopted to remove bottom grid 8 with the described oxide skin(coating) material of exterior domain.Then, as shown in Figure 7, the existing known technology of industry can be adopted, form sidewall 9 in described grid 8 both sides.Described side-wall material can by least one deck silica or silicon nitride are formed.
As shown in frame 06, step S06: the grid described in removing between first, second Fin structure and the oxide skin(coating) of side-wall material and bottom thereof, forms first, second grid structure with corresponding in first, second Fin structure described.
Finally, refer to Fig. 8 and Fig. 9, Fig. 9 is the device profile structural representation formed in the step S06 corresponding with Fig. 8 vertical view.Next, grid described in can first being removed by such as dry etching (Dry etch) mode between first, second Fin structure 4,5 and side-wall material, the described oxide skin(coating) material bottom this part of grid pole and side-wall material correspondence is removed again by such as wet processing (WET clean) mode, stop at substrate 1 layer, described grid 8 and sidewall 9 are separated between first, second Fin structure 4,5 described, thus correspondence form first, second grid structure 8-1,8-2 separately in first, second Fin structure 4,5 described.
Next, the manufacture of FinFET subsequent technique structure can be proceeded.
When using the FinFET formed as stated above, when voltage is lower, by voltage-drop loading in a Fin structure 4 of undoped, Fin structure 4 conducting can be made; When voltage is higher, in the 2nd Fin structure 5 voltage-drop loading can adulterated in transoid, make the 2nd Fin structure 5 conducting.Thus, utilize that the present invention can realize making first, second Fin structure 4,5 different raceway grooves obtain different conducting voltage, work under making to can be implemented in two kinds of different operating voltages in same FinFET.
Meanwhile, FinFET difference according to demand can also carry out adjustment setting, to obtain different device performances.Such as, according to different voltage, can select to load in different Fin structures, realize the work under different voltage; Also can, under same operating voltage, select voltage-drop loading to obtain different device performances in different Fin structures; Can also be that the 2nd Fin structure 5 side device loading high break-over voltage is used as protection device; when voltage exceedes certain value; the voltage loaded is switched in the 2nd Fin structure 5 of high break-over voltage by a Fin structure 4 of low conducting voltage, and a Fin structure 4 of low conducting voltage can be prevented breakdown.
Above-describedly be only the preferred embodiments of the present invention; described embodiment is also not used to limit scope of patent protection of the present invention; therefore the equivalent structure that every utilization specification of the present invention and accompanying drawing content are done changes, and in like manner all should be included in protection scope of the present invention.
Claims (10)
1. a manufacture method for two operating voltage FinFET structure device, is characterized in that, comprise the following steps:
Step S01: provide semi-conductive substrate, forms semi-conductor layer over the substrate;
Step S02: semiconductor layer described in patterning, forms FinFET matrix, comprises the source region and drain region that are formed and be oppositely arranged, and first, second Fin structure side by side between described source region and drain region;
Step S03: the transoid contrary with source region and drain region is carried out to described 2nd Fin structure and adulterates;
Step S04: form monoxide layer over the substrate, covers described FinFET matrix;
Step S05: formation one across the grid of first, second Fin structure described, and removes described gate bottom with the described oxide skin(coating) of exterior domain, then, forms sidewall in described grid both sides;
Step S06: the grid described in removing between first, second Fin structure and the oxide skin(coating) of side-wall material and bottom thereof, forms first, second grid structure with corresponding in first, second Fin structure described.
2. the manufacture method of according to claim 1 pair of operating voltage FinFET structure device, is characterized in that, forms described semiconductor layer over the substrate by epitaxy technology.
3. the manufacture method of according to claim 1 and 2 pair of operating voltage FinFET structure device, is characterized in that, described semiconductor layer material is monocrystalline silicon, germanium silicon or carbon silicon.
4. the manufacture method of according to claim 1 pair of operating voltage FinFET structure device, is characterized in that, carries out transoid doping by the method for ion implantation to described 2nd Fin structure.
5. the manufacture method of according to claim 1 pair of operating voltage FinFET structure device, is characterized in that, forms described oxide skin(coating) over the substrate by original position moisture-generation process, ald or chemical meteorology deposition.
6. the manufacture method of two operating voltage FinFET structure device according to claim 1 or 5, it is characterized in that, described oxide skin(coating) material is SiO
2, SiON or HfO
2.
7. the manufacture method of according to claim 1 pair of operating voltage FinFET structure device, is characterized in that, described grid material is the polysilicon gate material formed by chemical meteorology deposition.
8. the manufacture method of according to claim 1 pair of operating voltage FinFET structure device, is characterized in that, described side-wall material is by least one deck silica or silicon nitride are formed.
9. the manufacture method of according to claim 1 pair of operating voltage FinFET structure device, is characterized in that, described grid material is the metal or metal silicide gate material that are formed by physical vapor deposition.
10. the manufacture method of according to claim 1 pair of operating voltage FinFET structure device, it is characterized in that, in step S06, the method of the grid described in removing between first, second Fin structure and the oxide skin(coating) of side-wall material and bottom thereof comprises: the grid described in first being removed by dry etching mode between first, second Fin structure and side-wall material, then is removed the described oxide skin(coating) material of its corresponding bottom by wet processing mode.
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| CN201510198893.XA CN104779169B (en) | 2015-04-22 | 2015-04-22 | A kind of manufacture method of double work voltage FinFET structure device |
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| CN201510198893.XA CN104779169B (en) | 2015-04-22 | 2015-04-22 | A kind of manufacture method of double work voltage FinFET structure device |
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|---|---|---|---|---|
| CN1423837A (en) * | 1999-11-18 | 2003-06-11 | 英特尔公司 | Method of fabrication dual threshold voltage N-channel and P-channel MOSFETS with a single extra masked implant operation |
| CN1985365A (en) * | 2004-07-30 | 2007-06-20 | 飞思卡尔半导体公司 | CMOS with only a single implant |
| US20080179682A1 (en) * | 2007-01-31 | 2008-07-31 | Infineon Technologies Ag | Circuit layout for different performance and method |
| CN101523580A (en) * | 2006-09-29 | 2009-09-02 | Nxp股份有限公司 | A multi-transistor based non-volatile memory cell with dual threshold voltage |
| CN103325736A (en) * | 2012-03-19 | 2013-09-25 | 三星电子株式会社 | Method for fabricating fin type field effect transistor with fins of different widths |
| US20140377925A1 (en) * | 2013-06-20 | 2014-12-25 | International Business Machines Corporation | Selective laser anneal on semiconductor material |
-
2015
- 2015-04-22 CN CN201510198893.XA patent/CN104779169B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1423837A (en) * | 1999-11-18 | 2003-06-11 | 英特尔公司 | Method of fabrication dual threshold voltage N-channel and P-channel MOSFETS with a single extra masked implant operation |
| CN1985365A (en) * | 2004-07-30 | 2007-06-20 | 飞思卡尔半导体公司 | CMOS with only a single implant |
| CN101523580A (en) * | 2006-09-29 | 2009-09-02 | Nxp股份有限公司 | A multi-transistor based non-volatile memory cell with dual threshold voltage |
| US20080179682A1 (en) * | 2007-01-31 | 2008-07-31 | Infineon Technologies Ag | Circuit layout for different performance and method |
| CN103325736A (en) * | 2012-03-19 | 2013-09-25 | 三星电子株式会社 | Method for fabricating fin type field effect transistor with fins of different widths |
| US20140377925A1 (en) * | 2013-06-20 | 2014-12-25 | International Business Machines Corporation | Selective laser anneal on semiconductor material |
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| CN104779169B (en) | 2017-12-08 |
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Effective date of registration: 20180330 Address after: 201315 No. 1060, room 298, Kang Qiao East Road, Pudong New Area, Shanghai Patentee after: Shanghai Huali integrated circuit manufacturing Co. Ltd. Address before: 201210 Shanghai Gauss road in Pudong New Area Zhangjiang hi tech Park No. 568 Patentee before: Shanghai Hua Li Microelectronics Co., Ltd. |
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