US10985071B1 - Gate oxide forming process - Google Patents

Gate oxide forming process Download PDF

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US10985071B1
US10985071B1 US16/667,921 US201916667921A US10985071B1 US 10985071 B1 US10985071 B1 US 10985071B1 US 201916667921 A US201916667921 A US 201916667921A US 10985071 B1 US10985071 B1 US 10985071B1
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area
gate oxide
oxide layer
layer
substrate
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US20210134679A1 (en
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Yuan-Cheng Yang
Yi-Han SU
Sheng-Chen Chung
Chen-An Kuo
Chun-Lin Chen
Chiu-Te Lee
Chih-Chung Wang
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United Microelectronics Corp
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United Microelectronics Corp
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Assigned to UNITED MICROELECTRONICS CORP. reassignment UNITED MICROELECTRONICS CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, CHUN-LIN, CHUNG, SHENG-CHEN, KUO, CHEN-AN, LEE, CHIU-TE, SU, YI-HAN, WANG, CHIH-CHUNG, YANG, Yuan-cheng
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28229—Making the insulator by deposition of a layer, e.g. metal, metal compound or poysilicon, followed by transformation thereof into an insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer

Definitions

  • the present invention relates generally to a gate oxide forming process, and more specifically to a gate oxide forming process in different areas.
  • applied voltage to transistors in a high voltage component area is much higher than the applied voltage to transistors in a logic circuit area.
  • thicknesses of buffer layers or dielectric layers of the transistors in the high voltage component area should be larger than the thicknesses of buffer layers or dielectric layers of the transistors in the logic circuit area.
  • Fabricating transistors in the high voltage component area and in the logic circuit area includes the following steps.
  • a thick oxide layer suited for usage in transistors in the high voltage component area is formed on a substrate in the high voltage component area and in the logic circuit area.
  • the thick oxide layer in the logic circuit area is removed and a thinner oxide layer suited for usage in transistors in the logic circuit area is formed to replace the thick oxide layer.
  • a polysilicon layer is formed on the oxide layer in the two areas at the same time. Thereafter, the polysilicon layer, the thick oxide layer and the thinner oxide layer are sequentially patterned. Sequential transistor processes are then performed.
  • the present invention provides a gate oxide forming process, which integrates devices of two different voltage areas without extra thermal budget impact.
  • the present invention provides a gate oxide forming process including the following steps.
  • a substrate including a first area and a second area is provided.
  • a first oxide layer, a silicon containing cap layer and a second oxide layer on the substrate of the first area and the second area are sequentially and blanketly formed.
  • the silicon containing cap layer and the second oxide layer in the first area are removed.
  • An oxidation process is performed to oxidize the silicon containing cap layer and a gate oxide layer is therefore formed in the second area.
  • the present invention provides a gate oxide forming process, which sequentially and blanketly forms a first oxide layer, a silicon containing cap layer and a second oxide layer on a substrate of a first area and a second area; removes the silicon containing cap layer and the second oxide layer in the first area; and performs an oxidation process to oxidize the silicon containing cap layer and thus forms a gate oxide layer in the second area.
  • gate oxide layers with different thicknesses in the first area and the second area can be formed.
  • FIG. 1 schematically depicts a cross-sectional view of a gate oxide forming process according to an embodiment of the present invention.
  • FIG. 2 schematically depicts a cross-sectional view of a gate oxide forming process according to an embodiment of the present invention.
  • FIG. 3 schematically depicts a cross-sectional view of a gate oxide forming process according to an embodiment of the present invention.
  • FIG. 4 schematically depicts a cross-sectional view of a gate oxide forming process according to an embodiment of the present invention.
  • FIG. 5 schematically depicts a cross-sectional view of a gate oxide forming process according to an embodiment of the present invention.
  • FIG. 6 schematically depicts a cross-sectional view of a gate oxide forming process according to an embodiment of the present invention.
  • FIG. 7 schematically depicts a cross-sectional view of a gate oxide forming process according to an embodiment of the present invention.
  • FIG. 8 schematically depicts a cross-sectional view of a gate oxide forming process according to an embodiment of the present invention.
  • FIG. 9 schematically depicts a cross-sectional view of a gate oxide forming process according to an embodiment of the present invention.
  • FIGS. 1-9 schematically depict cross-sectional views of a gate oxide forming process according to an embodiment of the present invention.
  • a substrate 110 is provided.
  • the substrate 110 may be a semiconductor substrate such as a silicon substrate, a silicon containing substrate, a III-V group-on-silicon (such as GaN-on-silicon) substrate, a graphene-on-silicon substrate, a silicon-on-insulator (SOI) substrate or a substrate containing epitaxial layers etc.
  • the substrate 110 may include a first area A and a second area B, but it is not limited thereto.
  • the substrate 110 may further include other areas (not shown).
  • the first area A is a low voltage area while the second area B is a medium voltage area, so that the thickness of a gate oxide layer on the substrate 110 of the first area A is thinner than the thickness of a gate oxide layer on the substrate 110 of the second area B.
  • the method of the present invention described as follows can be applied in a bipolar-CMOS-DMOS (BCD) process or other processes of multiple voltage areas.
  • Isolation structures 30 may be formed in the substrate 110 .
  • the isolation structures 30 may be shallow trench isolation structures, which may be formed by a shallow trench isolation process, but it is not limited thereto.
  • Methods of forming the isolation structures 30 may include the following.
  • a first oxide layer (not shown) and a nitride layer (not shown) may be sequentially formed on the substrate 110 of the first area A and the second area B.
  • the first oxide layer (not shown) and the nitride layer (not shown) may be deposited by atomic layer deposition (ALD) processes or chemical vapor deposition (CVD) processes, but it is not restricted thereto.
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • the first oxide layer (not shown), the nitride layer (not shown) and the substrate 110 are etched to form recesses R in a first oxide layer 10 , a nitride layer 20 and the substrate 110 .
  • the isolation structures 30 fill in the recesses R.
  • the first oxide layer 10 is a pad oxide layer for forming the isolation structures 30 .
  • the first oxide layer 10 may be formed blanketly after the isolation structures 30 are carried out.
  • the thickness of the first oxide layer 10 is 110 angstroms.
  • a silicon containing cap layer 120 is formed on the substrate 110 of the first area A and the second area B blanketly.
  • the silicon containing cap layer 120 may include a silicon layer, a polysilicon layer or etc.
  • the silicon containing cap layer 120 may be deposited by an atomic layer deposition (ALD) processes or a chemical vapor deposition (CVD) process, but it is not restricted thereto.
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • the thickness of the silicon containing cap layer 120 is 10-20 angstroms.
  • a second oxide layer 130 is formed on the silicon containing cap layer 120 of the first area A and the second area B blanketly.
  • the second oxide layer 130 may be deposited by an atomic layer deposition (ALD) processes or a chemical vapor deposition (CVD) process, but it is not restricted thereto.
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • the thickness of the second oxide layer 130 is 15-20 angstroms.
  • the second oxide layer 130 and the silicon containing cap layer 120 are removed only in the first area A, and the second oxide layer 130 and the silicon containing cap layer 120 are reserved in the second area B.
  • a photoresist P may be formed by coating and then patterning to cover the second oxide layer 130 of the second area B but exposes the second oxide layer 130 of the first area A.
  • the silicon containing cap layer 120 and the second oxide layer 130 in the first area A are removed, and thus a silicon containing cap layer 120 a and a second oxide layer 130 a only in the second area B are formed, and the first oxide layer 10 in the first area A is exposed, as shown in FIG. 6 .
  • the photoresist P is then removed.
  • a first well 42 is formed on the substrate 110 of the first area A
  • a second well 44 is formed on the substrate 110 of the second area B.
  • the first well 42 and the second well 44 may be formed on the substrate 110 of the first area A and the second area B respectively by different implant processes. Due to the first oxide layer 10 covering the substrate 110 of the first area A and the first oxide layer 10 , the silicon containing cap layer 120 a and the second oxide layer 130 a covering the substrate 110 of the second area B, the substrate 110 can be prevented from damage and the performance of the first well 42 and the second well 44 is improved. Then, a thermal process Q 1 may be performed to active the first well 42 and the second well 44 .
  • the thermal process Q 1 may be a rapid thermal processing (RTP) process, but it is not limited thereto.
  • the first oxide layer 10 in the first area A is removed after the first well 42 and the second well 44 are formed, thereby a first oxide layer 10 a only on the substrate 110 of the second area B being formed and the substrate 110 in the first area A being exposed, as shown in FIG. 7 .
  • a first gate oxide layer 140 is formed on the substrate 110 of the first area A and a gate oxide layer K 1 is formed on the substrate 110 of the second area B.
  • an oxidation process Q 2 is performed to not only form the first gate oxide layer 140 on the substrate 110 of the first area A, but also oxidize the silicon containing cap layer 120 a on the substrate 110 of the second area B, therefore forming the gate oxide layer K 1 in the second area B, wherein the gate oxide layer K 1 is constituted by the first oxide layer 10 in the second area B, a silicon oxide layer 120 b transferring from the silicon containing cap layer 120 a and the second oxide layer 130 a .
  • the oxidation process is a rapid thermal oxide (RTO) process, but it is not limited thereto.
  • RTO rapid thermal oxide
  • the first area A is a low voltage area while the second area B is a medium voltage area in this case, a thickness t 1 of the first gate oxide layer 140 on the substrate 110 of the first area A is thinner than a thickness t 2 of the gate oxide layer K 1 on the substrate 110 of the second area B.
  • only one photoresist P is applied and one oxidation process Q 2 is processed to form the first gate oxide layer 140 in first area A and the gate oxide layer K 1 in the second area B.
  • devices in the second area B (meaning the medium voltage area in this case) can be integrated with devices in the first area A (meaning the low voltage area in this case) without extra thermal budget impact, hence keeping the performance of the devices in the low voltage area.
  • the thickness t 2 of the gate oxide layer K 1 is tunable, and the first oxide layer 10 in the second area B can be prevented from damage because of the coverage of the silicon containing cap layer 120 a .
  • the uniformity of the breakdown voltage of a formed device can be improved.
  • the first area A may include an input/output area A 1 and a logic area A 2 , as shown in FIG. 9 .
  • the first gate oxide layer 140 of FIG. 8 is an input/output gate oxide layer, so that the first gate oxide layer 140 in the logic area A 2 is removed to expose the substrate 110 while a first gate oxide layer 140 a in the input/output area A 1 is reserved. Then, a second gate oxide layer 140 b is formed on the substrate 110 of the logic area A 2 . A thickness t 3 of the second gate oxide layer 140 b is thinner than the thickness t 1 of the first gate oxide layer 140 a.
  • polysilicon gates may be disposed over the gate oxide layer Kl in the second area B, the first gate oxide layer 140 a in the input/output area A 1 and the second gate oxide layer 140 b in the logic area A 2 at the same time or respectively.
  • the present invention provides a gate oxide forming process, which sequentially and blanketly forms a first oxide layer, a silicon containing cap layer and a second oxide layer on a substrate of a first area and a second area; removes the silicon containing cap layer and the second oxide layer in the first area; and performs an oxidation process to oxidize the silicon containing cap layer and therefore forms a gate oxide layer in the second area.
  • gate oxide layers with different thicknesses in the first area and the second area can be formed.
  • the first oxide layer in the first area may be removed before the oxidation process is performed, so that a gate oxide layer on the substrate of the first area can be formed while the oxidation process is performed.
  • a first well may be formed in the substrate of the first area and a second well may be formed in the substrate of the second area before the first oxide layer is removed, thereby the substrate can being prevented from damage while implanting.

Abstract

A gate oxide forming process includes the following steps. A substrate including a first area and a second area is provided. A first oxide layer, a silicon containing cap layer and a second oxide layer on the substrate of the first area and the second area are sequentially and blanketly formed. The silicon containing cap layer and the second oxide layer in the first area are removed. An oxidation process is performed to oxidize the silicon containing cap layer and a gate oxide layer is formed in the second area.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates generally to a gate oxide forming process, and more specifically to a gate oxide forming process in different areas.
2. Description of the Prior Art
In integrated circuits, applied voltage to transistors in a high voltage component area is much higher than the applied voltage to transistors in a logic circuit area. Thus, thicknesses of buffer layers or dielectric layers of the transistors in the high voltage component area should be larger than the thicknesses of buffer layers or dielectric layers of the transistors in the logic circuit area.
Fabricating transistors in the high voltage component area and in the logic circuit area includes the following steps. A thick oxide layer suited for usage in transistors in the high voltage component area is formed on a substrate in the high voltage component area and in the logic circuit area. Then, the thick oxide layer in the logic circuit area is removed and a thinner oxide layer suited for usage in transistors in the logic circuit area is formed to replace the thick oxide layer. After the thick oxide layer is formed in the high voltage component area and the thinner oxide layer is formed in the logic circuit area, a polysilicon layer is formed on the oxide layer in the two areas at the same time. Thereafter, the polysilicon layer, the thick oxide layer and the thinner oxide layer are sequentially patterned. Sequential transistor processes are then performed.
SUMMARY OF THE INVENTION
The present invention provides a gate oxide forming process, which integrates devices of two different voltage areas without extra thermal budget impact.
The present invention provides a gate oxide forming process including the following steps. A substrate including a first area and a second area is provided. A first oxide layer, a silicon containing cap layer and a second oxide layer on the substrate of the first area and the second area are sequentially and blanketly formed. The silicon containing cap layer and the second oxide layer in the first area are removed. An oxidation process is performed to oxidize the silicon containing cap layer and a gate oxide layer is therefore formed in the second area.
According to the above, the present invention provides a gate oxide forming process, which sequentially and blanketly forms a first oxide layer, a silicon containing cap layer and a second oxide layer on a substrate of a first area and a second area; removes the silicon containing cap layer and the second oxide layer in the first area; and performs an oxidation process to oxidize the silicon containing cap layer and thus forms a gate oxide layer in the second area. Thereby, gate oxide layers with different thicknesses in the first area and the second area can be formed. By using the method of the present invention, devices in the second area can be integrated with devices in the first area without extra thermal budget impact, and the uniformity of the breakdown voltage of a formed device can be improved.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 schematically depicts a cross-sectional view of a gate oxide forming process according to an embodiment of the present invention.
FIG. 2 schematically depicts a cross-sectional view of a gate oxide forming process according to an embodiment of the present invention.
FIG. 3 schematically depicts a cross-sectional view of a gate oxide forming process according to an embodiment of the present invention.
FIG. 4 schematically depicts a cross-sectional view of a gate oxide forming process according to an embodiment of the present invention.
FIG. 5 schematically depicts a cross-sectional view of a gate oxide forming process according to an embodiment of the present invention.
FIG. 6 schematically depicts a cross-sectional view of a gate oxide forming process according to an embodiment of the present invention.
FIG. 7 schematically depicts a cross-sectional view of a gate oxide forming process according to an embodiment of the present invention.
FIG. 8 schematically depicts a cross-sectional view of a gate oxide forming process according to an embodiment of the present invention.
FIG. 9 schematically depicts a cross-sectional view of a gate oxide forming process according to an embodiment of the present invention.
 DETAILED DESCRIPTION
FIGS. 1-9 schematically depict cross-sectional views of a gate oxide forming process according to an embodiment of the present invention. As shown in FIG. 1, a substrate 110 is provided. The substrate 110 may be a semiconductor substrate such as a silicon substrate, a silicon containing substrate, a III-V group-on-silicon (such as GaN-on-silicon) substrate, a graphene-on-silicon substrate, a silicon-on-insulator (SOI) substrate or a substrate containing epitaxial layers etc. The substrate 110 may include a first area A and a second area B, but it is not limited thereto. The substrate 110 may further include other areas (not shown). In this embodiment, the first area A is a low voltage area while the second area B is a medium voltage area, so that the thickness of a gate oxide layer on the substrate 110 of the first area A is thinner than the thickness of a gate oxide layer on the substrate 110 of the second area B. The method of the present invention described as follows can be applied in a bipolar-CMOS-DMOS (BCD) process or other processes of multiple voltage areas.
Isolation structures 30 may be formed in the substrate 110. The isolation structures 30 may be shallow trench isolation structures, which may be formed by a shallow trench isolation process, but it is not limited thereto. Methods of forming the isolation structures 30 may include the following. A first oxide layer (not shown) and a nitride layer (not shown) may be sequentially formed on the substrate 110 of the first area A and the second area B. The first oxide layer (not shown) and the nitride layer (not shown) may be deposited by atomic layer deposition (ALD) processes or chemical vapor deposition (CVD) processes, but it is not restricted thereto. The first oxide layer (not shown), the nitride layer (not shown) and the substrate 110 are etched to form recesses R in a first oxide layer 10, a nitride layer 20 and the substrate 110. The isolation structures 30 fill in the recesses R.
Then, the nitride layer 20 is removed, as shown in FIG. 2. In this embodiment, the first oxide layer 10 is a pad oxide layer for forming the isolation structures 30. In other embodiments, the first oxide layer 10 may be formed blanketly after the isolation structures 30 are carried out. For example, the thickness of the first oxide layer 10 is 110 angstroms.
As shown in FIG. 3, a silicon containing cap layer 120 is formed on the substrate 110 of the first area A and the second area B blanketly. The silicon containing cap layer 120 may include a silicon layer, a polysilicon layer or etc. The silicon containing cap layer 120 may be deposited by an atomic layer deposition (ALD) processes or a chemical vapor deposition (CVD) process, but it is not restricted thereto. For example, the thickness of the silicon containing cap layer 120 is 10-20 angstroms.
As shown in FIG. 4, a second oxide layer 130 is formed on the silicon containing cap layer 120 of the first area A and the second area B blanketly. The second oxide layer 130 may be deposited by an atomic layer deposition (ALD) processes or a chemical vapor deposition (CVD) process, but it is not restricted thereto. For example, the thickness of the second oxide layer 130 is 15-20 angstroms.
Please refer to FIGS. 5-6, the second oxide layer 130 and the silicon containing cap layer 120 are removed only in the first area A, and the second oxide layer 130 and the silicon containing cap layer 120 are reserved in the second area B. As shown in FIG. 5, a photoresist P may be formed by coating and then patterning to cover the second oxide layer 130 of the second area B but exposes the second oxide layer 130 of the first area A. Thereafter, the silicon containing cap layer 120 and the second oxide layer 130 in the first area A are removed, and thus a silicon containing cap layer 120 a and a second oxide layer 130 a only in the second area B are formed, and the first oxide layer 10 in the first area A is exposed, as shown in FIG. 6. The photoresist P is then removed.
A first well 42 is formed on the substrate 110 of the first area A, and a second well 44 is formed on the substrate 110 of the second area B. The first well 42 and the second well 44 may be formed on the substrate 110 of the first area A and the second area B respectively by different implant processes. Due to the first oxide layer 10 covering the substrate 110 of the first area A and the first oxide layer 10, the silicon containing cap layer 120 a and the second oxide layer 130 a covering the substrate 110 of the second area B, the substrate 110 can be prevented from damage and the performance of the first well 42 and the second well 44 is improved. Then, a thermal process Q1 may be performed to active the first well 42 and the second well 44. The thermal process Q1 may be a rapid thermal processing (RTP) process, but it is not limited thereto.
Thereafter, the first oxide layer 10 in the first area A is removed after the first well 42 and the second well 44 are formed, thereby a first oxide layer 10 a only on the substrate 110 of the second area B being formed and the substrate 110 in the first area A being exposed, as shown in FIG. 7.
Please refer to FIGS. 7-8, a first gate oxide layer 140 is formed on the substrate 110 of the first area A and a gate oxide layer K1 is formed on the substrate 110 of the second area B. In this embodiment, an oxidation process Q2 is performed to not only form the first gate oxide layer 140 on the substrate 110 of the first area A, but also oxidize the silicon containing cap layer 120 a on the substrate 110 of the second area B, therefore forming the gate oxide layer K1 in the second area B, wherein the gate oxide layer K1 is constituted by the first oxide layer 10 in the second area B, a silicon oxide layer 120 b transferring from the silicon containing cap layer 120 a and the second oxide layer 130 a. Preferably, the oxidation process is a rapid thermal oxide (RTO) process, but it is not limited thereto. Since the first area A is a low voltage area while the second area B is a medium voltage area in this case, a thickness t1 of the first gate oxide layer 140 on the substrate 110 of the first area A is thinner than a thickness t2 of the gate oxide layer K1 on the substrate 110 of the second area B. By doing this, only one photoresist P is applied and one oxidation process Q2 is processed to form the first gate oxide layer 140 in first area A and the gate oxide layer K1 in the second area B. Thus, devices in the second area B (meaning the medium voltage area in this case) can be integrated with devices in the first area A (meaning the low voltage area in this case) without extra thermal budget impact, hence keeping the performance of the devices in the low voltage area. Besides, the thickness t2 of the gate oxide layer K1 is tunable, and the first oxide layer 10 in the second area B can be prevented from damage because of the coverage of the silicon containing cap layer 120 a. As a result, the uniformity of the breakdown voltage of a formed device can be improved.
In one case, the first area A may include an input/output area A1 and a logic area A2, as shown in FIG. 9. The first gate oxide layer 140 of FIG. 8 is an input/output gate oxide layer, so that the first gate oxide layer 140 in the logic area A2 is removed to expose the substrate 110 while a first gate oxide layer 140 a in the input/output area A1 is reserved. Then, a second gate oxide layer 140 b is formed on the substrate 110 of the logic area A2. A thickness t3 of the second gate oxide layer 140 b is thinner than the thickness t1 of the first gate oxide layer 140 a.
In later processes, polysilicon gates may be disposed over the gate oxide layer Kl in the second area B, the first gate oxide layer 140 a in the input/output area A1 and the second gate oxide layer 140 b in the logic area A2 at the same time or respectively.
To summarize, the present invention provides a gate oxide forming process, which sequentially and blanketly forms a first oxide layer, a silicon containing cap layer and a second oxide layer on a substrate of a first area and a second area; removes the silicon containing cap layer and the second oxide layer in the first area; and performs an oxidation process to oxidize the silicon containing cap layer and therefore forms a gate oxide layer in the second area. Thereby, gate oxide layers with different thicknesses in the first area and the second area can be formed. By using the method of the present invention, devices in the second area can be integrated with devices in the first area A without extra thermal budget impact, the performance of the devices in the low voltage area can be kept, and the uniformity of the breakdown voltage of a formed device can be improved.
Moreover, the first oxide layer in the first area may be removed before the oxidation process is performed, so that a gate oxide layer on the substrate of the first area can be formed while the oxidation process is performed. A first well may be formed in the substrate of the first area and a second well may be formed in the substrate of the second area before the first oxide layer is removed, thereby the substrate can being prevented from damage while implanting.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (14)

What is claimed is:
1. A gate oxide forming process, comprising:
providing a substrate comprising a first area and a second area;
sequentially and blanketly forming a first oxide layer, a silicon containing cap layer and a second oxide layer on the substrate of the first area and the second area;
removing the silicon containing cap layer and the second oxide layer in the first area; and
performing an oxidation process to oxidize the silicon containing cap layer completely and thus forming a gate oxide layer in the second area.
2. The gate oxide forming process according to claim 1, wherein the first area is a low voltage area while the second area is a medium voltage area.
3. The gate oxide forming process according to claim 1, wherein the silicon containing cap layer comprises a silicon layer or a polysilicon layer.
4. The gate oxide forming process according to claim 1, wherein the oxidation process comprises a rapid thermal oxide process.
5. The gate oxide forming process according to claim 1, wherein the steps of removing the silicon containing cap layer and the second oxide layer in the first area comprise:
forming a photoresist covering the second oxide layer of the second area but exposing the second oxide layer of the first area; and
removing the silicon containing cap layer and the second oxide layer in the first area; and
removing the photoresist.
6. The gate oxide forming process according to claim 1, further comprising:
forming a first well in the substrate of the first area, and a second well in the substrate of the second area before the oxidation process is performed.
7. The gate oxide forming process according to claim 6, wherein the first well and the second well are both formed by performing an implantation process and then a thermal process.
8. The gate oxide forming process according to claim 7, wherein the thermal process comprises a rapid thermal processing (RTP) process.
9. The gate oxide forming process according to claim 6, further comprising:
removing the first oxide layer in the first area after the first well and the second well are formed; and
forming a first gate oxide layer on the substrate of the first area.
10. The gate oxide forming process according to claim 9, wherein the first gate oxide layer is formed by performing the oxidation process.
11. The gate oxide forming process according to claim 10, wherein the first gate oxide layer is an input/output gate oxide layer in an input/output area.
12. The gate oxide forming process according to claim 11, further comprising:
forming a second gate oxide layer in a logic area.
13. The gate oxide forming process according to claim 1,
further comprising:
forming an isolation structure in the substrate before the silicon containing cap layer and the second oxide layer are formed.
14. The gate oxide forming process according to claim 13, wherein the steps of forming the isolation structure comprise:
sequentially forming the first oxide layer and a nitride layer on the substrate;
etching the first oxide layer, the nitride layer and the substrate to form a recess;
forming the isolation structure in the recess; and
removing the nitride layer.
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