CN114496921A - Method for manufacturing semiconductor device and semiconductor device - Google Patents
Method for manufacturing semiconductor device and semiconductor device Download PDFInfo
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- CN114496921A CN114496921A CN202210119361.2A CN202210119361A CN114496921A CN 114496921 A CN114496921 A CN 114496921A CN 202210119361 A CN202210119361 A CN 202210119361A CN 114496921 A CN114496921 A CN 114496921A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 68
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 238000000034 method Methods 0.000 title claims description 26
- 239000000758 substrate Substances 0.000 claims abstract description 41
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
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- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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Abstract
The application provides a manufacturing method of a semiconductor device and the semiconductor device, wherein the manufacturing method of the semiconductor device comprises the following steps: providing a substrate, wherein the substrate comprises a high-voltage device area and a low-voltage device area; forming a first grid electrode on the high-voltage device area and forming a second grid electrode on the low-voltage device area; and forming dielectric layers at least on the exposed surface of the first grid electrode and the exposed surface of the second grid electrode, wherein the thickness of the dielectric layer on the side wall of the first grid electrode is a first thickness, the thickness of the dielectric layer on the side wall of the second grid electrode is a second thickness, and the first thickness is larger than the second thickness. The manufacturing method of the semiconductor device solves the technical problem that the performance of the semiconductor device is degraded or damaged due to the fact that the hot carrier injection effect of the high-voltage device area is large.
Description
Technical Field
The present disclosure relates to the field of semiconductors, and in particular, to a method for manufacturing a semiconductor device and a semiconductor device.
Background
In the prior art, gate side walls of a High Voltage (HV) device region and a Low Voltage (LV) device region in a semiconductor device are both of an oxide layer-nitride layer structure, and the gate side walls are smaller along with the shrinkage of the critical dimension of the semiconductor device, which enhances the Hot Carrier Injection Effect (HCI) of the High Voltage device region, so that the performance of the semiconductor device is degraded or damaged.
The above information disclosed in this background section is only for enhancement of understanding of the background of the technology described herein and, therefore, certain information may be included in the background that does not form the prior art that is already known in this country to a person of ordinary skill in the art.
Disclosure of Invention
The present disclosure provides a method for manufacturing a semiconductor device and a semiconductor device, so as to solve the problem that HCI in a high voltage device region affects performance of the semiconductor device in the prior art.
In order to achieve the above object, according to an aspect of the present application, there is provided a method of manufacturing a semiconductor device, including: providing a substrate, wherein the substrate comprises a high-voltage device area and a low-voltage device area; forming a first grid electrode on the high-voltage device area, and forming a second grid electrode on the low-voltage device area; and forming dielectric layers at least on the exposed surface of the first grid electrode and the exposed surface of the second grid electrode, wherein the thickness of the dielectric layer on the side wall of the first grid electrode is a first thickness, the thickness of the dielectric layer on the side wall of the second grid electrode is a second thickness, and the first thickness is greater than the second thickness.
Optionally, forming a dielectric layer at least on the exposed surface of the first gate and the exposed surface of the second gate includes: sequentially superposing a first dielectric sublayer, a second dielectric sublayer and a third dielectric sublayer on the exposed surfaces of the substrate, the first grid and the second grid; removing part of the third dielectric sublayer, and reserving the third dielectric sublayer on the side wall of the first grid; and removing part of the second dielectric sublayer, and remaining the second dielectric sublayer on the side wall of the first gate and on the side wall of the second gate, wherein the first dielectric sublayer, the remaining second dielectric sublayer and the remaining third dielectric sublayer constitute the dielectric layer.
Optionally, removing a portion of the third dielectric sublayer includes: injecting a predetermined element into the third dielectric sublayer on the surface of the second gate, wherein the third dielectric sublayer after the predetermined element is injected forms a dielectric loose layer; and removing the dielectric loose layer, the third dielectric sub-layer on the surface of the substrate and the third dielectric sub-layer on the surface of the first grid far away from the substrate.
Optionally, implanting a predetermined element into the third dielectric sublayer on the second gate surface comprises: forming a sacrificial layer on an exposed surface of the third dielectric sublayer located on the first gate surface; injecting the predetermined element into the third medium sub-layer which is not shielded by the sacrificial layer to obtain the medium loose layer; and removing the sacrificial layer.
Optionally, the first dielectric sublayer includes silicon oxide, the second dielectric sublayer includes silicon nitride, and the third dielectric sublayer includes silicon oxide.
Optionally, the predetermined element is an inert element.
According to another aspect of the present application, there is also provided a semiconductor device including: a substrate including a high voltage device region and a low voltage device region; the first grid electrode is positioned on the high-voltage device area, and the second grid electrode is positioned on the low-voltage device area; and the dielectric layer at least covers the first grid electrode and the second grid electrode, the thickness of the dielectric layer on the side wall of the first grid electrode is a first thickness, the thickness of the dielectric layer on the side wall of the second grid electrode is a second thickness, and the first thickness is larger than the second thickness.
Optionally, the dielectric layer includes: the first dielectric sublayer is positioned on the side wall of the first grid electrode and the side wall of the second grid electrode; the second dielectric sublayer is positioned on the surface of the side wall of the first dielectric sublayer, which is far away from the first grid electrode, and the surface of the side wall of the first dielectric sublayer, which is far away from the second grid electrode; and the third dielectric sublayer is positioned on the surface of the side wall of the second dielectric sublayer, which is far away from the first grid electrode.
Optionally, the material of the first dielectric sublayer includes silicon oxide, the material of the second dielectric sublayer includes silicon nitride, and the material of the third dielectric sublayer includes silicon oxide.
Optionally, the semiconductor device further comprises: and the gate oxide layer comprises a high-voltage gate oxide layer and a low-voltage gate oxide layer, the high-voltage gate oxide layer is positioned between the high-voltage device area and the first grid electrode, and the low-voltage gate oxide layer is positioned between the low-voltage device area and the second grid electrode.
Optionally, the thickness of the high voltage gate oxide layer is greater than the thickness of the low voltage gate oxide layer.
According to the technical scheme, in the manufacturing method of the semiconductor device, a substrate comprising a high-voltage device area and a low-voltage device area is provided firstly, then a first grid electrode and a second grid electrode are formed on the high-voltage device area and the low-voltage device area respectively, finally, a dielectric layer is formed on exposed surfaces of the first grid electrode and the second grid electrode at least, and the thickness of the dielectric layer on the side wall of the first grid electrode is larger than that of the dielectric layer on the side wall of the second grid electrode, namely the thickness of the side wall of the first grid electrode on the high-voltage device area is larger than that of the side wall of the low-voltage device area. According to the manufacturing method, the thickness of the side wall of the upper grid of the high-voltage device area is increased, so that the hot carrier injection effect of the high-voltage device area is small, the damage of the hot carrier injection effect to the semiconductor device is relieved, and the problem that the performance of the semiconductor device is degraded or damaged due to the fact that the hot carrier injection effect of the high-voltage device area is large in the prior art is solved. Meanwhile, because the high-voltage device area and the low-voltage device area are different in sensitivity degree to HCI, the thickness of the side wall of the grid electrode on the low-voltage device area is smaller than that of the side wall of the grid electrode on the high-voltage device area, so that the HCI of the high-voltage device area is smaller, and the performance of the device in the low-voltage device area is basically not influenced.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
fig. 1 shows a schematic flow chart of a method of fabricating a semiconductor device according to an embodiment of the present application;
fig. 2 to 5 show schematic structural diagrams formed after different process steps according to a method for manufacturing a semiconductor device of the present application.
Wherein the figures include the following reference numerals:
100. a shallow trench isolation structure; 101. a substrate; 102. a low voltage gate oxide layer; 103. a first dielectric sublayer; 104. a second dielectric sublayer; 105. a third dielectric sublayer; 106. a high voltage gate oxide layer; 201. a first gate electrode; 202. a second gate electrode; 301. a high voltage device region; 302. a low voltage device region; 401. a sacrificial layer.
Detailed Description
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the application described herein may be used. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As described in the background, the present application provides a method for manufacturing a semiconductor device and a semiconductor device, so as to solve the problem that HCI in a high voltage device region affects the performance of the semiconductor device in the prior art.
According to an embodiment of the present application, a method of fabricating a semiconductor device is provided. Fig. 1 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present application, which includes the steps of, as shown in fig. 1 to 5:
step S101, providing a substrate 101, wherein the substrate comprises a high-voltage device area 301 and a low-voltage device area 302;
step S102, forming a first gate 201 on the high voltage device region 301, and forming a second gate 202 on the low voltage device region 302;
step S103, forming a dielectric layer at least on the exposed surface of the first gate 201 and the exposed surface of the second gate 202, where the thickness of the dielectric layer on the sidewall of the first gate 201 is a first thickness, the thickness of the dielectric layer on the sidewall of the second gate 202 is a second thickness, and the first thickness is greater than the second thickness, so as to obtain the structure shown in fig. 5.
In the manufacturing method of the semiconductor device, a substrate comprising a high-voltage device area and a low-voltage device area is provided firstly, then a first grid electrode and a second grid electrode are formed on the high-voltage device area and the low-voltage device area respectively, finally, a dielectric layer is formed on the exposed surfaces of the first grid electrode and the second grid electrode at least, the thickness of the dielectric layer on the side wall of the first grid electrode is larger than that of the dielectric layer on the side wall of the second grid electrode, namely, the thickness of the side wall of the first grid electrode on the high-voltage device area is larger than that of the side wall of the low-voltage device area. According to the manufacturing method, the thickness of the side wall of the grid electrode on the high-voltage device area is increased, so that the hot carrier injection effect of the high-voltage device area is small, the damage of the hot carrier injection effect to the semiconductor device is relieved, and the problem that the performance of the semiconductor device is degraded or damaged due to the fact that the hot carrier injection effect of the high-voltage device area is large in the prior art is solved. Meanwhile, because the high-voltage device area and the low-voltage device area are different in sensitivity degree to HCI, the thickness of the side wall of the grid electrode on the low-voltage device area is smaller than that of the side wall of the grid electrode on the high-voltage device area, so that the HCI of the high-voltage device area is smaller, and the performance of the device in the low-voltage device area is basically not influenced.
Specifically, the second thickness is the same as the sidewall thickness of the gate on the low-voltage device region in the prior art, and the first thickness is greater than the second thickness, that is, the sidewall thickness of the gate on the high-voltage device region is increased under the condition that the sidewall thickness of the gate on the low-voltage device region is not changed, so that the damage of the HCI of the high-voltage device region to the semiconductor device is relieved under the condition that the device performance of the low-voltage region is not attenuated.
It should be noted that each step in the above embodiments of forming the substrate can be implemented in a feasible manner in the prior art. The substrate in the above-mentioned base can be selected according to the actual requirements of the device, and may include a Silicon substrate, a germanium substrate, a Silicon germanium complete substrate, an SOI (Silicon On Insulator) substrate, or a GOI (germanium On Insulator) substrate. In other embodiments, the substrate may also be a substrate including other element semiconductors or compound semiconductors, such as GaAs, InP, SiC, or the like, may also be a stacked structure, such as Si/SiGe, or the like, and may also be another epitaxial structure, such as SGOI (silicon germanium on insulator) or the like. Of course, it may also be other substrates feasible in the art.
In practical applications, the high voltage device region is used to form a high voltage device, and the low voltage device region is used to form a low voltage device.
In one embodiment, as shown in fig. 2 to 5, a shallow trench isolation structure 100 is disposed between the low voltage device region 302 and the high voltage device region 301. The shallow trench isolation structure is used for defining an active region or used for isolation among devices, so that the devices cannot be communicated to cause a short circuit problem.
According to another specific embodiment of the present application, forming a dielectric layer at least on the exposed surface of the first gate and on the exposed surface of the second gate includes: as shown in fig. 2, a first dielectric sub-layer 103, a second dielectric sub-layer 104 and a third dielectric sub-layer 105 are sequentially stacked on exposed surfaces of the substrate 101, the first gate 201 and the second gate 202; removing a portion of the third dielectric sublayer 105, and leaving the third dielectric sublayer 105 on the sidewall of the first gate 201 to obtain the structure shown in fig. 4; removing part of the second dielectric sublayer 104, and leaving the second dielectric sublayer 104 on the sidewall of the first gate 201 and the sidewall of the second gate 202, wherein the first dielectric sublayer 103, the remaining second dielectric sublayer 104, and the remaining third dielectric sublayer 105 form the dielectric layer, so as to obtain the structure shown in fig. 5. Compared with the prior art that two dielectric layers are arranged on the side wall of the low-voltage device area and the side wall of the high-voltage device area, the two dielectric sub-layers on the side wall of the low-voltage device area are ensured, the two dielectric sub-layers on the side wall of the high-voltage device area are increased to three layers from two layers, and the hot carrier injection effect of the high-voltage device area is improved, so that the damage of the hot carrier injection effect to a semiconductor device is further ensured to be relieved, the original performance of the low-voltage device area is kept, the saturated drain current of the low-voltage device area is further ensured to be smaller, and the response speed of the low-voltage device area is higher.
In practical applications, the first, second and third dielectric sublayers may be made of materials available in the prior art. In a specific embodiment, the first dielectric sublayer includes silicon oxide, the second dielectric sublayer includes silicon nitride, and the third dielectric sublayer includes silicon oxide. In a more specific embodiment, the first dielectric sublayer is silicon oxide, the second dielectric sublayer is silicon nitride, and the third dielectric sublayer is silicon oxide.
According to another specific embodiment of the present application, removing a portion of the third dielectric sublayer includes: injecting a predetermined element into the third dielectric sublayer on the surface of the second gate, and forming a dielectric loose layer by the third dielectric sublayer after the predetermined element is injected; and removing the dielectric loose layer, the third dielectric sublayer positioned on the surface of the substrate and the third dielectric sublayer positioned on the surface of the first grid electrode far away from the substrate. The oxide etching selectivity of the third dielectric sublayer on the surface of the second grid electrode is changed by injecting a predetermined element into the third dielectric sublayer on the surface of the second grid electrode, so that the third dielectric sublayer and the dielectric loose layer on the surface, far away from the substrate, of the first grid electrode are only removed in the removing step, and the third dielectric sublayer on the side wall of the first grid electrode is reserved, so that the thickness of the side wall of the high-voltage device area is further ensured to be thicker, the hot carrier injection effect of the manufactured semiconductor device is further ensured to be smaller, and meanwhile, compared with the prior art, the thickness of the side wall of the low-voltage device area is further ensured to be unchanged, so that the saturated drain current of the low-voltage device area is further ensured to be smaller, and the response speed of the low-voltage device area is faster.
It should be noted that the technical means for removing the third dielectric sub-layer on the first predetermined surface is not limited to the above-mentioned process, and those skilled in the art can also implement other feasible manners in the prior art.
In a specific embodiment, the predetermined element is an inert element, such as nitrogen, argon, or the like.
In order to easily obtain the intermediate structure, according to another specific embodiment of the present application, as shown in fig. 2 and 3, the implanting a predetermined element into the third dielectric sublayer 105 on the surface of the second gate 202 includes: forming a sacrificial layer 401 on an exposed surface of the third dielectric sublayer 105 on the surface of the first gate 201; implanting the predetermined element into the third dielectric sublayer 105 that is not covered by the sacrificial layer to obtain the dielectric porous layer; the sacrificial layer 401 is removed. The third dielectric layer on the surface of the first grid electrode is shielded by the sacrificial layer, so that the lattice structure of the third dielectric layer at the position can be prevented from being damaged, and the dielectric loose layer can be conveniently and easily removed subsequently.
In a specific embodiment, the sacrificial layer is a photoresist layer. There are many methods for forming the photoresist layer described above, and those skilled in the art can select an appropriate method for forming the photoresist layer described above according to actual circumstances.
In a specific embodiment, after providing the substrate, the method further includes, before forming the second gate on the low-voltage device region, forming a first gate on the high-voltage device region: as shown in fig. 2 to 5, the gate oxide layer is formed on the substrate, and includes a high voltage gate oxide layer 106 and a low voltage gate oxide layer 102, the high voltage gate oxide layer 106 is located on a surface of the high voltage device region 301, and the low voltage gate oxide layer 102 is located on a surface of the low voltage device region 302. The thickness of the high-voltage gate oxide layer is larger than that of the low-voltage gate oxide layer, the thickness of the high-voltage gate oxide layer is larger, and the larger thickness enables the high-voltage device area to have stronger pressure-bearing capacity.
The material of the high-voltage gate oxide layer and the material of the low-voltage gate oxide layer both comprise silicon oxide. In a more specific embodiment, the material of the high voltage gate oxide layer and the material of the low voltage gate oxide layer are both silicon oxide.
These structural layers described above may be formed via one or more of Molecular Beam Epitaxy (MBE), Metal Organic Chemical Vapor Deposition (MOCVD), Metal Organic Vapor Phase Epitaxy (MOVPE), Hydride Vapor Phase Epitaxy (HVPE), and/or other well-known crystal growth processes.
It should be noted that, in the above embodiments of the present application, the reasons for maintaining the device performance of the low-voltage device region without degradation include the following: the lattice structure of the third dielectric sublayer at the side wall of the second gate is damaged through ion implantation to be loosened, and the loosened structure is etched at a higher speed under the same etching condition, so that the loosened third dielectric sublayer is removed when most of the third dielectric sublayer at the side wall of the first gate still remains in the subsequent etching process. Therefore, the thickness of the dielectric layer on the side wall of the second grid electrode cannot be increased, so that when the source and the drain are formed by subsequent ion implantation, the range of an ion implantation area shielded by the dielectric layer is smaller, the space between the formed source and drain cannot be increased, and the response speed of the device cannot be slowed down. Reasons for improving the hot carrier injection effect of the high-voltage device region include the following: the thickness of the dielectric layer on the side wall of the first grid electrode on the high-voltage device area is thick, so that when high-concentration ions are implanted subsequently, an LDD area can be formed between a high-concentration source drain electrode and the grid electrode through the side wall of the high-voltage device area, the source drain electrode distance of the MOS transistor can be accurately defined, and the problem that the source drain electrode and the drain electrode which can be implanted with large doses are too close to a channel area, so that the channel is too short, even the source drain electrode and the drain electrode are communicated and the like is solved.
According to another exemplary embodiment of the present application, a semiconductor device is provided, which is manufactured by using any one of the above methods for manufacturing a semiconductor device.
The semiconductor device is obtained by adopting any one of the manufacturing methods of the semiconductor device, and the method ensures that the hot carrier injection effect of the high-voltage device area is smaller by thickening the side wall thickness of the grid electrode on the high-voltage device area, relieves the damage of the hot carrier injection effect to the semiconductor device, and solves the problem that the performance of the semiconductor device is degraded or damaged due to the larger hot carrier injection effect of the high-voltage device area in the prior art. Meanwhile, because the high-voltage device area and the low-voltage device area are different in sensitivity degree to HCI, the thickness of the side wall of the grid electrode on the low-voltage device area is smaller than that of the side wall of the grid electrode on the high-voltage device area, so that the HCI of the high-voltage device area is smaller, and the performance of the device in the low-voltage device area is basically not influenced.
According to another exemplary embodiment of the present application, there is provided a semiconductor device including: the device comprises a substrate, a first grid, a second grid and a dielectric layer, wherein the substrate comprises a high-voltage device area and a low-voltage device area; the first gate is located on the high voltage device region and the second gate is located on the low voltage device region; the dielectric layer at least covers the first grid electrode and the second grid electrode, the thickness of the dielectric layer on the side wall of the first grid electrode is a first thickness, the thickness of the dielectric layer on the side wall of the second grid electrode is a second thickness, and the first thickness is larger than the second thickness.
The semiconductor device comprises a substrate with a high-voltage device area and a low-voltage device area, a first grid electrode positioned on the high-voltage device area, a second grid electrode positioned on the low-voltage device area and a dielectric layer positioned on the surfaces of the first grid electrode and the second grid electrode, wherein the thickness of the dielectric layer on the side wall of the first grid electrode is larger than that of the dielectric layer on the side wall of the second grid electrode, namely the thickness of the side wall of the first grid electrode on the high-voltage device area is larger than that of the side wall of the low-voltage device area. According to the manufacturing method, the thickness of the side wall of the grid electrode on the high-voltage device area is increased, so that the hot carrier injection effect of the high-voltage device area is small, the damage of the hot carrier injection effect to the semiconductor device is relieved, and the problem that the performance of the semiconductor device is degraded or damaged due to the fact that the hot carrier injection effect of the high-voltage device area is large in the prior art is solved. Meanwhile, because the high-voltage device area and the low-voltage device area are different in sensitivity degree to HCI, the thickness of the side wall of the grid electrode on the low-voltage device area is smaller than that of the side wall of the grid electrode on the high-voltage device area, so that the HCI of the high-voltage device area is smaller, and the performance of the device in the low-voltage device area is basically not influenced.
According to another specific embodiment of the present application, the dielectric layer includes a first dielectric sublayer located on a sidewall of the first gate and a sidewall of the second gate; a second dielectric sub-layer located on a surface of a sidewall of the first dielectric sub-layer away from the first gate and a surface of a sidewall of the first dielectric sub-layer away from the second gate; and the third dielectric sublayer is positioned on the surface of the side wall of the second dielectric sublayer, which is far away from the first grid electrode. Compared with the prior art, the two dielectric layers are arranged on the side wall of the low-voltage device area and the side wall of the high-voltage device area, the two dielectric layers are arranged on the side wall of the low-voltage device area, the two dielectric layers on the side wall of the high-voltage device area are increased to the three dielectric layers from the two dielectric layers while the two dielectric layers are arranged on the side wall of the low-voltage device area, and the hot carrier injection effect of the high-voltage device area is improved, so that the damage of the hot carrier injection effect to a semiconductor device is further guaranteed to be relieved, the low-voltage device area is enabled to keep the original performance, the saturated drain current of the low-voltage device area is further guaranteed to be small, and the response speed of the low-voltage device area is high.
In practical applications, the first, second and third dielectric sublayers may be made of materials available in the prior art. In a specific embodiment, the material of the first dielectric sublayer includes silicon oxide, the material of the second dielectric sublayer includes silicon nitride, and the material of the third dielectric sublayer includes silicon oxide. In a more specific embodiment, the first dielectric sublayer is silicon oxide, the second dielectric sublayer is silicon nitride, and the third dielectric sublayer is silicon oxide.
According to another specific embodiment of the present application, the semiconductor device further includes a gate oxide layer, the gate oxide layer includes a high voltage gate oxide layer and a low voltage gate oxide layer, the high voltage gate oxide layer is located between the high voltage device region and the first gate, and the low voltage gate oxide layer is located between the low voltage device region and the second gate. The thickness of the high-voltage gate oxide layer is larger than that of the low-voltage gate oxide layer. The high-voltage gate oxide layer is larger in thickness, and the high-voltage device area can have higher pressure-bearing capacity due to the larger thickness.
In the above embodiments of the present invention, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:
1) in the method for manufacturing the semiconductor device, a substrate including a high-voltage device region and a low-voltage device region is provided, a first gate and a second gate are formed on the high-voltage device region and the low-voltage device region, respectively, and a dielectric layer is formed on exposed surfaces of at least the first gate and the second gate, wherein the thickness of the dielectric layer on the sidewall of the first gate is greater than that of the dielectric layer on the sidewall of the second gate, that is, the sidewall thickness of the first gate on the high-voltage device region is greater than that of the low-voltage device region. According to the manufacturing method, the thickness of the side wall of the grid electrode on the high-voltage device area is increased, so that the hot carrier injection effect of the high-voltage device area is small, the damage of the hot carrier injection effect to the semiconductor device is relieved, and the problem that the performance of the semiconductor device is degraded or damaged due to the fact that the hot carrier injection effect of the high-voltage device area is large in the prior art is solved. Meanwhile, because the high-voltage device area and the low-voltage device area are different in sensitivity degree to HCI, the thickness of the side wall of the grid electrode on the low-voltage device area is smaller than that of the side wall of the grid electrode on the high-voltage device area, so that the HCI of the high-voltage device area is smaller, and the performance of the device in the low-voltage device area is basically not influenced.
2) The semiconductor device is obtained by adopting any one of the manufacturing methods of the semiconductor device, and the method ensures that the hot carrier injection effect of the high-voltage device area is small by thickening the side wall thickness of the grid electrode in the high-voltage device area, relieves the damage of the hot carrier injection effect to the semiconductor device, and solves the problem that the performance of the semiconductor device is degraded or damaged due to the large hot carrier injection effect of the high-voltage device area in the prior art. Meanwhile, because the high-voltage device area and the low-voltage device area are different in sensitivity degree to HCI, the thickness of the side wall of the grid electrode on the low-voltage device area is smaller than that of the side wall of the grid electrode on the high-voltage device area, so that the HCI of the high-voltage device area is smaller, and the performance of the device in the low-voltage device area is basically not influenced.
3) The semiconductor device includes a substrate having a high-voltage device region and a low-voltage device region, a first gate located on the high-voltage device region, a second gate located on the low-voltage device region, and a dielectric layer located on the surfaces of the first gate and the second gate, wherein the thickness of the dielectric layer on the sidewall of the first gate is greater than the thickness of the dielectric layer on the sidewall of the second gate, that is, the sidewall thickness of the first gate on the high-voltage device region is greater than the sidewall thickness of the low-voltage device region. According to the manufacturing method, the thickness of the side wall of the grid electrode on the high-voltage device area is increased, so that the hot carrier injection effect of the high-voltage device area is small, the damage of the hot carrier injection effect to the semiconductor device is relieved, and the problem that the performance of the semiconductor device is degraded or damaged due to the fact that the hot carrier injection effect of the high-voltage device area is large in the prior art is solved. Meanwhile, because the high-voltage device area and the low-voltage device area are different in sensitivity degree to HCI, the thickness of the side wall of the grid electrode on the low-voltage device area is smaller than that of the side wall of the grid electrode on the high-voltage device area, so that the HCI of the high-voltage device area is smaller, and the performance of the device in the low-voltage device area is basically not influenced.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A method for manufacturing a semiconductor device, comprising:
providing a substrate, wherein the substrate comprises a high-voltage device area and a low-voltage device area;
forming a first grid electrode on the high-voltage device area, and forming a second grid electrode on the low-voltage device area;
and forming dielectric layers at least on the exposed surface of the first grid electrode and the exposed surface of the second grid electrode, wherein the thickness of the dielectric layer on the side wall of the first grid electrode is a first thickness, the thickness of the dielectric layer on the side wall of the second grid electrode is a second thickness, and the first thickness is greater than the second thickness.
2. The method of claim 1, wherein forming a dielectric layer on at least an exposed surface of the first gate and an exposed surface of the second gate comprises:
sequentially superposing a first dielectric sublayer, a second dielectric sublayer and a third dielectric sublayer on the exposed surfaces of the substrate, the first grid and the second grid;
removing part of the third dielectric sublayer, and reserving part of the third dielectric sublayer positioned on the side wall of the first grid electrode;
and removing part of the second dielectric sublayer, and reserving part of the second dielectric sublayer on the side wall of the first gate and on the side wall of the second gate, wherein the first dielectric sublayer, the reserved part of the second dielectric sublayer and the reserved part of the third dielectric sublayer form the dielectric layer.
3. The method of claim 2, wherein removing a portion of the third dielectric sublayer comprises:
injecting a predetermined element into the third dielectric sublayer on the surface of the second gate, wherein the third dielectric sublayer after the predetermined element is injected forms a dielectric loose layer;
and removing the dielectric loose layer, the third dielectric sub-layer on the surface of the substrate and the third dielectric sub-layer on the surface of the first grid far away from the substrate.
4. The method of claim 3, wherein implanting a predetermined element into the third dielectric sublayer on the second gate surface comprises:
forming a sacrificial layer on an exposed surface of the third dielectric sublayer located on the first gate surface;
injecting the predetermined element into the third medium sub-layer which is not shielded by the sacrificial layer to obtain the medium loose layer;
and removing the sacrificial layer.
5. A method for manufacturing a semiconductor device according to claim 3 or 4, wherein the predetermined element is an inert element.
6. A semiconductor device, comprising:
a substrate including a high voltage device region and a low voltage device region;
the first grid electrode is positioned on the high-voltage device area, and the second grid electrode is positioned on the low-voltage device area;
and the dielectric layer at least covers the first grid electrode and the second grid electrode, the thickness of the dielectric layer on the side wall of the first grid electrode is a first thickness, the thickness of the dielectric layer on the side wall of the second grid electrode is a second thickness, and the first thickness is larger than the second thickness.
7. The semiconductor device of claim 6, wherein the dielectric layer comprises:
the first dielectric sublayer is positioned on the side wall of the first grid electrode and the side wall of the second grid electrode;
the second dielectric sublayer is positioned on the surface of the side wall of the first dielectric sublayer, which is far away from the first grid electrode, and the surface of the side wall of the first dielectric sublayer, which is far away from the second grid electrode;
and the third dielectric sublayer is positioned on the surface of the side wall of the second dielectric sublayer, which is far away from the first grid electrode.
8. The semiconductor device of claim 7, wherein the material of the first dielectric sublayer comprises silicon oxide, the material of the second dielectric sublayer comprises silicon nitride, and the material of the third dielectric sublayer comprises silicon oxide.
9. The semiconductor device according to any one of claims 6 to 8, further comprising:
and the gate oxide layer comprises a high-voltage gate oxide layer and a low-voltage gate oxide layer, the high-voltage gate oxide layer is positioned between the high-voltage device area and the first grid electrode, and the low-voltage gate oxide layer is positioned between the low-voltage device area and the second grid electrode.
10. The semiconductor device of claim 9, wherein a thickness of the high voltage gate oxide layer is greater than a thickness of the low voltage gate oxide layer.
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| CN117690927A (en) * | 2024-02-04 | 2024-03-12 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and preparation method thereof |
| CN117690927B (en) * | 2024-02-04 | 2024-06-07 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and preparation method thereof |
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