CN105097542A - 一种半导体器件的制造方法和电子装置 - Google Patents

一种半导体器件的制造方法和电子装置 Download PDF

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CN105097542A
CN105097542A CN201410220030.3A CN201410220030A CN105097542A CN 105097542 A CN105097542 A CN 105097542A CN 201410220030 A CN201410220030 A CN 201410220030A CN 105097542 A CN105097542 A CN 105097542A
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semiconductor device
grid
manufacture method
fin structure
shallow trench
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CN105097542B (zh
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韩秋华
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Abstract

本发明提供一种半导体器件的制造方法和电子装置，涉及半导体技术领域。本发明的半导体器件的制造方法，通过在形成伪栅极和栅极侧壁之前控制浅沟槽隔离的厚度，可以保证伪栅极和栅极侧壁具有良好的形貌，通过在形成伪栅极和栅极侧壁之后、形成金属栅极之前，去除沟道区域的一定厚度的浅沟槽隔离，可以保证鳍型结构达到预定高度以及最终形成的金属栅极具有良好的形貌，因此，相对于现有技术，可以提高半导体器件的性能和良率。本发明的电子装置，使用了上述半导体器件，因而同样具有上述优点。

Description

一种半导体器件的制造方法和电子装置
技术领域
本发明涉及半导体技术领域，具体而言涉及一种半导体器件的制造方法和电子装置。
背景技术
在半导体技术领域中，随着半导体技术工艺节点的不断减小，鳍型场效应晶体管(FinFET)由于具有优异的性能表现而得到了广泛的应用。
在一种半导体器件的制造方法中，包括：形成鳍型结构(Fin)、形成位于鳍型结构之间的浅沟槽隔离(STI)、形成覆盖鳍型结构的顶端与侧壁的栅极、以及形成位于栅极两侧的侧壁层(spacer)等步骤。其中，在形成栅极和栅极侧壁的步骤中，由于鳍型结构的高度(指鳍型结构高出浅沟槽隔离的部分)导致的高纵横比，往往造成无法形成良好的栅极图案和栅极侧壁图案(topographyissue)。
由此可见，现有技术中存在无法形成良好的栅极图案和栅极侧壁图案的问题，而这会严重影响半导体器件的性能和良率。为解决这一技术问题，有必要提出一种新的半导体器件的制造方法和电子装置。
发明内容
针对现有技术的不足，本发明提出一种半导体器件的制造方法和电子装置。
本发明的一个实施例提供一种半导体器件的制造方法，所述方法包括：
步骤S101：提供半导体衬底，通过刻蚀工艺在所述半导体衬底上形成鳍型结构；
步骤S102：在所述鳍型结构的两侧形成浅沟槽隔离；
步骤S103：在所述鳍型结构之上形成伪栅极以及位于所述伪栅极两侧的栅极侧壁；
步骤S104：通过刻蚀工艺将所述浅沟槽隔离位于栅极区域以外的部分去除一定的厚度；
步骤S105：在所述半导体衬底上形成层间介电层；
步骤S106：去除所述伪栅极；
步骤S107：通过刻蚀工艺将所述浅沟槽隔离位于栅极区域的部分中的至少一部分去除一定的厚度；
步骤S108：在所述伪栅极原来的位置形成高k介电层和金属栅极。
可选地，在所述步骤S104中，所述刻蚀工艺为各向同性刻蚀。
可选地，在所述步骤S104中，所述浅沟槽隔离位于栅极区域以外的部分被去除的厚度为5nm～20nm。
可选地，在所述步骤S107中，所述刻蚀工艺包括采用DHF的湿法刻蚀或采用SiCoNi的干法刻蚀。
在一个示例中，在所述步骤S107中，将所述浅沟槽隔离位于PMOS的栅极区域的部分去除一定厚度，以使得位于PMOS区的所述鳍型结构高于位于NMOS区的所述鳍型结构。
在另一个示例中，在所述步骤S107中，将所述浅沟槽隔离位于NMOS的栅极区域的部分去除一定厚度，以使得位于NMOS区的所述鳍型结构高于位于PMOS区的所述鳍型结构。
可选地，在所述步骤S105与所述步骤S106之间还包括步骤S1056：
对所述层间介电层进行离子注入，以降低所述层间介电层在去除所述伪栅极的工艺中的去除率。
可选地，在所述步骤S1056中，所述离子注入采用的注入离子为碳，注入能量为10KV～50KV，注入剂量为1E15～1E19。
可选地，所述步骤S101包括：
步骤S1011：提供半导体衬底，在所述半导体衬底上形成硬掩膜层；
步骤S1012：利用所述硬掩膜层对所述半导体衬底进行刻蚀，以形成鳍型结构。
可选地，所述步骤S102包括：
步骤S1021：在所述半导体衬底上沉积隔离材料；
步骤S1022：通过CMP工艺去除所述隔离材料高于所述鳍型结构的部分；
步骤S1023：通过回刻蚀去除一定厚度的所述隔离材料以形成浅沟槽隔离。
可选地，所述步骤S103包括：
步骤S1031：在所述半导体衬底上沉积覆盖所述鳍型结构的伪栅极材料层；
步骤S1032：对所述伪栅极材料层进行刻蚀以形成伪栅极(102)；
步骤S1033：在所述半导体衬底上形成覆盖所述伪栅极结构的侧壁材料层；
步骤S1034：对所述侧壁材料层进行刻蚀以形成位于所述伪栅极两侧的栅极侧壁。
可选地，所述步骤S105包括：
在所述半导体衬底上形成介电材料层；
对所述介电材料层进行CMP工艺以形成层间介电层。
可选地，在所述步骤S106中，去除所述伪栅极的方法包括湿法刻蚀。
可选地，所述步骤S108包括：
步骤S1081：在所述半导体衬底上沉积高k介电材料和位于其上的栅极金属；
步骤S1082：通过CMP工艺去除所述栅极金属和所述高k介电材料高于所述栅极侧壁的部分，以形成高k介电层和金属栅极。
可选地，在所述步骤S104与所述步骤S105之间还包括步骤S1045：
在所述伪栅极的两侧形成源极和漏极。
本发明的另一个实施例提供一种电子装置，包括电子组件以及与所述电子组件电连接的半导体器件，其中所述半导体器件的制造方法包括如下步骤：
步骤S101：提供半导体衬底，通过刻蚀工艺在所述半导体衬底上形成鳍型结构；
步骤S102：在所述鳍型结构的两侧形成浅沟槽隔离；
步骤S103：在所述鳍型结构之上形成伪栅极以及位于所述伪栅极两侧的栅极侧壁；
步骤S104：通过刻蚀工艺将所述浅沟槽隔离位于栅极区域以外的部分去除一定的厚度；
步骤S105：在所述半导体衬底上形成层间介电层；
步骤S106：去除所述伪栅极；
步骤S107：通过刻蚀工艺将所述浅沟槽隔离位于栅极区域的部分中的至少一部分去除一定的厚度；
步骤S108：在所述伪栅极原来的位置形成高k介电层和金属栅极。
本发明的半导体器件的制造方法，通过在形成伪栅极和栅极侧壁之前控制浅沟槽隔离的厚度，可以保证伪栅极和栅极侧壁具有良好的形貌，通过在形成伪栅极和栅极侧壁之后、形成金属栅极之前，去除沟道区域的一定厚度的浅沟槽隔离，可以保证鳍型结构达到预定高度以及最终形成的金属栅极具有良好的形貌，因此，相对于现有技术，可以提高半导体器件的性能和良率。本发明的电子装置，使用了上述半导体器件，因而同样具有上述优点。
附图说明
本发明的下列附图在此作为本发明的一部分用于理解本发明。附图中示出了本发明的实施例及其描述，用来解释本发明的原理。
附图中：
图1A至图1I为本发明的一个实施例的半导体器件的制造方法的相关步骤形成的结构的示意图；
图1H’和图1I’为本发明的一个实施例的半导体器件的制造方法的其中两个步骤形成的结构的示意图；
图2为本发明的一个实施例的半导体器件的制造方法的一种示意性流程图。
具体实施方式
在下文的描述中，给出了大量具体的细节以便提供对本发明更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本发明可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本发明发生混淆，对于本领域公知的一些技术特征未进行描述。
应当理解的是，本发明能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本发明的范围完全地传递给本领域技术人员。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例。这样，可以预期由于例如制造技术和/或容差导致的从所示形状的变化。因此，本发明的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本发明的范围。
为了彻底理解本发明，将在下列的描述中提出详细的步骤以及详细的结构，以便阐释本发明的技术方案。本发明的较佳实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。
实施例一
下面，参照图1A至图1I、图1H’和图1I’以及图2来描述本发明的一个实施例提出的半导体器件的制造方法。其中，图1A至图1I为本发明的一个实施例的半导体器件的制造方法的相关步骤形成的结构的示意图；图1H’和图1I’为本发明的一个实施例的半导体器件的制造方法的其中两个步骤形成的结构的示意图；图2为本发明的一个实施例的半导体器件的制造方法的一种示意性流程图。图1A至图1I分别包括两个示意图，其中，右图为俯视图，左图为沿右图中的切割线(AA’或BB’)的剖视图。图1H’和图1I’也分别包括两个示意图，其中，右图为俯视图，左图为沿右图中的切割线AA’的剖视图。
本发明实施例的半导体器件的制造方法，包括如下步骤：
步骤A1：提供半导体衬底100，通过刻蚀工艺在半导体衬底100上形成鳍型结构1001，如图1A所示。
通常地，鳍型结构1001的顶端还可以形成有硬掩膜层10011，如图1A所示。
在图1A中，右图为俯视图，左图为沿右图中的切割线AA’的剖视图。作为示例，图1A分别示出了位于PMOS区和NMOS区的两个鳍型结构。
在一个实例中，步骤A1包括如下步骤：
步骤A101：提供半导体衬底100，在半导体衬底100上形成硬掩膜层10011；
步骤A102：利用硬掩膜层10011对半导体衬底100进行刻蚀，以形成鳍型结构1001。
其中，半导体衬底100可以为硅衬底、SOI衬底或其他合适衬底。硬掩膜层10011的材料可以为氮化硅或其他合适的材料。
步骤A2：在半导体衬底100上形成位于鳍型结构1001两侧的浅沟槽隔离(STI)101，如图1B所示。
在图1B中，右图为俯视图，左图为沿右图中的切割线AA’的剖视图。
其中，浅沟槽隔离101的材料，可以为氧化硅或其他合适的材料。
在本步骤中，位于不同区域(PMOS区或NMOS区)的浅沟槽隔离101的厚度通常相同，浅沟槽隔离101的上表面处于同一平面。
示例性地，步骤A2可以包括如下步骤：
步骤A201：在半导体衬底100上沉积隔离材料。
其中，隔离材料可以为氧化硅或其他合适的材料。沉积的隔离材料通常高于鳍型结构1001上的硬掩膜层10011。
步骤A202：通过CMP工艺去除所述隔离材料高于硬掩膜层10011的部分。
步骤A203：通过回刻蚀(etchback)工艺去除一定厚度的隔离材料，以形成浅沟槽隔离101，形成的结构如图1B所示。
在本步骤中，通过回刻蚀(etchback)工艺去除的隔离材料的厚度，比现有技术中去除的厚度要小，以避免形成高纵横比从而导致无法形成良好的栅极和栅极侧壁图案。也就是说，在本步骤中，鳍型结构高于浅沟槽隔离的高度，比现有技术中在相应步骤中形成的鳍型结构高于浅沟槽隔离的高度要低。
在本实施例中，可以在后续步骤中，通过对浅沟槽隔离101再次进行刻蚀，实现预定高度的鳍型结构。
步骤A3：在鳍型结构1001之上形成伪栅极(dummygate)102以及位于伪栅极102两侧的栅极侧壁(spacer)103，如图1C所示。
在图1C中，右图为俯视图，左图为沿右图中的切割线AA’的剖视图。
其中，伪栅极102的材料可以为多晶硅或其他合适的材料。栅极侧壁103可以为氧化硅、氮化硅或其他合适的材料。
示例性地，步骤A3可以通过如下步骤实现：
步骤A301：在半导体衬底100上沉积覆盖鳍型结构1001的伪栅极材料层；
步骤A302：对伪栅极材料层进行刻蚀，以形成伪栅极102；
步骤A303：在半导体衬底100上形成覆盖伪栅极结构的侧壁材料层；
步骤A304：对侧壁材料层进行刻蚀以形成位于伪栅极102两侧的栅极侧壁103。
经过步骤A301至A304，形成的结构如图1C所示。
本实施例的步骤A3还可以采用其他各种可行的方式来实现，在此并不进行限定。
步骤A4：通过刻蚀工艺将浅沟槽隔离101位于栅极区域以外的部分去除一定的厚度，如图1D所示。
在图1D中，右图为俯视图，左图为沿右图中的切割线BB’的剖视图。浅沟槽隔离101位于栅极区域以外的部分(即，浅沟槽隔离101位于伪栅极102两侧的部分)被去除一定厚度后，记作101’，如图1D所示。
其中，刻蚀工艺可以采用干法刻蚀、湿法刻蚀或其他合适的刻蚀方法。示例性地，所述刻蚀工艺为各向同性刻蚀。浅沟槽隔离101位于栅极区域以外的部分被去除的厚度可以为5nm～20nm。
由于之前的步骤A2形成的浅沟槽隔离101的厚度较厚，相应的鳍型结构1001比现有技术要低，因此，本步骤将浅沟槽隔离101位于栅极区域之外的部分去除一定的厚度，可以使得鳍型结构1001在相应区域达到预定高度。需要指出的是，现有技术中通常在步骤A2中就实现预定高度的鳍型结构(通过一并去除适当厚度的浅沟槽隔离实现)，并不具有这一步骤。
此外，在本步骤中，在将浅沟槽隔离101位于伪栅极102两侧的部分去除一定的厚度之后，还可以进行在伪栅极102的两侧形成源极和漏极的步骤。其中，形成源极和漏极的步骤，可以采用现有的各种可行的方法来实现。为了表示的简要，图1D中未示出源极和漏极。
步骤A5：在半导体衬底100上形成层间介电层104，如图1E所示。
在图1E中，右图为俯视图，左图为沿右图中的切割线AA’的剖视图。
其中，层间介电层104主要位于相邻的伪栅极102之间，其高度通常与伪栅极102的高度一致。层间介电层104的材料可以为氧化硅或其他合适的材料。
示例性地，步骤A5可以包括：在半导体衬底100上形成介电材料层并进行CMP，以形成层间介电层104。
步骤A6：对层间介电层104进行离子注入以降低层间介电层104在后续的伪栅极102的去除工艺中的去除率，如图1F所示。
在图1F中，右图为俯视图，左图为沿右图中的切割线AA’的剖视图。其中，向下的箭头用于示意离子注入过程。
在本步骤中，进行离子注入时所注入的离子为碳或其他具有类似性质的离子。对层间介电层104进行离子注入的同时，也可以对伪栅极102和栅极侧壁103一并进行离子注入，在此并不进行限定。
示例性地，所注入的离子为碳离子，离子注入采用的注入能量(energy)为10KV～50KV，注入剂量(dosage)为1E15～1E19。
其中，降低层间介电层104在去除伪栅极的工艺中的去除率(例如：降低层间介电层的湿法刻蚀速率)，主要是为了避免在后续的去除伪栅极102的过程中对层间介电层104造成损害。在某些情况下，步骤A6可以省略，例如，当层间介电层104本身不易受去除伪栅极102的工艺的影响时。
步骤A7：去除伪栅极102，如图1G所示。
在图1G中，右图为俯视图，左图为沿右图中的切割线AA’的剖视图。
其中，去除伪栅极102的方法，可以为湿法刻蚀或其他合适的方法。
由于步骤A7的存在，可以降低层间介电层104的在去除伪栅极102的工艺中的去除率，因此，可以避免在去除伪栅极102的过程中对层间介电层104造成损害，从而可以提高器件的良率。
步骤A8：通过刻蚀工艺将浅沟槽隔离101位于栅极区域(即，沟道区域)的部分中的至少一部分(例如，位于PMOS的栅极区域的部分)去除一定的厚度。
其中，图1H示意了将浅沟槽隔离101位于栅极区域的部分全部去除一定的厚度之后形成的结构。在图1H中，右图为俯视图，左图为沿右图中的切割线AA’的剖视图。浅沟槽隔离101位于栅极区域的部分被去除一定厚度后，记作101”，如图1H所示。
除图1H所示的情况外，还可以对浅沟槽隔离101位于栅极区域的部分进行选择性去除，例如：仅去除浅沟槽隔离101位于PMOS的栅极区域的部分，或仅去除浅沟槽隔离101位于NMOS的栅极区域的部分，此时将使得鳍型结构1001在不同的区域(例如PMOS区与NMOS区)具有不同的高度，即，可以在同一半导体器件中形成不同高度的鳍型结构。
在一个实例中，仅将浅沟槽隔离101位于PMOS的栅极区域的部分去除一定的厚度，以使得位于PMOS区的鳍型结构高于位于NMOS区的鳍型结构。
在本实施例中，刻蚀工艺可以采用干法刻蚀、湿法刻蚀或其他合适的刻蚀方法。示例性地，刻蚀工艺为采用DHF(稀释的氢氟酸)的湿法刻蚀，或采用SiCoNi的干法刻蚀。在采用DHF的湿法刻蚀中，选取的DHF可以为50:1～1000:1的DHF。
由于之前的步骤A2形成的浅沟槽隔离101的厚度较厚，相应的鳍型结构1001比现有技术要低。本步骤将浅沟槽隔离101位于栅极区域的部分中的至少一部分去除一定的厚度，可以使得鳍型结构1001在相应区域达到预定高度。并且，如果仅将浅沟槽隔离101位于栅极区域的部分中的一部分去除，可以形成不同高度的鳍型结构。
步骤A9：在栅极区域形成高k介电层105和位于高k介电层105之上的金属栅极106，如图1I所示。
其中，高k介电层105和金属栅极106可以采用现有技术中的各种合适的材料，在此并不进行限定。
示例性地，步骤A9包括如下步骤：
步骤A901：在半导体衬底上沉积高k介电材料和位于其上的栅极金属；
步骤A902：通过CMP工艺去除栅极金属和高k介电材料高于栅极侧壁103的部分，以形成高k介电层105和金属栅极106。
在本发明实施例的一个实例中，步骤A1至A7与上述描述完全相同，步骤A8与步骤A9形成的结构与图1H和图1I示出的结构有所不同。具体如下：
在步骤A8中，通过刻蚀工艺将浅沟槽隔离101位于PMOS的栅极区域的部分去除一定的厚度，以使得位于PMOS区的鳍型结构高于位于NMOS区的鳍型结构，如图1H’所示。
其中，图1H’示意了将浅沟槽隔离101位于PMOS的栅极区域的部分去除一定的厚度之后形成的结构。在图1H’中，右图为俯视图，左图为沿右图中的切割线AA’的剖视图。浅沟槽隔离101位于PMOS的栅极区域的部分被去除一定厚度后，记作101A”，如图1H’所示。也就是说，图1H’示出了在同一半导体器件中形成不同高度的鳍型结构的情况。
相应地，经过步骤A9形成的结构如图1I’所示。
本实施例的半导体器件的制造方法，在形成伪栅极102和栅极侧壁103之前，通过控制浅沟槽隔离的厚度从而控制鳍型结构的高度，可以保证形成的伪栅极和栅极侧壁103具有良好的形貌；在形成伪栅极102和栅极侧壁103之后、形成金属栅极之前，通过去除沟道区域(也称栅极区域)的一定厚度的浅沟槽隔离，保证了鳍型结构可以达到预定高度，并保证了最终形成的金属栅极具有良好的形貌。因此，相对于现有技术，本实施例的半导体器件的制造方法可以提高半导体器件的性能和良率。
图2示出了本发明的一个实施例提出的半导体器件的制造方法的一种示意性流程图，用于简要示出上述方法的典型流程。具体包括：
在步骤S101中，提供半导体衬底，通过刻蚀工艺在所述半导体衬底上形成鳍型结构；
在步骤S102中，在所述鳍型结构的两侧形成浅沟槽隔离；
在步骤S103中，在所述鳍型结构之上形成伪栅极以及位于所述伪栅极两侧的栅极侧壁；
在步骤S104中，通过刻蚀工艺将所述浅沟槽隔离位于栅极区域以外的部分去除一定的厚度；
在步骤S105中，在所述半导体衬底上形成层间介电层；
在步骤S106中，去除所述伪栅极；
在步骤S107中，通过刻蚀工艺将所述浅沟槽隔离位于栅极区域的部分中的至少一部分去除一定的厚度；
在步骤S108中，在所述伪栅极原来的位置形成高k介电层和金属栅极。
实施例二
本发明实施例提供一种电子装置，其包括电子组件以及与该电子组件电连接的半导体器件。其中，所述半导体器件为根据实施例一所述的半导体器件的制造方法制造的半导体器件。
本实施例的电子装置，可以是手机、平板电脑、笔记本电脑、上网本、游戏机、电视机、VCD、DVD、导航仪、照相机、摄像机、录音笔、MP3、MP4、PSP等任何电子产品或设备，也可为任何包括该半导体器件的中间产品。其中，该电子组件可以为任何组件，在此并不进行限定。
本发明实施例的电子装置，由于使用了上述的半导体器件，因而具有更好的性能。
本发明已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本发明限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本发明并不局限于上述实施例，根据本发明的教导还可以做出更多种的变型和修改，这些变型和修改均落在本发明所要求保护的范围以内。本发明的保护范围由附属的权利要求书及其等效范围所界定。

Claims (16)

1.一种半导体器件的制造方法，其特征在于，所述方法包括：
步骤S101：提供半导体衬底，通过刻蚀工艺在所述半导体衬底上形成鳍型结构；
步骤S102：在所述鳍型结构的两侧形成浅沟槽隔离；
步骤S103：在所述鳍型结构之上形成伪栅极以及位于所述伪栅极两侧的栅极侧壁；
步骤S104：通过刻蚀工艺将所述浅沟槽隔离位于栅极区域以外的部分去除一定的厚度；
步骤S105：在所述半导体衬底上形成层间介电层；
步骤S106：去除所述伪栅极；
步骤S107：通过刻蚀工艺将所述浅沟槽隔离位于栅极区域的部分中的至少一部分去除一定的厚度；
步骤S108：在所述伪栅极原来的位置形成高k介电层和金属栅极。
2.如权利要求1所述的半导体器件的制造方法，其特征在于，在所述步骤S104中，所述刻蚀工艺为各向同性刻蚀。
3.如权利要求1所述的半导体器件的制造方法，其特征在于，在所述步骤S104中，所述浅沟槽隔离位于栅极区域以外的部分被去除的厚度为5nm～20nm。
4.如权利要求1所述的半导体器件的制造方法，其特征在于，在所述步骤S107中，所述刻蚀工艺包括采用DHF的湿法刻蚀或采用SiCoNi的干法刻蚀。
5.如权利要求1所述的半导体器件的制造方法，其特征在于，在所述步骤S107中，将所述浅沟槽隔离位于PMOS的栅极区域的部分去除一定厚度，以使得位于PMOS区的所述鳍型结构高于位于NMOS区的所述鳍型结构。
6.如权利要求1所述的半导体器件的制造方法，其特征在于，在所述步骤S107中，将所述浅沟槽隔离位于NMOS的栅极区域的部分去除一定厚度，以使得位于NMOS区的所述鳍型结构高于位于PMOS区的所述鳍型结构。
7.如权利要求1所述的半导体器件的制造方法，其特征在于，在所述步骤S105与所述步骤S106之间还包括步骤S1056：
对所述层间介电层进行离子注入，以降低所述层间介电层在去除所述伪栅极的工艺中的去除率。
8.如权利要求7所述的半导体器件的制造方法，其特征在于，在所述步骤S1056中，所述离子注入采用的注入离子为碳，注入能量为10KV～50KV，注入剂量为1E15～1E19。
9.如权利要求1所述的半导体器件的制造方法，其特征在于，所述步骤S101包括：
步骤S1011：提供半导体衬底，在所述半导体衬底上形成硬掩膜层；
步骤S1012：利用所述硬掩膜层对所述半导体衬底进行刻蚀，以形成鳍型结构。
10.如权利要求1所述的半导体器件的制造方法，其特征在于，所述步骤S102包括：
步骤S1021：在所述半导体衬底上沉积隔离材料；
步骤S1022：通过CMP工艺去除所述隔离材料高于所述鳍型结构的部分；
步骤S1023：通过回刻蚀去除一定厚度的所述隔离材料以形成浅沟槽隔离。
11.如权利要求1所述的半导体器件的制造方法，其特征在于，所述步骤S103包括：
步骤S1031：在所述半导体衬底上沉积覆盖所述鳍型结构的伪栅极材料层；
步骤S1032：对所述伪栅极材料层进行刻蚀以形成伪栅极(102)；
步骤S1033：在所述半导体衬底上形成覆盖所述伪栅极结构的侧壁材料层；
步骤S1034：对所述侧壁材料层进行刻蚀以形成位于所述伪栅极两侧的栅极侧壁。
12.如权利要求1所述的半导体器件的制造方法，其特征在于，所述步骤S105包括：
在所述半导体衬底上形成介电材料层；
对所述介电材料层进行CMP工艺以形成层间介电层。
13.如权利要求1所述的半导体器件的制造方法，其特征在于，在所述步骤S106中，去除所述伪栅极的方法包括湿法刻蚀。
14.如权利要求1所述的半导体器件的制造方法，其特征在于，所述步骤S108包括：
步骤S1081：在所述半导体衬底上沉积高k介电材料和位于其上的栅极金属；
步骤S1082：通过CMP工艺去除所述栅极金属和所述高k介电材料高于所述栅极侧壁的部分，以形成高k介电层和金属栅极。
15.如权利要求1所述的半导体器件的制造方法，其特征在于，在所述步骤S104与所述步骤S105之间还包括步骤S1045：
在所述伪栅极的两侧形成源极和漏极。
16.一种电子装置，其特征在于，包括电子组件以及与所述电子组件电连接的半导体器件，其中所述半导体器件的制造方法包括如下步骤：
步骤S101：提供半导体衬底，通过刻蚀工艺在所述半导体衬底上形成鳍型结构；
步骤S102：在所述鳍型结构的两侧形成浅沟槽隔离；
步骤S103：在所述鳍型结构之上形成伪栅极以及位于所述伪栅极两侧的栅极侧壁；
步骤S104：通过刻蚀工艺将所述浅沟槽隔离位于栅极区域以外的部分去除一定的厚度；
步骤S105：在所述半导体衬底上形成层间介电层；
步骤S106：去除所述伪栅极；
步骤S107：通过刻蚀工艺将所述浅沟槽隔离位于栅极区域的部分中的至少一部分去除一定的厚度；
步骤S108：在所述伪栅极原来的位置形成高k介电层和金属栅极。
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