JP6709732B2 - TiNゲートを備えた高k/金属ゲートCMOSトランジスタ - Google Patents
TiNゲートを備えた高k/金属ゲートCMOSトランジスタ Download PDFInfo
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- JP6709732B2 JP6709732B2 JP2016544064A JP2016544064A JP6709732B2 JP 6709732 B2 JP6709732 B2 JP 6709732B2 JP 2016544064 A JP2016544064 A JP 2016544064A JP 2016544064 A JP2016544064 A JP 2016544064A JP 6709732 B2 JP6709732 B2 JP 6709732B2
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- 229910052751 metal Inorganic materials 0.000 title claims description 206
- 239000002184 metal Substances 0.000 title claims description 206
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 title claims description 161
- 238000000034 method Methods 0.000 claims description 109
- 239000000463 material Substances 0.000 claims description 83
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 43
- 229920005591 polysilicon Polymers 0.000 claims description 43
- 238000000151 deposition Methods 0.000 claims description 25
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 22
- 239000003989 dielectric material Substances 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 22
- 229910052760 oxygen Inorganic materials 0.000 claims description 22
- 239000001301 oxygen Substances 0.000 claims description 22
- 229920002120 photoresistant polymer Polymers 0.000 claims description 21
- 238000002955 isolation Methods 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 2
- 238000000137 annealing Methods 0.000 claims 4
- 239000000945 filler Substances 0.000 claims 2
- 238000004519 manufacturing process Methods 0.000 description 37
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 24
- 239000000758 substrate Substances 0.000 description 16
- 238000000231 atomic layer deposition Methods 0.000 description 15
- 238000009792 diffusion process Methods 0.000 description 12
- 235000012239 silicon dioxide Nutrition 0.000 description 12
- 239000000377 silicon dioxide Substances 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910004129 HfSiO Inorganic materials 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
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Description
Claims (17)
- 集積回路を形成するプロセスであって、
PMOSトランジスタエリアとNMOSトランジスタエリアとの両方において厚いTiN層を形成することと、
前記厚いTiN層を酸素内でアニールすることと、
アニールした後に、前記NMOSトランジスタエリアにおいて前記厚いTiN層を取り除くことと、
前記NMOSトランジスタエリアにおいて前記厚いTiN層を取り除いた後に、前記PMOSトランジスタエリアと前記NMOSトランジスタエリアとの両方において薄いTiN層を形成することであって、前記薄いTiN層が、前記厚いTiN層より薄く、そして低減された酸素濃度を有する、前記薄いTiN層を形成することと、
を含む、プロセス。 - 請求項1に記載のプロセスであって、
厚いTiN金属ゲート材料としての前記厚いTiN層が8nmより大きい厚みを有し、薄いTiN金属としての前記薄いTiN層が1〜3nmの厚みを有する、プロセス。 - 請求項1に記載のプロセスであって、
厚いTiN金属ゲート材料としての前記厚いTiN層が10nmの厚みを有し、薄いTiN金属としての前記薄いTiN層が2nmの厚みを有する、プロセス。 - 請求項1に記載のプロセスであって、
ドープされたポリシリコンを前記薄いTiN層上に堆積することと、
前記ドープされたポリシリコン上にトランジスタゲートパターンを形成することであって、前記トランジスタゲートパターンがPMOSトランジスタゲートパターンとNMOSトランジスタゲートパターンとを含む、前記トランジスタゲートパターンを形成することと、
PMOSトランジスタのゲートを形成するために、前記ドープされたポリシリコンと前記薄いTiN層と前記厚いTiN層とをエッチングすることと、
NMOSトランジスタのゲートを形成するために、前記ポリシリコンと前記薄いTiN層とをエッチングすることと、
を更に含む、プロセス。 - 請求項1に記載のプロセスであって、
前記厚いTiN層を形成する前に、前記NMOSトランジスタエリアにおいてNMOSリプレースメントゲートトランジスタトレンチを形成するために前記NMOSトランジスタエリアからポリシリコンゲートを取り除き、前記PMOSトランジスタエリアにおいてPMOSリプレースメントゲートトランジスタトレンチを形成するために前記PMOSトランジスタエリアからポリシリコンゲートを取り除くこと、
を更に含む、プロセス。 - 請求項1に記載のプロセスであって、
前記厚いTiN層を形成する前に、前記PMOSトランジスタエリアと前記NMOSトランジスタエリアとの両方において第1の高k誘電体を堆積することと、
前記薄いTiN層を形成する前に、前記NMOSトランジスタエリアから前記第1の高k誘電体を取り除き、前記NMOSトランジスタエリアと前記PMOSトランジスタエリアとにおいて第2の高k誘電体を堆積することと、
前記薄いTiN層を形成した後に、前記PMOSトランジスタエリアから前記薄いTiN層を取り除き、前記PMOSトランジスタエリアから前記第2の高k誘電体を取り除くことと、
前記PMOSトランジスタエリアと前記NMOSトランジスタエリアとにおいてドープされたポリシリコンを堆積することと、
前記ドープされたポリシリコン上にトランジスタゲートパターンを形成することであって、前記トランジスタゲートパターンがPMOSトランジスタゲートパターンとNMOSトランジスタゲートパターンとを含む、前記トランジスタゲートパターンを形成することと、
前記PMOSトランジスタのゲートを形成するように、前記ポリシリコンと前記厚いTiN層とをエッチングすることと、
前記NMOSトランジスタのゲートを形成するように、前記ポリシリコンと前記薄いTiN層とをエッチングすることと、
を更に含む、プロセス。 - 請求項6に記載のプロセスであって、
前記第1及び第2の高k誘電体が1.2nmのHfOxであり、前記厚いTiNが10nmの厚みを有し、前記薄いTiNが2nmの厚みを有する、プロセス。 - 請求項1に記載のプロセスであって、
前記厚いTiN層を形成する前に、前記NMOSトランジスタエリアにおいてNMOSリプレースメントゲートトランジスタトレンチを形成するために前記NMOSトランジスタエリアからポリシリコンゲートを取り除き、前記PMOSトランジスタエリアにおいてPMOSリプレースメントゲートトランジスタトレンチを形成するために前記PMOSトランジスタエリアからポリシリコンゲートを取り除き、前記PMOSリプレースメントゲートトランジスタトレンチ内と前記NMOSトランジスタエリアとにおいて第1の高k誘電体を堆積することと、
前記薄いTiN層を形成する前に、前記NMOSトランジスタエリアから前記第1の高k誘電体を取り除き、前記PMOSトランジスタエリア上と前記NMOSリプレースメントゲートトランジスタトレンチ内とに第2の高k誘電体を堆積することと、
前記薄いTiN層を形成した後に、前記PMOSトランジスタエリアから前記薄いTiN層を取り除き、前記PMOSトランジスタエリアから前記第2の高k誘電体を取り除くことと、
を更に含む、プロセス。 - 請求項8に記載のプロセスであって、
前記第1及び第2の高k誘電体が1.2nmのHfOxであり、前記厚いTiNが10nmの厚みを有し、前記薄いTiNが2nmの厚みを有する、プロセス。 - リプレースメント金属ゲートCMOSトランジスタを備える集積回路を形成するプロセスであって、
部分的に処理された集積回路を提供することであって、前記部分的に処理された集積回路が、第1のゲート誘電体上の第1のポリシリコンゲートを備えるPMOSトランジスタと、第2のゲート誘電体上の第2のポリシリコンゲートを備えるNMOSトランジスタとを備え、前記NMOSトランジスタと前記PMOSトランジスタとに重なるプレメタル誘電体を備え、前記プレメタル誘電体が前記第1及び第2のポリシリコンゲートの頂部表面を露出させて平坦化される、前記部分的に処理された集積回路を提供することと、
PMOSリプレースメントゲートトランジスタトレンチとNMOSリプレースメントゲートトランジスタトレンチとを形成するために前記第1及び第2のゲート誘電体から前記第1及び第2のポリシリコンゲートを取り除くようにエッチングすることと、
前記PMOSリプレースメントゲートトランジスタトレンチと前記NMOSリプレースメントゲートトランジスタトレンチ内に第1の高k誘電体を堆積することと、
前記PMOSリプレースメントゲートトランジスタトレンチと前記NMOSリプレースメントゲートトランジスタトレンチ内の前記第1の高k誘電体上に少なくとも8nmのPMOS TiN金属ゲート材料を堆積することと、
前記PMOS TiN金属ゲート材料を酸素内でアニールすることと、
前記NMOSリプレースメントゲートトランジスタトレンチの上に開口を備えるNMOS金属ゲートパターンを形成することと、
下にある誘電体から前記PMOS TiN金属ゲート材料を取り除くために前記NMOSリプレースメントゲートトランジスタトレンチから前記PMOS TiN金属ゲート材料をエッチングすることと、
前記NMOS金属ゲートパターンを取り除くことと、
前記NMOSリプレースメントゲートトランジスタトレンチ内に第2の高k誘電体を堆積することと、
前記第2の高k誘電体上に、低減された酸素濃度を有するNMOS TiN金属ゲート材料を1nm〜3nm堆積することと、
前記PMOSリプレースメントゲートトランジスタトレンチをオーバーフィルし、前記NMOSリプレースメントゲートトランジスタトレンチをオーバーフィルするために、前記NMOS TiN金属ゲート材料の上で充填材金属を堆積することと、
前記プレメタル誘電体の表面から、前記オーバーフィルと、前記PMOS TiN金属ゲート材料と前記NMOS TiN金属ゲート材料との一部とを取り除くために、前記充填材金属と、前記PMOS TiN金属ゲート材料と前記NMOS TiN金属ゲート材料とを研磨することと、
を含む、プロセス。 - 請求項10に記載のプロセスであって、
前記プロセスが高kラストプロセスであり、前記下にある誘電体が前記第2のゲート誘電体であり、
前記プロセスが、
前記第1の高k誘電体を堆積する前に、前記PMOSリプレースメントゲートトランジスタトレンチの上に開口を備える第1のPMOSトランジスタフォトレジストパターンを形成し、前記PMOSリプレースメントゲートトランジスタトレンチから前記第1のゲート誘電体をエッチングし、前記第1のゲート誘電体をエッチングした後に、前記第1のPMOSトランジスタフォトレジストパターンを剥がすことと、
第2の高k誘電体を堆積する前に、前記NMOSリプレースメントゲートトランジスタトレンチから前記第2のゲート誘電体をエッチングすることと、
前記充填材金属を堆積する前に、前記PMOSリプレースメントゲートトランジスタトレンチの上に開口を備える前記集積回路上の第2のPMOSトランジスタフォトレジストパターンを形成することと、
前記NMOS TiN金属ゲート材料をエッチングすることと、
前記第2の高k誘電体をエッチングすることと、
前記充填材金属を堆積する前に前記第2のPMOSトランジスタフォトレジストパターンを取り除くことと、
を更に含む、プロセス。 - 請求項10に記載のプロセスであって、
前記PMOS TiN金属ゲート材料をエッチングすることが、NH4OHとH2O2とを加えた希釈SClにおけるウェットエッチングである、プロセス。 - 請求項10に記載のプロセスであって、
前記第1及び第2の高k誘電体が1.2nmのHfOxであり、前記PMOS TiN金属ゲート材料が10nmの厚みであり、前記NMOS TiN金属ゲート材料が2nmの厚みである、プロセス。 - 金属ゲートファーストCMOSトランジスタを備える集積回路を形成するプロセスであって、
部分的に処理された集積回路を提供することであって、前記部分的に処理された集積回路が、PMOS金属ゲートトランジスタが形成されるべき場所に第1の犠牲誘電体を備える第1の領域を、NMOS金属ゲートトランジスタが形成されるべき場所に第2の犠牲誘電体を備える第2の領域から分離するシャロートレンチアイソレーションを備える、前記部分的に処理された集積回路を提供することと、
前記PMOS金属ゲートトランジスタが形成されるべき場所に第1の高k誘電体を堆積することと、
前記第1の高k誘電体上に少なくとも8nmのPMOS TiN金属ゲート材料を堆積することと、
前記PMOS TiN金属ゲート材料を酸素内でアニールすることと、
前記NMOS金属ゲートトランジスタが形成されるべき場所に開口を備えるNMOS金属ゲートパターンを、前記PMOS TiN金属ゲート材料上に形成することと、
前記PMOS TiN金属ゲート材料を、下にある誘電体から取り除くためにエッチングすることと、
前記NMOS金属ゲートトランジスタが形成されるべき場所に第2の高k誘電体を堆積することと、
前記PMOS TiN金属ゲート材料と比較して低減された酸素濃度を備えるNMOS TiN金属ゲート材料を1nm〜3nm堆積することと、
前記NMOS TiN金属ゲート材料の上にポリシリコンを堆積することと、
前記NMOS金属ゲートトランジスタのゲートと前記PMOS金属ゲートトランジスタのゲートとが形成されるべき場所にレジストジオメトリを有するトランジスタゲートパターンを、前記ポリシリコン上に形成することと、
前記PMOS金属ゲートトランジスタのゲートを形成するように、前記ポリシリコンと前記PMOS TiN金属ゲート材料とをエッチングすることと、
前記NMOS金属ゲートトランジスタのゲートを形成するように、前記ポリシリコンと前記NMOS TiN金属ゲート材料とをエッチングすることと、
を含む、プロセス。 - 請求項14に記載のプロセスであって、
前記プロセスが高kラストプロセスであり、前記下にある誘電体が前記第2の犠牲誘電体であり、
前記プロセスが、
前記第1の高k誘電体を堆積する前に、前記PMOS金属ゲートトランジスタが形成されるべき場所に開口を備える第1のPMOSトランジスタフォトレジストパターンを前記集積回路上に形成し、前記第1の犠牲誘電体をエッチングし、前記第1のPMOSトランジスタフォトレジストパターンを剥がすことと、
前記第2の高k誘電体を堆積する前に、前記第2の犠牲誘電体をエッチングして取り除くことと、
前記ポリシリコンを堆積する前に、前記PMOS金属ゲートトランジスタが形成されるべき場所に開口を備える第2のPMOSトランジスタフォトレジストパターンを前記集積回路上に形成し、前記NMOS TiN金属ゲート材料をエッチングし、前記第2の高k誘電体をエッチングし、前記第2のPMOSトランジスタフォトレジストパターンを取り除くことと、
を更に含む、プロセス。 - 請求項14に記載のプロセスであって、
前記PMOS TiN金属ゲート材料をエッチングすることが、NH4OHとH2O2とを加えた希釈SClにおけるウェットエッチングである、プロセス。 - 請求項14に記載のプロセスであって、
前記第1及び第2の高k誘電体が1.2nmのHfOxであり、前記PMOS TiN金属ゲート材料が10nmの厚みであり、前記NMOS TiN金属ゲート材料が2nmの厚みである、プロセス。
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