CN101236968A - Mos器件及其制造方法 - Google Patents

Mos器件及其制造方法 Download PDF

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CN101236968A
CN101236968A CNA2008100089039A CN200810008903A CN101236968A CN 101236968 A CN101236968 A CN 101236968A CN A2008100089039 A CNA2008100089039 A CN A2008100089039A CN 200810008903 A CN200810008903 A CN 200810008903A CN 101236968 A CN101236968 A CN 101236968A
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sige
layer
sill
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strain regime
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尹海洲
刘小虎
斯德哈萨·潘达
欧阳齐庆
杨美基
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Core Usa Second LLC
GlobalFoundries Inc
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Abstract

公开了一种具有独立应变的沟道区的NMOS和PMOS器件结构及其制造方法。NMOS器件的源极和漏极由使得NMOS器件沟道的应变朝着拉伸方向偏移的材料外延生长。而PMOS器件的源极和漏极由使得PMOS器件沟道的应变朝着压缩方向偏移的材料外延生长。

Description

MOS器件及其制造方法
技术领域
本发明涉及电子器件。具体地说，本发明涉及处于拉伸或压缩应变的MOS器件，并涉及通过外延生长源极和漏极结来制造这种结构的方法。
背景技术
目前的集成电路包括大量的器件。更小的器件和收缩基本规则是提高性能和降低成本的关键。随着FET(场效应晶体管)器件的尺寸缩小，该工艺变得更为复杂，而且从一代器件到下一代需要器件结构的改变和新制造方法来维持所期望的性能提高。微电子器件的主流材料是硅(Si)，或更宽泛地说是Si基材料。一种对微电子器件很重要的Si基材料是硅锗(SiGe)合金。
在深度亚微米时代的器件中很难保持性能的提高。因此，无需改变尺寸就能提高性能的方法就受到关注。一种用于提高性能的通用方法是增大FET中载流子(电子和/或空穴)的迁移率。一种提高载流子迁移率的很有前景的途径是修改用作制造器件的原材料的半导体。已经公知而且近来深入研究过，拉伸或压缩应变地半导体具有非常好的载流子特性。具体地说，电子迁移率的提高已在应变硅(Si)沟道NMOS中实现，如授予J.O.Chu的美国专利6,649,492 B2“Strained SiBased Layer Made By UHV-CVD，and Devices Therein”中所述，通过引用将其合并于此。类似地，为了提高空穴迁移率，压缩应变的SiGe产生了高的空穴迁移率。锗(Ge)也具有很诱人的空穴载流子特性。为此SiGe合金是空穴导电类型器件的优选材料。Si和Ge以及SiGe合金的带结构使得在该材料处于压缩应变时空穴传输、主要是空穴迁移率提高了。在授予J.O.Chu的美国专利6,963,078“Dual Strain-State SiGe Layers for Microelectronics”中描述了在同一个晶片中结合拉伸和压缩应变的SiGe区域，通过引用将其合并于此。
应变Si层可以是在衬底上生长的硅中引入双轴拉伸应变的结果，该衬底由晶格常数大于硅的晶格常数的材料形成。锗的晶格常数大约比硅的晶格常数大4.2％，硅锗合金的晶格常数与其锗的浓度大致成线性函数。结果，包含50个原子百分比锗的SiGe合金的晶格常数大约比硅的晶格常数大2％。硅在这种SiGe衬底上的外延生长将产生处于拉伸应变的硅层。通常，如果外延层具有比下层更小的Ge浓度而且其厚度小于临界厚度，则外延层处于拉伸应变，相反，如果下层具有更低的Ge浓度，则外延层处于压缩应变。
理想状态下，人们希望具有这样的集成电路，即电子导电类型器件如NMOS寄宿(host)在拉伸应变的Si或SiGe材料中，而空穴导电类型器件如PMOS寄宿在压缩应变的Ge或SiGe材料中。(MOSFET代表金属氧化物半导体场效应晶体管，这是具有通常表示绝缘栅极场效应晶体管的历史内涵的名称，而nFET或NMOS以及pFET或PMOS代表n和p型MOSFET。)
发明内容
考虑到所讨论的问题，本发明的实施例公开了由应变材料制成的NMOS和PMOS器件的结构。NMOS和PMOS具有其寄宿在基于Si的层中的对应的沟道区。基于Si的层外延地设置在SiGe支撑层上，基于Si的层具有小于临界厚度的厚度。第一应变状态基于该基于Si的层与该SiGe支撑层的外延关系而为该基于Si的层所固有(pertainto)。
该器件结构还包括与基于Si的层以及与SiGe支撑层外延地交界(interface)的第二Si基材料。NMOS器件的源极和漏极由第二Si基材料制成，该材料具有低于SiGe支撑层的Ge浓度。该第二Si基材料填充为NMOS器件的源极和漏极产生的第一空隙(void)。第一空隙穿透基于Si的层并进入SiGe支撑层。第二Si基材料使得NMOS器件的沟道区处于应变状态，该应变状态与第一应变状态相比被朝着拉伸方向偏移。
该器件结构还包括与基于Si的层以及与SiGe支撑层外延地交界的第二SiGe材料。PMOS器件的源极和漏极由第二SiGe材料制成，该材料具有高于SiGe支撑层的Ge浓度。该第二SiGe材料填充为PMOS器件的源极和漏极产生的第二空隙。第二空隙穿透基于Si的层并进入SiGe支撑层。第二SiGe材料使得PMOS器件的沟道区处于应变状态，该应变状态与第一应变状态相比被朝着压缩方向偏移。
本发明的实施例还公开了制造该器件结构的方法。
附图说明
本发明的这些以及其它特征将从下面的详细描述和附图中变得明显，其中：
图1A和1B以示意截面图示出具有外延源极和漏极的应变器件的实施例变形；
图2示出在器件准备好进行源极/漏极制造的处理阶段中的示意截面图；
图3示出在已经在源极/漏极区域中产生了器件空隙的处理阶段的示意截面图；
图4示出在已经在一个器件中制造了外延源极/漏极的处理阶段的示意截面图；
图5示出在已经在源极/漏极区域中产生了互补器件空隙的处理阶段的示意截面图；
图6示出在已经在一个互补器件中制造了外延源极/漏极的处理阶段的示意截面图。
具体实施方式
本发明的实施例将具有拉伸应变的沟道的NMOS器件的增大了的电子迁移率和具有压缩应变的沟道的PMOS器件的增大了的空穴迁移率结合起来。在本发明的代表性实施例中，NMOS和PMOS的源极和漏极外延生长并具有这样的材料成分，即将NMOS器件的应变状态朝着拉伸方向偏移，而将PMOS器件的应变状态朝着压缩方向偏移。应变的这些偏移是相对于没有外延源极和漏极时在这些器件的沟道中呈现的应变状态的。
图1A和1B以示意截面图示出具有外延源极和漏极的应变器件结构的实施例变形。该器件结构具有NMOS和PMOS结构。在本发明的代表性实施例中，NMOS和PMOS器件连接到CMOS电路配置中，这是现有技术公知的。但是，外延源极/漏极可以用于其它类型的微电子应用，例如模拟电路、存储器等等。
该器件结构的一部分处理按照本领域公知的方式进行，因为NMOS和PMOS器件在电子领域中是高度成熟的。在图1A和1B中，该器件示意性地按照仅显示对展现本发明的代表性实施例有用的部件的方式来示出。相似的元件，如栅极52，在PMOS和NMOS器件上用相同的附图标记表示，当然本领域的技术人员知道NMOS和PMOS中的类似元件可以能在其细节上有所差异。但是，这样的细节对展示本发明的代表性实施例并不重要。
该器件结构由衬底55按照本领域公知的方式支撑。这种衬底在SOI工艺的情况下可以是埋置氧化物层(BOX)，或在块体工艺的情况下是Si衬底，或任何其它公知类型的衬底。在本发明的典型实施例中，衬底还可以包括具有分级Ge浓度的SiGe层。本领域公知，该器件具有栅极52、栅绝缘体53，通常还具有间隔件51。该器件通过隔离结构54如浅沟隔离而彼此隔离。
NMOS和PMOS器件在衬底55上包含弛豫的单晶SiGe支撑层40。该SiGe支撑层40的晶格常数在其与基于单晶Si的层20交界的界面上是确定可在该器件的沟道区中发现的应变水平的分量之一。
本领域公知，当基于Si的层20的Ge含量不同于SiGe支撑层40的Ge含量时，会在基于Si的层20中出现应变。这两个层都是单晶，并且彼此之间处于外延关系，这是因为基于Si的层20外延地沉积在SiGe支撑层40上。在本发明的代表性实施例中，基于Si的层20的厚度在临界厚度以下。层的临界厚度是已清楚定义(well defined)的参数，超过该厚度该层就开始朝着其平衡晶格间距的方向弛豫回来而且形成结构缺陷。临界厚度取决于两个外延层之间的晶格常数差。该差值越大，临界厚度就越小。在典型的实施例中，基于Si的层20的厚度可以在大约10nm至大约70nm之间。由于基于Si的层20的厚度小于临界厚度，因此其平衡应变状态由它和SiGe支撑层40之间的晶格常数差决定。这种平衡应变状态称为第一应变状态，其因为基于Si的层20与SiGe支撑层40的外延关系而为基于Si的层20所固有。
SiGe支撑层40的厚度可以在从大约50nm到几微米的宽范围内变化，这取决于几个因素，如Ge浓度和衬底55的特性。
基于Si的层20是寄宿该器件的层。将器件寄宿在特定材料或层中意思是器件的关键部分，主要是对载流子特性敏感的关键部分如MOSFET器件的沟道，驻留在该特定材料或层中、由该特定材料或层构成、容纳在该特定材料或层中。
在本发明的代表性实施例中，基于Si的层20的Ge含量，如果有的话，小于20％的Ge，而且通常低于SiGe支撑层40的Ge含量。在本发明的代表性实施例中，基于Si的层20本质上是Si。作为基于Si的层20和SiGe支撑层40的相对Ge含量的结果，在基于Si的层中的第一应变状态通常是拉伸应变状态。本领域公知，拉伸应变对NMOS器件可能更有利，但是对PMOS器件却不利。因此，人们期望区分开NMOS和PMOS，并且在这些器件的沟道区中产生附加的应变，使得该附加的应变在NMOS中将第一应变状态朝着拉伸方向偏移，通常使得该NMOS更为拉伸，而在PMOS中将第一应变状态朝着压缩方向偏移，通常使PMOS拉伸较小，或干脆转换为压缩应变状态。
NMOS和PMOS沟道区的应变状态的区分可以通过为每种器件内嵌其自己的源极和漏极来完成，该源极和漏极由适当选择的材料制成。
对于NMOS器件，通过将第二Si基材料30内嵌到基于Si的层20和SiGe支撑层40中来形成源极和漏极。第二Si基材料30与基于Si的层20和SiGe支撑层40处于外延关系，而且与基于Si的层20和SiGe支撑层40交界。如果第二Si基材料30含有Ge，则其具有低于SiGe支撑层40的Ge含量。第二Si基材料30的Ge含量通常低于大约20％。在本发明的示例性实施例中，第二Si基材料本质上是Si。
第二Si基材料30实质地填在空隙中，该空隙称为第一空隙31(图3)，这些空隙是专门为NMOS器件的源极和漏极产生的。在本发明的示例性实施例中，第二Si基材料30完全填充在第一空隙31中。位于源极和漏极位置上的原材料被去除到使得第一空隙31穿透基于Si的层20并进入SiGe支撑层40的程度。第二Si基材料30外延地沉积到该空隙中，由此产生新的单晶材料源极/漏极。
当在SiGe支撑层40的空隙中形成第二Si基材料30时，第二Si基材料30的原子伸展以便将其自身与SiGe支撑层40较大的晶格结构对齐，从而导致在源极/漏极区域中SiGe支撑层40的拉伸应变。该拉伸应变又传递到沟道区并且使该沟道区伸展。只要涉及NMOS器件沟道，SiGe支撑层40中由于内嵌的第二Si基材料30所引起的拉伸应变就与最初存在的第一应变状态结合，其最终结果是将第一应变状态朝着拉伸方向偏移。对于NMOS器件的电特性，主要是电子的迁移率，这种朝着更为拉伸的状态的偏移正是追求的结果：导致电子迁移率的增加。
对于PMOS器件，通过将第二SiGe材料10内嵌到基于Si的层20和SiGe支撑层40中来形成源极和漏极。该第二SiGe材料10与基于Si的层20和SiGe支撑层40处于外延关系而且与基于Si的层20和SiGe支撑层40交界。第二SiGe材料10通常具有高于SiGe支撑层40的Ge含量。
第二SiGe材料10实质地填在空隙中，该空隙称为第二空隙11(图5)，这些空隙是专门为PMOS器件的源极和漏极产生的。在本发明的示例性实施例中，第二SiGe材料10完全填充在第二空隙11中。位于源极和漏极位置上的原材料被去除到使得第二空隙11穿透基于Si的层20并进入SiGe支撑层40的程度。第二SiGe材料10外延地沉积到该空隙中，由此产生新的单晶材料源极/漏极。
当第二SiGe材料10形成在SiGe支撑层40的空隙中时，第二SiGe材料10的原子被压缩以便将其自身与SiGe支撑层40的较小的晶格结构对齐，从而导致在源极/漏极区域中的压缩应变。该压缩应变又传递到该沟道区并且压缩该沟道区。只要涉及PMOS器件沟道，由于内嵌的第二SiGe材料10所引起的压缩应变就与最初存在的第一应变状态结合，其最终结果是将第一应变状态朝着压缩方向偏移。对于PMOS器件的电特性，主要是空穴的迁移率，这种朝着更为压缩的状态的偏移正是追求的结果：导致空穴迁移率的增加。
详细的模拟示出用内嵌外延的源极和漏极可实现的应变偏移可以非常明显。在本发明的代表性实施例中，SiGe支撑层40的Ge含量可以是20％，基于Si的层20可以本质上是Si。详细的数字模拟显示在NMOS源极/漏极中嵌入本质上也是Si的第二Si基材料30会使得在栅绝缘体正下方的沟道中的拉伸应变朝着更高度拉伸的状态偏移，从而使拉伸应变增加大约30％。如果在该沟道的边缘即在所谓的间隔件区域中也包含这种应变，则该偏移超过50％。对于PMOS器件，通过本质上为Si的相同的基于Si的层20以及具有20％Ge的相同的SiGe支撑层40，并且在源极/漏极中嵌入具有40％Ge的第二SiGe材料10，详细的模拟显示在栅绝缘体正下方的拉伸应变减小了大约20％。如果在PMOS沟道的边缘即在所谓的间隔件区域中也包含这种应变，则该偏移超过30％。第二SiGe材料10的更高的Ge含量使得在栅绝缘体之下的沟道的最初第一应变状态朝着压缩方向偏移。
通常，应变状态的偏移反映了应变的材料的晶格常数的变化。人们可以用应变的材料的晶格常数的相应改变来表征应变状态的偏移。各种SiGe合金都具有介于弛豫Si的晶格常数0.5431nm和弛豫Ge的晶格常数0.5646nm之间的晶格常数。因此，很自然地用晶格常数的变化来表征应变状态的变化，其中该晶格常数的变化表达为弛豫Ge晶格常数和弛豫Si晶格常数之间的差异的一部分。在本发明的代表性实施例中，由于在源极/漏极结中嵌入适当选择的Ge浓度而带来的应变状态的期望偏移在绝对项(absolute term)方面对应于晶格常数的变化，该晶格常数的变化为弛豫Ge晶格常数和弛豫Si晶格常数之间的差异的至少3％。但是，在本发明的示例性实施例中可以明显超过该值。
根据特定实施例的需要，SiGe支撑层40的成分可以在很宽的范围内变化，基本上是Ge浓度从大约15％变到大约85％。还有可能基于Si的层20碰巧具有与SiGe支撑层40相同的成分。在这种情况下，很清楚，在SiGe支撑层40和基于Si的层20之间不存在明显的界限。这在本发明的一些实施例中可能如此。例如在测试情况下，SiGe支撑层40和基于Si的层20都本质上是弛豫的Si，作为Si/Ge晶格常数差异的百分比，详细的模拟表明将具有20％Ge的第二SiGe材料10嵌入源极/漏极使得栅极下的压缩应变对应于5％的晶格常数变化，在整个沟道上的平均压缩应变对应于7％的晶格常数变化。
展示本发明的实施例的图显然是示例性的，本领域的技术人员会注意到在细节上会有很多变化。例如，在附图中第二Si基材料30和第二SiGe材料10以及它们各自的空隙31和11都毗邻隔离结构54。附图中的细节如这种毗邻不应当限制性地解释。在本发明的示例性实施例中，在隔离结构54与器件的源极和漏极之间完全可能存在诸如基于Si的层20和SiGe支撑层40的材料。
图1B示出了图1A的变型。在这个被关注的特定实施例中，作为通常可提供的可能性之一，衬底是表示为55’的BOX。在该实施例中，整个器件结构非常浅。由第二Si基材料30和第二SiGe材料10制成的内嵌源极/漏极一直向下到达BOX结构。在该实施例中，内嵌的外延源极和漏极的横向生长可能是重要的。
在展示了本发明的器件结构的代表性实施例之后，其它附图示出处理中的各阶段。仅讨论涉及本发明实施例的步骤。本领域的技术人员应当意识到，这些器件结构的完整处理包括本领域公知的上百个步骤。
图2示出在器件准备好进行源极/漏极制造的处理阶段中的示意截面图。直到此时为止的制造都遵循公知的途径。图2中的间隔件用51’表示而不是图1中的51，以表示它们可能不是相同的间隔件。在制造器件结构的过程中，间隔件经常被构建和去除。示出绝缘层56是为了表示栅极可能在处理期间需要额外的保护。而且，这些元件及其制造也是本领域技术人员公知的。SiGe支撑层40和基于Si的层20已经就位。根据这两层的相对Ge含量，基于Si的层20中的应变实际上可以为任何类型。在嵌入源极和漏极之前，这一阶段的基于Si的层20中的应变状态是第一应变状态。
图3示出在已经在源极/漏极区域中产生了器件空隙的处理阶段的示意截面图。通常，在处理NMOS和PMOS器件时的顺序没有什么因果关系。为了图示，在此假定首先加工NMOS器件。在图3中，已经产生第一空隙31，一个用于源极，一个用于漏极，在第一空隙31上的虚线指出表面最初所在的位置。
通过在源极/漏极区域中蚀刻基于Si的层20和SiGe支撑层40来形成第一空隙31。第一空隙31的深度可以在大约30nm到大约100nm之间，穿透基于Si的层20。第一空隙31通常通过活性离子蚀刻(RIE)形成。RIE蚀刻可以是各向同性或各向异性。在需要紧密靠近沟道的实施例中，优选各向同性的RIE，这可能在间隔件51’之下给出横向的底切(undercut)。为了让其它结构如栅极52完整无缺，RIE优选是选择性的，这在本领域中是公知的。当针对一种类型的器件(在这种情况下是NMOS)进行处理时，通过公知方法来保护61其它的类型，在这种情况下是PMOS。
图4示出了在已经对一个器件制造了外延源极/漏极的处理阶段的示意截面图。第二Si基材料30通过选择性外延沉积在第一空隙31中。术语“外延地”、“外延”等是指它们的惯常用法：采用外延方法来沉积层，而在结构上的含义是在整个界面上采用单晶晶格结构。如果第二Si基材料30包含Ge，则其具有低于SiGe支撑层40的Ge浓度。第二Si基材料30通常具有低于大约20％的Ge浓度。在本发明的代表性实施例中，第二Si基材料30本质上是Si。用于选择性沉积的技术是本领域公知的，可采用的这种技术之一是超高真空化学汽相沉积(UHV-CVD)。用于沉积第二Si基材料30的温度范围可以在大约620℃到大约800℃之间。
图5示出在已经在源极/漏极区域中产生了互补器件空隙的处理阶段的示意截面图。通过在源极/漏极区域中蚀刻基于Si的层20和SiGe支撑层40来形成第二空隙11。第二空隙11上的虚线只是指示表面最初在哪里。第二空隙11的深度可以在大约30nm到大约100nm之间，并穿透基于Si的层20。第一空隙31和第二空隙11的深度，以及作为结果的NMOS和PMOS器件的源极/漏极深度不必与本发明的代表性实施例中的相同。空隙的深度参数可以根据特定需要单独选择。第二空隙11通常通过活性离子蚀刻(RIE)形成。RIE蚀刻可以是各向同性或各向异性。在需要紧密靠近沟道的实施例中，优选各向同性的RIE，这可能在间隔件51’之下给出横向的底切。为了让其它结构如栅极52完整无缺，RIE优选是选择性的，这在本领域中是公知的。当针对一种类型的器件(在这种情况下是PMOS)进行处理时，通过公知方法来保护61’其它的类型，在这种情况下是NMOS。
图6示出在已经在互补器件中制造了外延源极/漏极的处理阶段的示意截面图。第二SiGe材料10通过选择性的外延沉积在第二空隙11中。单晶的第二SiGe材料10包含高于SiGe支撑层40的Ge浓度。第二SiGe材料10通常具有大约20％的Ge浓度。在本发明的代表性实施例中，第二SiGe材料10可以本质上是Ge。用于选择性地沉积的技术是本领域公知的，可采用的这种技术之一是UHV-CVD。用于沉积第二SiGe材料10的温度范围可以在大约550℃到大约750℃之间。
在源极/漏极结的外延生长之后，制造过程可以沿着公知的路径继续。此外，在本发明的代表性实施例中，可以将NMOS和PMOS连接、即耦接到CMOS电路中，这是本领域公知的。
通过上述教导的启示可以进行本发明的很多修改和变型，这对于本领域的技术人员是明显的。本发明的范围由所附权利要求限定。

Claims (18)

1.一种器件结构，包括：
至少一个NMOS器件和至少一个PMOS器件，其中所述至少一个NMOS器件和所述至少一个PMOS器件具有其寄宿在基于Si的层中的对应的沟道区，其中所述基于Si的层是外延的并且与SiGe支撑层交界，其中第一应变状态为所述基于Si的层所固有；
与所述基于Si的层以及与所述SiGe支撑层交界的外延的第二Si基材料，其中所述至少一个NMOS器件的源极和漏极由所述第二Si基材料制成，所述第二Si基材料具有低于所述SiGe支撑层的Ge浓度，所述第二Si基材料实质地填充为所述至少一个NMOS器件的所述源极和所述漏极产生的第一空隙，所述第一空隙穿透所述基于Si的层并进入所述SiGe支撑层，所述第二Si基材料使得所述至少一个NMOS器件的所述沟道区处于应变状态，该应变状态与所述第一应变状态相比被朝着拉伸方向偏移；
与所述基于Si的层以及与所述SiGe支撑层交界的外延的第二SiGe材料，其中所述至少一个PMOS器件的源极和漏极由所述第二SiGe材料制成，所述第二SiGe材料具有高于所述SiGe支撑层的Ge浓度，所述第二SiGe材料实质地填充为所述至少一个PMOS器件的所述源极和所述漏极产生的第二空隙，所述第二空隙穿透所述基于Si的层并进入所述SiGe支撑层，所述第二SiGe材料使得所述至少一个PMOS器件的所述沟道区处于应变状态，该应变状态与所述第一应变状态相比被朝着压缩方向偏移。
2.根据权利要求1的器件结构，其中所述基于Si的层是SiGe，其中Ge的浓度小于大约20％。
3.根据权利要求1的器件结构，其中所述基于Si的层本质上是Si。
4.根据权利要求1的器件结构，其中所述第二Si基材料是SiGe，其中Ge的浓度小于大约20％。
5.根据权利要求1的器件结构，其中所述第二Si基材料本质上是Si。
6.根据权利要求1的器件结构，其中所述基于Si的层的厚度在大约10nm到大约70nm之间。
7.根据权利要求1的器件结构，其中所述第一空隙和所述第二空隙的深度在大约30nm到大约100nm之间。
8.根据权利要求1的器件结构，其中在所述沟道区中的应变状态的偏移的幅度至少为对应的晶格常数变化是弛豫Ge晶格常数和弛豫Si晶格常数之间的差异的至少3％。
9.根据权利要求1的器件结构，其中所述器件结构连接到CMOS电路中。
10.一种用于制造器件结构的方法，包括：
制造至少一个NMOS器件和至少一个PMOS器件，其中所述至少一个NMOS器件和所述至少一个PMOS器件具有其寄宿在基于Si的层中的对应的沟道区，其中所述基于Si的层外延地沉积在SiGe支撑层上，其中第一应变状态为所述基于Si的层所固有；
通过选择性外延将第二Si基材料沉积到为所述至少一个NMOS器件的源极和漏极产生的第一空隙中，其中所述第一空隙穿透所述基于Si的层并进入所述SiGe支撑层，所述第二Si基材料具有低于所述SiGe支撑层的Ge浓度，所述第二Si基材料使得所述至少一个NMOS器件的所述沟道区处于应变状态，该应变状态与所述第一应变状态相比被朝着拉伸方向偏移；以及
通过选择性外延将第二SiGe材料沉积到为所述至少一个PMOS器件的源极和漏极产生的第二空隙中，其中所述第二空隙穿透所述基于Si的层并进入所述SiGe支撑层，所述第二SiGe材料具有高于所述SiGe支撑层的Ge浓度，所述第二SiGe材料使得所述至少一个PMOS器件的所述沟道区处于应变状态，该应变状态与所述第一应变状态相比被朝着压缩方向偏移。
11.根据权利要求10的方法，其中所述基于Si的层被选择为SiGe，其中Ge的浓度小于大约20％。
12.根据权利要求10的方法，其中所述基于Si的层被选择为本质上是Si。
13.根据权利要求10的方法，其中将所述第二Si基材料被选择为SiGe，其中Ge的浓度小于大约20％。
14.根据权利要求10的方法，其中所述第二Si基材料被选择为本质上是Si。
15.根据权利要求10的方法，其中所述基于Si的层的厚度被选择为在大约10nm到大约70nm之间。
16.根据权利要求10的方法，其中所述第一空隙和所述第二空隙的深度被选择为在大约30nm到大约100nm之间。
17.根据权利要求10的方法，其中所述第二Si基材料和所述第二SiGe材料的成分被选择为使得在所述沟道区中的应变状态的偏移的幅度至少为对应的晶格常数变化是弛豫Ge晶格常数和弛豫Si晶格常数之间的差异的至少3％。
18.根据权利要求10的方法，其中所述方法还包括将所述器件结构连接到CMOS电路中。
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CN104934375A (zh) * 2014-03-17 2015-09-23 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法

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