TWI383498B - 鰭式場效電晶體裝置的製造方法 - Google Patents
鰭式場效電晶體裝置的製造方法 Download PDFInfo
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Classifications
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Description
本發明係有關於半導體裝置的製造方法,還特別係關於鰭式場效電晶體裝置的製造方法。
雙閘極金屬氧化半導體場效電晶體(double-gate MOSFET)係將兩個閘極結構合併於單一元件中的金屬氧化半導體場效電晶體。由於這種元件的結構包含由基底延伸出的「鰭」,因此亦被稱做鰭式場效電晶體(FinFET)。鰭式場效電晶體可利用一般金屬氧化半導體場效電晶體的技術製造。一般的鰭式場效電晶體係製造於具有絕緣層覆蓋於其上的矽層上,且上述裝置會由絕緣層延伸而出如同矽層之鰭。場效電晶體的通道(channel)係形成於此垂直的鰭中。而雙閘極結構係形成於鰭上。雙閘極結構的優點是,由於在通道兩端上都具有閘極結構,因此閘極結構能夠自通道兩端進行控制動作。而鰭式場效電晶體的優點更包含減少短通道效應(short channel effect)以及增加電流量。其他的鰭式場效電晶體裝置可包含三或更多個有效應的閘極結構。
然而現行的鰭式場效電晶體技術仍有需要克服的問題。例如,一般係利用離子植入製程(ion implantation)形成輕摻雜汲極(lightly doped drain,LDD)。然而,離子植入製程會使鰭具有非均一性的摻雜分佈(non-conformal doping profile)(例如,鰭頂部的摻雜量大於靠近基底之鰭底部的摻雜量)。此非均一性的摻雜分佈可造成包含與短通道效應相關的問題。利用傾斜角度植入技術(tilt implant)可改進非均一性摻雜分佈的問題,但缺點是會造成陰影遮蔽效應(shadowing effect)。而由於浸沒式電漿離子植入技術所具有的離子能量太低,因此無法滿足鰭式場效電晶體裝置其效能所要的需求。
因此需要一種改善製造鰭式場效電晶體裝置的方法。本發明即提供這樣的方法。
為達成上述目的,本發明之實施例提供一種鰭式場效電晶體裝置的製造方法,包括下列步驟:提供一基底,其包含一第一鰭及一第二鰭;形成一第一材料層於該第一鰭上,其中該第一材料層包含一第一種類之雜質;提供一第二種類之雜質於該第二鰭上;以及對該基底進行一高溫製程,該基底包含該第一材料層及該第二種類之雜質。
本發明之另一實施例也提供一種鰭式場效電晶體裝置的製造方法,包括下列步驟:提供一基底,其包含一第一鰭及一第二鰭;形成一磷矽玻璃層於包含該第一鰭之周圍區域的該基底上;進行一氣相製程,於包含該第二鰭之周圍區域的該基底上形成一硼元素之擴散層;以及對包含該磷矽玻璃層及該硼元素之擴散層的基底進行一退火製程,該退火製程使磷元素自該磷矽玻璃層趨入至該第一鰭中,且使硼元素自該硼元素之擴散層趨入至該第二鰭中。
另外,本發明之又一實施例提供一種鰭式場效電晶體裝置的製造方法,包括下列步驟:進行一固相擴散製程將一第一雜質擴散至一半導體基底上之一第一鰭中;以及進行至少一固相擴散製程及一氣相擴散製程,將一第二雜質擴散至該半導體基底上之一第二鰭中。
有關各實施例之製造和使用方式係如以下所詳述。然而,值得注意的是,本發明所提供之各種可應用的發明概念係依具體內文的各種變化據以實施,且在此所討論的具體實施例僅是用來顯示具體使用和製造本發明的方法,而不用以限制本發明的範圍。
以下係透過各種圖示及例式說明本發明較佳實施例的製造過程。此外,在本發明各種不同之各種實施例和圖示中,相同的符號代表相同或類似的元件。
第1圖顯示鰭式場效電晶體裝置100之實施例。鰭式場效電晶體裝置100包含基底102、絕緣層106、鰭104,以及閘極結構108。在一實施例中,基底102包含矽基底。其他適合用作基底之材料的例子包含絕緣層上覆矽(silicon-on-insulator,SOI)、鍺化矽、鍺,及/或半導體材料組成物。絕緣層106可包含形成於基底102上的淺溝槽隔離(shallow trench isolation)結構。淺溝槽隔離孔洞可利用傳統方法,如以微影技術進行圖案化製程後,進行反應式離子蝕刻製程(reactive ion etching)形成。接著利用如氧化物的絕緣材料將孔洞填充。在一實施例中,製程包含利用化學氣相沉積法形成氧化物以填充淺溝槽隔離孔洞,再以化學機械研磨法對氧化物進行平坦化製程。可利用習知之如微影及蝕刻製程(以及整修(trimming)技術)形成鰭104。鰭104可包含矽材料。在一實施例中,可於鰭104形成後進行氧化製程及/或氫退火製程(H2
anneal process)。所進行的氧化製程及/或氫退火製程能夠修補在蝕刻製程中於鰭表面所形成的缺陷。氧化層可以是一犧牲層。鰭104包含鰭式場效電晶體裝置100中的通道。鰭104於標示為104a之位置處可與鰭式場效電晶體裝置100之源極耦接,及/或鰭104在104a之位置處可包括源極。鰭104於標示為104b之位置處可與鰭式場效電晶體裝置100之汲極耦接,及/或鰭104在104b之位置處可包括汲極。一閘極結構108形成於鰭104上。閘極結構108包含閘介電層108a與閘電極層108b。閘介電層108a可利用習知之製程形成。閘介電層108a包含介電材料,如氧化矽(silicon oxide)、氮化矽(silicon nitride)、氮氧化矽(silicon oxinitride),具有高介電係數(high k)的介電材料及/或其組合。具有高介電係數(high k)之介電材料的例子包含矽酸鉿(hafnium silicate)、氧化鉿(hafnium oxide)、氧化鋯(zirconium oxide)、氧化鋁(aluminum oxide),二氧化鉿-三氧化二鋁合金(hafnium dioxide-alumina alloy,HfO2
-Al2
O3
alloy)及/或其組合。閘電極層108b可形成於閘介電層108a上。閘電極層108b可包含多晶矽、矽-鍺(silicon-germanium),包含如鉬、銅、鎢、鈦、鉭、氮化鈦、氮化鉭、矽化鎳、矽化鈷之金屬合成物的金屬材料及/或其他習知適合的導電材料。鰭式場效電晶體裝置100可包含其他額外的結構,如間隔層。
所繪示的閘極結構108顯示鰭式場效電晶體裝置100的雙閘極結構。另外,其他習知不同的鰭式場效電晶體裝置,如具有多於兩個閘極結構的鰭式場效電晶體裝置,亦包含在本發明之相關領域中。鰭式場效電晶體裝置100可利用進行如第2、3、5,及/或第7圖中所描述之方法一或更多次而形成。在一實施例中,鰭式場效電晶體裝置100為包含正摻雜通道(positively doped channel)的P型鰭式場效電晶體裝置(P-FinFET)(P型金屬氧化半導體鰭式場效電晶體裝置(PMOS FinFET))。在一實施例中,鰭104是以如硼元素的P型雜質進行摻雜製程。在其他實施例中,鰭式場效電晶體裝置100為包含負摻雜通道(negatively doped channel)的N型鰭式場效電晶體裝置(N-FinFET)(N型金屬氧化半導體鰭式場效電晶體裝置(NMOS FinFET))。在一實施例中,鰭104是以如磷元素的N型雜質進行摻雜製程。鰭式場效電晶體裝置100可為形成於單一基底上之複數個鰭式場效電晶體裝置中的其中一個,而基底包含N型鰭式場效電晶體裝置及P型鰭式場效電晶體裝置。
第2圖顯示一實施例中,形成鰭式場效電晶體裝置,如第1圖所繪示之鰭式場效電晶體裝置100的製造方法200。方法200可用以摻雜鰭式場效電晶體裝置中的鰭,如第1圖所繪示的鰭104。方法200可用以形成於同一基底上之複數鰭式場效電晶體裝置中的一部分元件,包含對N型鰭式場效電晶體裝置中的鰭,以及鄰接之P型鰭式場效電晶體裝置中的鰭進行摻雜製程。因此方法200可用以在一基底上形成一或多個鰭式場效電晶體裝置中的輕摻雜區(lightly doped drain,LDD),及/或源極/汲極摻雜區。
方法200由步驟202開始,步驟202為提供包含第一鰭及第二鰭之基底。基底實質上可與第1圖中所繪式的基底102相似。第一鰭及/或第二鰭實質上可與第1圖中所繪式的鰭104相似。在一實施例中,第一鰭為N型鰭式場效電晶體裝置中的一部份,第二鰭為P型鰭式場效電晶體裝置中的一部份。
方法200進行至步驟204,一矽玻璃(silica glass)層形成於基底上。具體的說,矽玻璃層係形成於包含第一鰭的區域上或此區域的周圍上。在一實施例中,矽玻璃層係形成於複數鰭上,並利用一般的製程將一或更多鰭上的矽玻璃層移除,而保留第一鰭周圍的矽玻璃層。所形成的矽玻璃層包含第一類型的雜質。雜質可以是正型(positive type)(P型(P-type))或負型雜質(negative type)(N型(N-type))。在一實施例中,雜質類型為N型,而矽玻璃層包含磷矽玻璃(phosphosilicate glass,PSG),或摻雜磷元素的矽玻璃。在此實施例中,N型雜質為磷元素。在其他實施例中,雜質類型為P型,而矽玻璃層可包含硼矽玻璃(borosilicate glass,BSG),或摻雜硼元素的矽玻璃。在此實施例中,P型雜質為硼元素。
方法200進行至步驟206,提供一第二類型之雜質至包含第二鰭形成於其上的基底中。在一實施例中,所提供之雜質係利用沉積包含第二類型之雜質的矽玻璃層於基底上而形成。此矽玻璃層可與如上所述之步驟204中包含第一雜質的矽玻璃層區別。矽玻璃層可利用習知傳統製程如化學氣相沉積法(chemical vapor deposition)、電漿輔助(plasma enhanced)化學氣相沉積法,物理氣相沉積法及/或其他習知之沉積方法形成。在一實施例中,包含在矽玻璃層內的雜質為P型雜質。P型雜質為硼元素,而所沉積的矽玻璃層為磷矽玻璃。
在其他實施例中,是利用氣相製程(vapor phase processing)將雜質擴散至基底中。在氣相製程中,可將具氣體型態(gaseous form)的雜質提供至基底的周圍環境。由於濃度梯度(concentration gradient)因素,雜質會擴散至基底中,而在基底的表面形成一擴散層(包含擴散雜質的材料層)。在一實施例中,可利用習知傳統的氣相製程進行擴散製程。擴散製程的時間及溫度參數會隨著雜質種類的不同而改變。所提供的雜質可以是N型或P型雜質。在一實施例中,雜質為N型雜質,且雜質為磷元素。其他可能之N型雜質的例子包含砷元素(arsenic)及銻元素(antimony)。在其他實施例中,雜質為P型雜質,且雜質為硼元素。其他可能之P型雜質的例子包含鋁元素。
方法200繼續進行至步驟208,對基底進行高溫製程,如退火製程中。步驟208可包含快速熱退火製程(rapid thermal anneal,RTA)。在一實施例中,是以接近1000℃的溫度下進行快速熱退火製程約10秒鐘。退火製程可將雜質驅動至第一鰭及/或第二鰭中。退火製程使雜質自於步驟204中所形成的矽玻璃層中以固相擴散(solid phase diffusion)(趨入(drive-in))至基底上的第一鰭中。退火製程亦可對於步驟204中進行氣相擴散時所導入的雜質做趨入製程。在一實施例中,方法200進行至步驟208開始,會將基底上一或更多的材料層,例如在步驟204中所形成的矽玻璃層移除。
另外,方法200可以不同的順序進行。方法200也可包含未被敘述如上的步驟,例如形成其他的材料層,如保護氧化層(protective oxide layer);移除材料層,如在退火製程、預先非晶化摻雜(pre-amorphization implant,PAI)製程,及/或其他習知之製程後將矽玻璃層移除;方法200可包含繼續在基底上形成一或更多的閘極結構。閘極結構實質上可與第1圖中所繪示的閘極結構108相似。
第3圖顯示對鰭式場效電晶體裝置進行摻雜製程的方法300,其為第2圖所顯示之方法200中的一實施例;第4a、4b、4c、4d、4e,及4f圖顯示基底400在進行第3圖中的方法300時可能會有的構造變化。方法300起始於步驟302,提供一含有第一鰭及第二鰭的基底。請參考第4a圖所顯示的例子,提供一基底400。基底400實質上可與第1圖中所繪示的基底100相似。位於基底上的結構為淺溝槽隔離區402a、402b,及402c。為形成淺溝槽隔離區402a、402b,及402c,可利用傳統製程對基底400進行圖案化及蝕刻製程以形成孔洞;接著可以絕緣材料,如氧化物將孔洞填充。在一實施例中,製程包含利用一般的低壓化學氣相沉積法沉積氧化物,以填充淺溝槽隔離孔洞,再以化學機械研磨法對氧化物進行平坦化。鰭404及鰭406係位在基底400上。第一鰭404及第二鰭406實質上可與第1圖中所繪示的鰭104相似。在一實施例中,基底400,鰭404及鰭406包含矽材料。在所說明的實施例中,鰭404為N型鰭式場效電晶體裝置中的一部份,鰭406為P型鰭式場效電晶體裝置中的一部份。鰭406可被摻雜以形成P型鰭式場效電晶體裝置中的通道;而鰭404被摻雜以形成N型鰭式場效電晶體裝置中的通道。
方法300進行至步驟304,於基底上形成一磷矽玻璃層(phosphosilicate glass,PSG)。在第4a圖所顯示的例子中,磷矽玻璃層408係沉積於基底400上。磷矽玻璃層408圍繞著鰭406及鰭404。磷矽玻璃層408可包含以電漿輔助技術所形成的磷矽玻璃材料(plasma-enhanced PSG,PE-PSG)。在一實施例中,以電漿輔助技術所沉積的磷矽玻璃層其厚度為約500至1000。方法300進行至步驟306,將在P型鰭式場效電晶體裝置區域的磷矽玻璃層,特別是在P型鰭式場效電晶體裝置中之鰭區域的磷矽玻璃層移除。在第4b圖所顯示的例子中,將鰭406之周圍區域的磷矽玻璃層408移除。鰭406之周圍區域包含P型鰭式場效電晶體裝置之區域,例如,P型鰭式場效電晶體裝置之源極及汲極區域。可利用如微影技術進行圖案化製程,再進行濕式或乾式蝕刻製程的傳統方法將磷矽玻璃層408移除。
方法300進行至步驟308,於基底上形成一氧化層。在方法300中的一實施例中,步驟308係被省略的。在第4c圖所顯示的例子中,氧化層410係形成於基底400上。在一實施例中,所形成的氧化層其厚度為約10至約30。氧化層410可以係成長(growing)氧化層,沉積(depositing)氧化層及/或以其他習知之方法形成。
方法300進行至步驟310,具有氣相型態的硼元素被導入至基底中。含有硼元素的擴散層係利用氣相製程(摻雜製程)將硼元素擴散至基底中而形成。在第4d圖所顯示的例子中,含有硼元素的擴散層412係形成於基底400上。擴散層的性質,包括厚度,是取決於擴散製程中所設定的時間及溫度而定。
方法300進行至步驟312,對基底進行退火製程。所進行的退火製程可使存在於磷矽玻璃層內的雜質做固相擴散(趨入)的動作。退火製程亦可趨動存在於擴散層內的雜質。請參考第4e圖所繪示的例子,退火製程能使存在於磷矽玻璃層408內的磷元素固相擴散至鰭404中標示為404a的區域中。退火製程亦可使存在於擴散層412內的硼元素趨入至鰭406中標示為406a的區域中。因此,鰭404為N型摻雜的(N-doped),而鰭406為P型摻雜的(P-doped)。就以上所述之內容而論,方法300所提供的固相擴散製程能夠形成N型金氧半導體鰭式場效電晶體裝置中的一部份,而方法300所提供的氣相擴散製程能夠形成P型金氧半導體鰭式場效電晶體裝置中的一部份。
方法300進行至步驟314,將磷矽玻璃層及/或氧化層自基底移除。在方法300之一實施例中,步驟314係被省略的。請參考第4f圖所繪示的例子,磷矽玻璃層408及氧化層410移除自基底400。在所說明的實施例中,淺溝槽隔離結構402b及402c係於基底400進行蝕刻製程以移除部份氧化層410而形成的。
第5圖顯示製造鰭式場效電晶體裝置的方法500,其為第2圖所顯示之方法200中的一實施例;第6a、6b、6c、6d,及6e圖顯示基底600在進行第5圖中的方法500時可能會有的構造變化。
方法500起始於步驟502,提供一包含第一鰭及第二鰭之基底。請參考第6a圖所繪示的例子,提供一基底600。基底600實質上可與第1圖中所繪式的基底100相似。位於基底上的結構為淺溝槽隔離區602a,602b及602c。為形成淺溝槽隔離區602a,602b及602c,可利用傳統製程對基底600進行圖案化及蝕刻製程以形成孔洞;接著可以絕緣材料,如氧化物將孔洞填充。在一實施例中,製程包含利用一般的低壓化學氣相沉積法沉積氧化物,以填充淺溝槽隔離孔洞,再以化學機械研磨法對氧化物進行平坦化。鰭604及鰭606位於基底600上。第一鰭604及/或第二鰭606實質上可與第1圖中所繪示的鰭104相似。在一實施例中,基底600,鰭604及鰭606包含矽材料。在所說明的實施例中,鰭604為N型鰭式場效電晶體裝置中的一部份,鰭606為P型鰭式場效電晶體裝置中的一部份。鰭604可以雜質摻雜以形成N型鰭式場效電晶體裝置中的通道;而鰭606可以雜質摻雜以形成P型鰭式場效電晶體裝置中的通道。
方法500進行至步驟504,於基底上形成一磷矽玻璃(phosphosilicate glass,PSG)層。在第6a圖所顯示的例子中,磷矽玻璃層608係沉積於積底600上且包圍著鰭606及鰭604。磷矽玻璃層608可包含以電漿輔助技術所形成的磷矽玻璃材料(plasma-enhanced PSG,PE-PSG)。在一實施例中,以電漿輔助技術所沉積的磷矽玻璃層其厚度為約500至1000。方法500進行至步驟506,將在P型鰭式場效電晶體裝置區域的磷矽玻璃層,特別是在P型鰭式場效電晶體裝置中之鰭周圍區域的磷矽玻璃層移除。在第6b圖所顯示的例子中,是將鰭606之周圍區域的磷矽玻璃層608移除。鰭606之周圍區域包含P型鰭式場效電晶體裝置之區域,例如,P型鰭式場效電晶體裝置之源極及汲極區域。可利用如微影技術進行圖案化製程,再進行濕式或乾式蝕刻製程的傳統方法將磷矽玻璃層608移除。
方法500進行至步驟508,硼矽玻璃(borosilicate glass,BSG)層形成於基底上,包含在基底之第二鰭或其周圍上。在第6c圖所顯示的例子中,硼矽玻璃層610係形成於基底600上。在一實施例中,硼矽玻璃層610係利用電漿輔助技術所形成的硼矽玻璃層。方法500進行至步驟510,對基底進行退火製程。所進行的退火製程可使存在於磷矽玻璃層及硼矽玻璃層內的雜質進行固相擴散(趨入)的動作。在第6d圖所繪示的例子中,退火製程能使存在於磷矽玻璃層608內的磷元素固相擴散至鰭604中,而形成摻雜區域604a。退火製程亦可使存在於硼矽玻璃層610內的硼元素趨入至鰭606中,而形成摻雜區域606a。因此,鰭604成為N型摻雜的(N-doped),而鰭606成為P型摻雜的(P-doped)。所以,方法500所提供的固相擴散製程能夠形成N型金氧半導體鰭式場效電晶體裝置中的一部份,以及P型金氧半導體鰭式場效電晶體裝置中的一部份
方法500進行至步驟512,將磷矽玻璃層及/或硼矽玻璃層自基底移除。在方法500之一實施例中,步驟512係被省略的。請參考第6e圖所繪示的例子,磷矽玻璃層608及硼矽玻璃層610自基底600移除。在所說明的實施例中,淺溝槽隔離結構602b及602c自基底400移除部份硼矽玻璃層610。
第7圖顯示製造鰭式場效電晶體裝置的方法700,其為第2圖所顯示之方法200中的其他實施例;第8a、8b、8c、8d、8e,及8f圖顯示基底800在進行第7圖中的方法700時可能會有的構造變化。
方法700起始於步驟702,提供一包含第一鰭及第二鰭之基底。請參考第8a圖所繪示的例子,提供一基底800。基底800實質上可與第1圖中所繪式的基底100相似。位於基底上的結構為淺溝槽隔離區802a,802b及802c。為形成淺溝槽隔離區802a,802b及802c,可利用傳統製程對基底800進行圖案化及蝕刻製程以形成孔洞;接著可以絕緣材料,如氧化物將孔洞填充。在一實施例中,製程包含利用一般的低壓化學氣相沉積法沉積氧化物,以填充淺溝槽隔離孔洞,再以化學機械研磨法對氧化物進行平坦化。鰭804及鰭806被裝置在基底800上。第一鰭804及/或第二鰭806實質上可與第1圖中所繪示的鰭104相似。在一實施例中,基底800,鰭804及鰭806包含矽材料。在所說明的實施例中,鰭804為N型鰭式場效電晶體裝置中的一部份,鰭806為P型鰭式場效電晶體裝置中的一部份。鰭804可成為N型鰭式場效電晶體裝置;而鰭806可成為P型鰭式場效電晶體裝置。
方法700進行至步驟704,於基底上形成一硼矽玻璃(borosilicate glass,BSG)層。在第8a圖所顯示的例子中,硼矽玻璃層808係沉積於基底800上。硼矽玻璃層808包圍著鰭806及鰭804。硼矽玻璃層808可包含以電漿輔助技術所形成的硼矽玻璃材料(plasma-enhanced BSG,PE-BSG)。方法700進行至步驟706,將在N型鰭式場效電晶體裝置區域的硼矽玻璃層,特別是在N型鰭式場效電晶體裝置中之鰭周圍區域的硼矽玻璃層移除。在第8b圖所顯示的例子中,是將鰭804之周圍區域的硼矽玻璃層808移除。鰭806之周圍區域包含N型鰭式場效電晶體裝置之區域,例如,N型鰭式場效電晶體裝置之源極及汲極區域。可利用如微影技術進行圖案化製程,再進行濕式或乾式蝕刻製程的傳統方法將硼矽玻璃層808移除。
方法700進行至步驟708,進行一預先非晶化摻雜(pre-amorphization implant,PAI)製程。預先非晶化摻雜製程可對表面提供一粗糙度。請參考第8c圖所顯示的例子,可形成一粗糙化區域(roughening area)810。方法700進行至步驟710,具有氣相型態之磷元素被導入至基底中。含有磷元素的擴散層係利用於基底上進行氣相製程(vapor phase process)(摻雜製程(doping process))的方式形成。在第8d圖所顯示的例子中,擴散層812係形成於包含在鰭806周圍區域的基底800上。
方法700進行至步驟712,對基底進行退火製程。所進行的退火製程能使存在於硼矽玻璃層內的雜質固相擴散至鰭中,如同將擴散層內的雜質趨入基底上的鰭中。請參考第8e圖所繪示的例子,退火製程亦可使存在於硼矽玻璃層808內的硼元素固相擴散至至鰭806中所標示的摻雜區域806a。而退火製程亦可使存在於擴散層812內的磷元素固相擴散至至鰭804中所標示的摻雜區域804a。因此,鰭804為N型摻雜的(N-doped),而鰭806為P型摻雜的(P-doped)。因此,方法700所提供的固相擴散製程能夠形成P型金氧半導體鰭式場效電晶體裝置中的一部份,而方法700所提供的氣相擴散製程能夠形成N型金氧半導體鰭式場效電晶體裝置中的一部份。
方法700進行至步驟714,將硼矽玻璃層自基底移除。在方法700之一實施例中,步驟714係被省略的。請參考第8f圖所繪示的例子,硼矽玻璃層808係自基底800被移除。在所說明的實施例中,淺溝槽隔離結構802b及802c被部份蝕刻。所進行的部份蝕刻製程可移除剩餘的磷元素。
雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何熟悉此項技藝者,在不脫離本發明之精神和範圍內,當可做些許更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100...鰭式場效電晶體裝置
102、400、600、800...基底
104、104a、104b、404、406、604、606、804、806...鰭
106...絕緣層
108...閘極結構
108a...閘介電層
108b...閘電極層
402a、402b、402c、602a、602b、602c、802a、802b、802c...淺溝槽隔離區
404a、406a、604a、606a、804a、806a...摻雜區
408、608...磷矽玻璃層
410...氧化層
412、812...擴散層
610、808...硼矽玻璃層
810...粗糙化區域
第1圖顯示本發明之實施例中的鰭式場效電晶體裝置其透視圖。
第2圖為本發明之實施例中製造鰭式場效電晶體裝置的方法流程圖。
第3圖為第2圖中方法之實施例的流程圖。
第4a-4f圖為第2圖中方法之實施例的剖面圖。
第5圖為第2圖中方法之實施例的流程圖。
第6a-6e圖為第5圖中方法之實施例的剖面圖。
第7圖為第2圖中方法之實施例的流程圖。
第8a-8f圖為第7圖中方法之實施例的剖面圖。
100...鰭式場效電晶體裝置
102...基底
104...鰭
104a...鰭
104b...鰭
106...絕緣層
108...閘極結構
108a...閘介電層
108b...閘電極層
Claims (17)
- 一種鰭式場效電晶體裝置的製造方法,包括下列步驟:提供一基底,其包含一第一鰭及一第二鰭;形成一第一材料層於該第一鰭上,其中該第一材料層包含一第一種類之雜質;形成一氧化層於該第一材料層及該第二鰭上;提供一第二種類之雜質於該第二鰭上,其中提供該第二種類的雜質的製程包含利用氣相製程將該第二種類的雜質擴散至該氧化層中;以及在形成該第一材料層並提供該第二種類的雜質之後,對該基底進行一高溫製程,該基底包含該第一種類之雜質及該第二種類之雜質。
- 如申請專利範圍第1項所述之鰭式場效電晶體裝置的製造方法,其中該基底所進行之該高溫製程使該第一種類之雜質趨入至該第一鰭中,且使該第二種類之雜質趨入至該第二鰭中。
- 如申請專利範圍第1項所述之鰭式場效電晶體裝置的製造方法,其中該第一鰭包含一N型鰭式場效電晶體裝置之一通道,且該第二鰭包含一P型鰭式場效電晶體裝置之一通道。
- 如申請專利範圍第1項所述之鰭式場效電晶體裝置的製造方法,其中該第一材料層的製造方法包含:沉積一矽玻璃層於包含該第一鰭之周圍區域及該第 二鰭之周圍區域的基底上;以及蝕刻該矽玻璃層,以移除該第二鰭之周圍區域的該矽玻璃層。
- 如申請專利範圍第4項所述之鰭式場效電晶體裝置的製造方法,其中該矽玻璃層包含硼矽玻璃材料。
- 如申請專利範圍第4項所述之鰭式場效電晶體裝置的製造方法,其中該矽玻璃層包含磷矽玻璃材料。
- 如申請專利範圍第1項所述之鰭式場效電晶體裝置的製造方法,其中更包含:於該高溫製程後,自該基底移除該第一材料層。
- 如申請專利範圍第1項所述之鰭式場效電晶體裝置的製造方法,其中該第二種類之雜質包含硼元素。
- 如申請專利範圍第1項所述之鰭式場效電晶體裝置的製造方法,其中該第二種類之雜質包含磷元素。
- 如申請專利範圍第1項所述之鰭式場效電晶體裝置的製造方法,更包含:在提供該第二種類之雜質前,進行一預先非晶化摻雜製程。
- 如申請專利範圍第1項所述之鰭式場效電晶體裝置的製造方法,其中該高溫製程包含一快速熱退火製程。
- 一種鰭式場效電晶體裝置的製造方法,包括下列步驟:提供一基底,其包含一第一鰭及一第二鰭;形成一磷矽玻璃層於包含該第一鰭之周圍區域的該 基底上;形成一氧化層於該基底上,其中該氧化層是形成於包含該第二鰭的周圍區域的該基底上;進行一氣相製程,以將硼元素擴散至形成於包含該第二鰭之周圍區域的該基底上的該氧化層中而形成一硼元素之擴散層;以及對包含該磷矽玻璃層及該硼元素之擴散層的基底進行一退火製程,該退火製程使磷元素自該磷矽玻璃層趨入至該第一鰭中,且使硼元素自該硼元素之擴散層趨入至該第二鰭中。
- 如申請專利範圍第12項所述之鰭式場效電晶體裝置的製造方法,其中該氧化層是形成於該磷矽玻璃層上。
- 如申請專利範圍第13項所述之鰭式場效電晶體裝置的製造方法,其中該氧化層之厚度介於約10 Å至約30 Å。
- 如申請專利範圍第12項所述之鰭式場效電晶體裝置的製造方法,其中該磷矽玻璃層之厚度介於約500 Å至約1000 Å。
- 如申請專利範圍第12項所述之鰭式場效電晶體裝置的製造方法,其中進行該退火製程之該基底形成一N型摻雜的第一鰭及一P型摻雜的第二鰭;該N型摻雜的第一鰭包含一N型金氧半導體鰭式場效電晶體裝置中的一通道,該P型摻雜的第二鰭包含一P型金氧半導體鰭 式場效電晶體裝置中的一通道。
- 一種鰭式場效電晶體裝置的製造方法,包括下列步驟:將一氧化層設置於一半導體基底上的一第一鰭上;進行一氣相擴散製程,將一第一雜質擴散至該半導體基底上的該氧化層中;以及進行一固相擴散製程將一第二雜質擴散至該半導體基底上的一第二鰭中,並同時將該氧化層中的該第一雜質擴散至該第一鰭中。
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US8883597B2 (en) | 2014-11-11 |
TW200905875A (en) | 2009-02-01 |
CN104037086B (zh) | 2018-04-24 |
CN104037086A (zh) | 2014-09-10 |
CN101359622A (zh) | 2009-02-04 |
US20090035909A1 (en) | 2009-02-05 |
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