TW200849405A - Semiconductor structure and method for forming a semiconductor device - Google Patents

Semiconductor structure and method for forming a semiconductor device Download PDF

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Publication number
TW200849405A
TW200849405A TW096137427A TW96137427A TW200849405A TW 200849405 A TW200849405 A TW 200849405A TW 096137427 A TW096137427 A TW 096137427A TW 96137427 A TW96137427 A TW 96137427A TW 200849405 A TW200849405 A TW 200849405A
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Taiwan
Prior art keywords
substrate
dielectric material
layer
semiconductor
item
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TW096137427A
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Chinese (zh)
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TWI362076B (en
Inventor
Mong-Song Liang
Tze-Liang Lee
Kuo-Tai Huang
Chao-Cheng Chen
Hao-Ming Lien
Chih Tang Peng
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Taiwan Semiconductor Mfg
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Publication of TW200849405A publication Critical patent/TW200849405A/en
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Publication of TWI362076B publication Critical patent/TWI362076B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7846—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the lateral device isolation region, e.g. STI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A semiconductor structure is disclosed. An isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the surface with the surface of the substrate. The dielectric material is then recessed below the surface of the substrate. In the recessed portion of the trench, the dielectric material may remain along the sidewalls or the dielectric material may be removed along the sidewalls. A stress film, either tensile or compressive, may then be formed over the dielectric material within the recessed portion. The stress film may also extend over a transistor or other semiconductor structure.

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200849405 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體元件，且特別是有關於 一種金氧半導體場效電晶體（metal oxide semiconductor field effect transistor，以下可簡稱M0SFET)和其製造方 法0 【先前技術】 在過去數年間，尺寸之微縮（包括閘極長度和閘極氧 化層厚度之縮減）係使金氧半導體場效電晶體持續改進速 度、效能、電路密度和單位功能之成本。爲進一步增進 電晶體之效能，金氧半導體場效電晶體係應用於半導體 基底中的應變通道區，於通道區施加應變可使載子之移 動速率增加，因此，使得N通道金氧半導體場效電晶體 (NM0SFET)和P通道金氧半導體場效電晶體（PMOSFET) 增加效能。一般來說，沿源極至没極方向施加張應力於N 型金氧半導體場效電晶體之N通道，可增加電子移動 率，沿源極至汲極方向施加壓應力於P型金氧半導體場 效電晶體之P通道，可增加電洞移動率。現已發展出許 多導引應變至電晶體通道區之方法。 在習知技術之一方法中，例如石夕-鍺或石夕-鍺-碳之半 導體混合層係形成於一薄半導體層下，其中半導體混合 層之晶格結構和其上之半導體層不同，而晶格結構之不 同，使其上之半導體層產生應變，增加載子移動率。 0503-A3 3166TWF/wayne 5 200849405 老、此形成毯覆之半導體混合層的方法，除了需 接面漏電流，亦難以進行。舉例來說，i晶成長石夕 石ί之半㈣混合層花費成本較高，且難以精確的控制 半導體混合層中之鍺的程度。此外，半導體混 口二的存在會於源極"及極區之接面產生不需要的接面， 進而可能產生接面漏電流。 變導之成電晶體後，將應 部梦基底之電晶體=構:r::應力薄膜係形成於全 • 、、σ構上方，咼應力薄膜或應變條係於 丄1:顯著的影響’調整通道區之矽晶格間距，因 體-構通道區。另外’應變條係放置於整個電晶 度，改進元件之效能。 胰之’予 成高:二：施加的應力量係受限，舉例來說，藉由形 πW Λ 、施加之應力，受限於後續的埴洞能力和# 刻製程範圍。 /、糾此力和蝕 【發明内容】 根據上述問題，本發明目的為提供一有效 的方法，可㈣額外的應變，以增加電晶體之效能。 基底ΐ發:=了種半導體結構。-絕緣溝槽形成於- ^ /、中至ν 分絕緣溝槽填入介電材料，且奶缕 溝槽中，至少部份介 且、、、巴、、彖 之ί 叙頂部表面㈣至低於基底 以表面―笔晶體間極位於基底上方，—接觸飯刻 0503-A33166TWF/wayne 6 200849405 p撐層位於基底和絕緣溝槽巾之介電材料上方。 本發明提供—種半導體結 一基底中，1中、气、秦姑 久屏6、*巴緣形成於 槽。一凹#位、;絕、緣包括—填人介電材料之溝 凹槽中和基底上。 任啁蝕刻阻擋層位於 本發明提供一種半導體結構。一基底且 μ 部側邊和一相對之第一 ，-二 弟一頂 形成-絕緣溝槽，絕緩、盖诚、t 1 &於第一頂部侧邊 冬屏彳日、纟巴緣溝槽至少部份填入一介帝 至少部份介電材料之頂、 私；' 角。一電晶體位/11緣溝槽之上部邊 基底上方。 _方，一應力層位於介電材料和 步驟本ΪΖ::種半導體元件之製造方法，包括以下 後續埴入—入2 —基底，並形成一絕緣溝槽於基底中。 吏、、負，、入—"笔材料於絕緣溝槽 至少部份介電材料之頂邻# > |£3"电材抖，使 面。接m Γ 陷至低於基底之頂部表 μ 成一電晶體閘極於基底上方，並形成一岸 力層，至少覆蓋部份基底和介電材料。 7成應 【實施方式】 而妒：“本發明較佳實施例之製造和使用，然 而’根據本發明之概今， 術範圍。須注意的括或運用於更廣泛之技 使用之特㈣以揭示本發明製造和 w知1不本發明一實施例包括應變通道區 0503-A33166TWF/wayne 200849405 之半導體元件的製造方法，本發明在此所揭示之實施 可應用於各種之電路。首先，請參照第丨圖，其顯示— 部份晶圓100，包括形成於基底Π2中之絕緣溝^曹'u〇。 基底112可包括石夕塊材、摻雜或未換雜基底，或絕緣層 上有石夕基底之主動層。—般來說，絕緣層上有發基底^ 开〆成於、’色4：層上之半導體材料層（例如發）。絕緣層可 如為埋藏氧化層（buded 〇xide ’以下可簡稱Β〇χ)或氧化 矽層。絕緣層一般係形成於矽或玻璃之基底上，另外， 本發明之實施例可使用多層或漸進(gradient)之基底。 使用此技藝所熟知的微影技術形成絕緣溝槽110。一 ，來說’微影技術包括以下步驟：沉積—光阻材料，接 者進行罩幕、曝光和顯影。如« 1圖所示，在圖形化光 ，罩幕後，可進行一蝕刻製程以移除基底112不需要之 部? 1在基底包括梦塊材之較佳實施例中，㈣製程可 以疋絲式或乾式、等向性或非等向性蝕刻製程，惟蝕刻 製程較佳為非等向性之乾㈣製程。在—實施例中，絕 緣屢槽110之深度約為2000埃〜3〇〇〇埃。 第2圖揭示本發明一實施例在絕緣溝槽110埴入絕 緣材，210後之晶圓100。在一實施例中，絕緣材料2i〇 包括氧，製程形成之氧化層，其中氧化製程例如為在一 包括氧氣、水氣、-氧化氮或其組合之環境的濕式或乾 式…、氧化。或者，氧化層可採用化學氣相沉積（cvd)使用 四乙氧基石夕 *元（tetra-ethyl-ortho-silicate，TEOS)和氧氣作 為前趨物形成。 0503-A33166TWF/wayne 8 200849405 之可進行—平坦化步驟’以平坦化絕緣材料210 表面，亚使其和基底n2之頂部表面共面 驟：採用此技藝所熟知的化學機械研磨法⑽二 meChanical pohshmg，以下可簡稱 cmj))。 第3圖揭示本發明-實施例在絕緣材料210中妒虚 晶圓10〇。可進行—固定時間之嫌刻製 王V成凹乜310,例如在—絕緣材料21〇 m表面約細埃〜綱 ^至低於基底 料训浸泡稀釋hF溶液約可將絕緣材 料形成凹槽。 ”5"肩秒，以使絕緣材 =曰4圖揭示本發明一實施例形成電晶體41〇之步 ^。屯日日體410包括閘極介電412、閘電極414、間隙辟 汲極區418。如同—般的技術，形成並圖形2 一間極介電412和一間電極414於基底ιΐ2。 :土匕 極:電為例如氧化梦、氮氧切、氮化 物、含氮氧化物、卜诚人+丄 平^ 1匕 之較佳介電常數約大412 鋁、氧仆襴气儿Λ .另外閑極"電可包括氧化 高介電材料/ A、氧化鍅、氮氧化給或上述組合之 412 包括氧化層之實施例中，閘極介電 产 羊衣程形成，氧化製程例如為在一包括气 氣、水氣、一氧化氮或其組合 括虱 化’或閘極介電可採用化學氣相沉：:：:$ WE0S)和氧氣作為前趨物形成。在本=4: 0503-A33166TWF/wayne 200849405 中，閘極介電412之厚度約為8埃〜5 20埃。 、 矢，較佳厚度約為 較佳閘電極4U包括導電㈣ 化物、金屬氮化物、摻雜多曰 D I屬、金屬石夕 曰曰切、其它道+ 組合。金屬例如為趣、鈦、銦、 、琶材料或上述 金屬矽化物例如為矽化鈦、劢 、’g、給或釕， 金屬氮化物例如為氮化鈦或氣 匕鎳或矽化鈕， 石夕之形成包括沉積一非晶石夕：並二。上:範例中，多晶 多晶石夕。在間電極是多晶發 :石再結晶以形成 麼化學氣相沉積法（LPCVD)沉積;^Y ’可藉由低 矽，形成閘電極414，苴中、、冗并夕曰5 格4之多晶 彻埃〜2500埃，較佳厚度約為貝8〇夕〇曰^之厚度可以約為 採用此技藝所熟知的微影技術圖 和閘電極414，一般來★兒，Θ極；|電412 料，之後對光阻材料進行罩幕、瞧^括，儿知一光阻材 先阻草幕後’可進純刻製程，移 = 4電:刚不必需之部份，以形成閘極介電4=^^^ ’如弟4圖所不。在閘電極材料是多晶矽 ==是氧㈣之較佳實施财，_製程可以是以 t 向性或非等向性钮刻製程，惟較佳崎程 係非等向性乾敍刻製程。 藉由離子佈值製程形成源極/汲極區418，對源極/没 ^ 418佈植N型摻雜物（例如罐、氮、神、録或類似的 貝），以製作NMOS元件，或對源極/汲極區佈植p型 wayne °503-A33l66TWF/' 10 200849405 摻雜物（例如硼、銘、銦或類似的物質），以製作PM〇S 元件。在另一實施例中，需使用此技藝所熟知的多道罩 幕和離子佈植步驟，以僅於特定之區域佈植N型或P型 離子。 間隙壁416較佳包括氮化矽（Si3N4)、其它成分之含 氮層（SixNy ，不包括Si3N4)、氮氧化矽（SiOxNy)、肟化 石夕（silicon oxime，Si〇xNy:Hz)或上述之組合，其中形成 間隙壁係用以於源極/汲極區418進行第二次離子步植。 在一較佳實施例中，係進行化學氣相沉積法（以矽烷和氨 為前趨物）形成包括氮化矽（Si3N4)之層，以製作間隙壁 416。 進行一等向性（例如浸泡填酸H3P04溶液）或非等向 性製程圖形化間隙壁416。在等向性蝕刻形成間隙壁之範 例中，由於氮化砍（Si3N4)層位於閘電極414侧壁的厚度 大於鄰接閘電極414頂部之部份，等向性蝕刻係移除位 於閘電極414頂部之部份氮化矽（Si3N4)材料，和基底112 不直接鄰接閘電極414之另一部份氮化矽（Si3N4)材料， 而保留第4圖所示之間隙壁416。 請注意本實施例尚可進行一矽化製程。使用矽化製 程可改進導電閘電極414之導電率，並減少源極/汲極區 418之阻抗。矽化製程可包括以下步驟··以物理氣相沉積 法（physical vapor deposition，PVD)沉積一例如鈦、錄、 鎢或鈷之金屬層。接著進行一回火製程，使金屬層與導 電閑電極414和源極/>及極區418反應’以形成金屬砍化 0503-A33166TWF/wayne 11 200849405 物，而部份位於絕緣間隙壁416上之金屬層係未反應， 可採用例如濕蝕刻製程選擇性的移除金屬層未反應之部 份。若需要，可進行額外的回火製程，改變矽化區之相， 以降低電阻。 請注意以上所描述係為應用於本發明一實施例之電 晶體410範例，本發明可使用其它電晶體和半導體元件。 舉例來說，電晶體可包括凸起之源極/汲極，電晶體可以 為分離閘極（split gate)電晶體或鰭式電晶體（FinFET)之設 ^ 計。另外，本發明可採用不同的材料和厚度。此外，本 發明可於間隙壁和閘電極間可形成襯層。本發明另可使 用複合間隙壁，或使用不同的摻雜剖面，或類似製程。 第5圖揭示本發明一實施例形成高應力薄膜510後 之晶圓100,其中高應力薄膜覆蓋電晶體410和絕緣溝槽 110之凹槽310(在此實施例中高應力薄膜510可以為接觸 蝕刻阻擋層）。請注意高應力薄膜510可以是張應力或壓 應力。張應力薄膜會於通道區產生張應變，增加N通道 、 電晶體之電子移動率，而壓應力薄膜會於通道區產生壓 應變，增加P通道電晶體之電洞移動率。 採用例如化學氣相沉積法（CVD)、物理氣相沉積法 (PVD)、原子層沉積法（atomic layer deposition，ALD)或 類似之製程形成高應力薄膜510。張應力薄膜之較佳厚度 約為5nm〜500nm，且其大體上沿著源極至没極方向施加 OGPa〜5GPa之應力。壓應力薄膜之較佳厚度約為 5nm〜500nm，且其大體上施加OGPa〜_5GPa之應力。適用 0503-A33166TWF/wayne 12 200849405 於張應力薄膜之材料包括氮化石夕（SiN)、氧化物、氣 物、、碳化石夕（sic)、碳氮化石夕（SiCN)、矽化鎳、矽二二、 上述之組合或類似之物質。適用於壓應力薄膜之材 括錯化石夕（SiGe)、氮鍺化石夕（SiGeN)、氧化物、化匕 上述之組合或類似之物質。 物、 請注意高應力薄膜510可包括複數層相同或不同之 材料，或是相同或不同應力特性之材料。本發明之實施 例可用於製造包括NM0S* PM〇s元件之晶圓，例如， 可藉由熟知的沉積和圖形化技術於同一晶圓上，分別製 作具有張應力薄膜之NM0S電晶體和壓應力薄膜: PMOS電晶體，可使電晶體依特定之功能製作。 狀後績，可採用標準製程完成半導體元件之製作和封 才例如了 士成和圖形化接觸|虫刻阻擋層（可選擇）、舞 間介電層和金屬層，另外可形成其它電路，切割和封^ 晶圓。 ^ 第“圖揭示本發明另—實施例形之晶圓跡第6_8 ，所揭示此實施例之晶圓200的初始元件，如第u圖之 乾例所揭示，請注意此實施例與第1-2圖範例類似之 採用相同之符號。 首先請參照第6圖，其顯示本發明一實施例，絕緣 =科2! 〇凹陷後之晶圓2 〇 〇。在此實施例中，雖然絕緣材 210係凹陷’沿著凹槽31()之絕緣溝槽㈣的側壁， ，保留部份絕緣材料21〇。其凹槽310可採用例如上述之 4影技術形成。在此實施射，可形成和圖形化光阻材 0503-A33166TWF/wayne 13 200849405 ，’至暴露絕緣溝槽11〇之絕緣材料21〇。可使 制之乾齡m程使絕緣材料產生㈣。例如二 ^緣材料2U)日陷約2〇〇埃〜埃之實施例中， 乾崎程約3 0秒〜! 5 〇秒，使絕緣材料2】〇凹陷 凹槽310之絕緣溝槽11G側壁的絕緣材料训較佳 約為40埃〜150埃。 又 >弟7圖揭示本發明一實施例電晶體7ι〇之 採用類似形成第4圖電晶體410之方法 之電晶體710,並中類似之罝分佔田4 貝知例 ，、〒六員似之早兀使用相同之符號。請注音 本發明可採用其它型態或結構。 ^ 、第8圖揭示本發明一實施例高應力薄膜81〇之形 成。本實施例高應力薄膜810之形成係類似於上述: 圖實施例高應力_510之形成（在此實施例巾高應力薄 膜810可以為接觸㈣阻擋層）。由於沿著絕緣溝槽HQ 側壁之部份絕緣材料21Q係保留，高應力薄膜 接接觸絕緣溝槽U〇之侧^。此實施例係傳遞大量的鹿 力至電晶體710之通道區，可避免漏電流之問題。、 …、請注意，上述之製程可以不同方式進行，例如為方 便說明’ i述之製程係在形成閘極介電4121電極414 和間隙壁416前，凹陷絕緣溝槽110之絕緣材料21〇。在 貝細*例中凹陷絕緣溝槽之絕緣材料210係在形成 閘極介電412、閘電極414和間隙壁416之後進行。又另 一實施例中，若需要在凹陷製程中保護其下結構，可於 閘電極414和間隙壁416上方形成一罩幕。 、 050j-A33 166TWF/wayne 14 200849405 以上提供之實施例係用以描述本發明不同之技術特 徵，但根據本發明之概念，其可包括或運用於更廣泛之 技術範圍。須注意的是，實施例僅用以揭示本發明製程、 裝置、組成、製造和使用之特定方法，並不用以限定本 發明，任何熟習此技藝者，在不脫離本發明之精神和範 圍内，當可作些許之更動與潤飾。因此，本發明之保護 範圍，當視後附之申請專利範圍所界定者為準。 05 03-A3 3166TWF/wayne 15 200849405 【圖式簡單說明】 第1圖〜第5圖揭系本發明一實施例包括應變通道區 之半導體元件的製造方法。 第6圖〜第8圖揭系本發明另一實施例包括應變通道 區之半導體元件的製造方法。 11〇〜絕緣溝槽； 2〇〇〜晶圓； 310〜凹槽； 412〜閘極介電· 416〜間隙壁； 510〜高應力薄膜； 810〜局應力薄膜。 【主要元件符號說明】 100〜晶圓； 112〜基底； 210〜絕緣材料； 410〜電晶體； 414〜閘電極； 418〜源極/汲極區； 710〜電晶體； 〇503-A33166TWF/wayne 16200849405 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device, and more particularly to a metal oxide semiconductor field effect transistor (hereinafter referred to as MOSFET) and Manufacturing Method 0 [Prior Art] Over the past few years, the miniaturization of dimensions (including gate length and gate oxide thickness reduction) has enabled MOS field effect transistors to continuously improve speed, performance, circuit density, and unit function. cost. In order to further enhance the performance of the transistor, the MOS field effect crystal system is applied to the strain channel region in the semiconductor substrate, and strain is applied in the channel region to increase the moving rate of the carrier, thereby making the N-channel MOS field effect Transistor (NM0SFET) and P-channel MOS field effect transistors (PMOSFET) increase efficiency. Generally, the tensile stress is applied to the N-channel of the N-type MOSFET in the source-to-polar direction to increase the electron mobility and apply compressive stress along the source to the drain to the P-type MOS. The P channel of the field effect transistor can increase the hole mobility. Many methods of guiding strain to the transistor channel region have been developed. In one of the methods of the prior art, a semiconductor mixed layer such as a Shi Xi-锗 or a Shi Xi-锗-carbon is formed under a thin semiconductor layer, wherein the lattice structure of the semiconductor mixed layer is different from the semiconductor layer thereon, The difference in lattice structure causes strain on the semiconductor layer thereon to increase the carrier mobility. 0503-A3 3166TWF/wayne 5 200849405 The old method of forming a blanket mixed semiconductor layer is difficult to carry out except for the leakage current. For example, the half-layer (four) mixed layer of i-crystal growth is costly, and it is difficult to precisely control the degree of flaws in the semiconductor mixed layer. In addition, the presence of the semiconductor hybrid 2 can create unwanted junctions at the junctions of the source " and the pole regions, which in turn can cause junction leakage currents. After the transistor is transformed into a transistor, the crystal of the base of the dream base = structure: r:: the stress film is formed above the full and σ structures, and the stress film or strain gauge is attached to 丄1: significant influence' Adjust the lattice spacing between the channel regions, due to the body-structure channel region. In addition, the strain gauge is placed throughout the electrical crystal to improve the performance of the component. The pancreas's height is high: two: the amount of stress applied is limited. For example, the stress applied by the shape πW Λ is limited by the subsequent cavities and the range of the engraving process. SUMMARY OF THE INVENTION According to the above problems, an object of the present invention is to provide an effective method for (4) additional strain to increase the efficiency of a transistor. Substrate burst: = a semiconductor structure. - the insulating trench is formed in the - ^ /, medium to ν minute insulating trench filled with the dielectric material, and at least part of the milk mite trench, the top surface (four) to low On the substrate, the surface-pen crystal is located above the substrate, and the contact is placed above the dielectric material of the substrate and the insulating grooved towel. The invention provides a semiconductor junction, a medium, a gas, a Qingu long screen 6, and a rim are formed in the groove. A concave # position,; absolute, edge includes - filling the groove of the dielectric material in the groove and on the substrate. Any of the etch barrier layers is provided. The present invention provides a semiconductor structure. a base and a side of the μ and a first opposite, a second and a top forming an insulating trench, a gentle, sturdy, t 1 & first on the first top side of the winter screen, the 纟巴缘沟The trough is at least partially filled with a top and a private part of at least part of the dielectric material; 'corner. An upper surface of the transistor/11 edge trench is above the substrate. The _ square, a stress layer is located in the dielectric material and the step ΪΖ:: a method of manufacturing a semiconductor device, comprising the following subsequent intrusion into the substrate, and forming an insulating trench in the substrate.吏,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, The m Γ is recessed below the top of the substrate. μ is formed into a transistor gate above the substrate and forms a bank layer covering at least part of the substrate and the dielectric material.于成应实施实施实施方式 [ 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施The present invention discloses a method of fabricating a semiconductor device including a strain channel region 0503-A33166TWF/wayne 200849405, and the implementation disclosed herein can be applied to various circuits. First, please refer to The second diagram, which shows a portion of the wafer 100, includes an insulating trench formed in the substrate 2. The substrate 112 may comprise a stone block, a doped or unsubstituted substrate, or an insulating layer. The active layer of the Shixi base. Generally speaking, there is a base on the insulating layer, and a layer of semiconductor material (such as hair) on the color 4: layer. The insulating layer can be a buried oxide layer. Xide 'hereafter referred to as Β〇χ or yttrium oxide layer. The insulating layer is typically formed on a substrate of tantalum or glass. Additionally, embodiments of the invention may use multiple layers or gradient substrates. Lithography Insulating trenches 110. First, the 'micro-picture technology includes the following steps: deposition - photoresist material, and the cover is exposed, exposed and developed. As shown in Fig. 1, after the patterned light, the mask can be An etching process is performed to remove portions of the substrate 112 that are not needed. 1 In a preferred embodiment in which the substrate comprises a dream block, the (4) process can be a ruthenium or dry, isotropic or anisotropic etch process, but etching. The process is preferably an anisotropic dry (four) process. In the embodiment, the depth of the insulating spacer 110 is about 2000 angstroms to 3 angstroms. FIG. 2 illustrates an embodiment of the present invention in the insulating trench 110. Insulating material, wafer 100 after 210. In an embodiment, the insulating material 2i includes oxygen, a process for forming an oxide layer, wherein the oxidation process is, for example, one comprising oxygen, moisture, nitrogen oxide, or a combination thereof. The environment is wet or dry..., oxidized. Alternatively, the oxide layer can be formed by chemical vapor deposition (cvd) using tetra-ethyl-ortho-silicate (TEOS) and oxygen as precursors. 0503-A33166TWF/wayne 8 200849405 is available - The planarization step 'to planarize the surface of the insulating material 210 to make it coplanar with the top surface of the substrate n2: a chemical mechanical polishing method well known in the art (10) two mechanical pohshmg, hereinafter referred to as cmj)). Disclosed to the present invention - an embodiment in the insulating material 210 妒 晶圆 晶圆 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 绝缘 绝缘 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 晶圆 乜 乜 乜 乜 乜 乜The insulating material is formed into a groove below the substrate material soaking the diluted hF solution. "5" shoulder seconds, so that the insulating material = 曰 4 figure reveals the step of forming the transistor 41 in an embodiment of the present invention. The solar body 410 includes a gate dielectric 412, a gate electrode 414, and a gap-opening drain region 418. As with the conventional technique, a pole dielectric 412 and an electrode 414 are formed on the substrate ι2. : 匕 匕 pole: electricity for example oxidized dream, oxynitride, nitride, nitrogen oxides, Bucheng people + 丄 flat ^ 1 匕 preferred dielectric constant is about 412 aluminum, oxygen servant gas In addition, the electrode may include an oxidized high dielectric material / A, yttrium oxide, oxynitride or a combination of the above 412. In an embodiment including an oxide layer, the gate dielectric is formed by a process, and the oxidation process is, for example, One includes gas, water vapor, nitric oxide or a combination thereof, or a gate dielectric can be formed by chemical vapor deposition::::$WE0S) and oxygen as a precursor. In this = 4: 0503-A33166TWF/wayne 200849405, the thickness of the gate dielectric 412 is about 8 angstroms to 5 20 angstroms. Preferably, the thickness of the preferred gate electrode 4U comprises a conductive (tetra) compound, a metal nitride, a doped poly(D) genus, a metal slab, and other channels + combinations. The metal is, for example, a fun, titanium, indium, or niobium material or the above metal halide such as titanium telluride, tantalum, 'g, niobium or tantalum, metal nitride such as titanium nitride or niobium nickel or niobium button, Shi Xizhi Formation consists of depositing an amorphous stone eve: and two. Top: In the example, polycrystalline polycrystalline stone. The inter-electrode is a polycrystalline hair: the stone is recrystallized to form a chemical vapor deposition (LPCVD) deposition; ^Y' can be formed by a low enthalpy, forming a gate electrode 414, 苴中, 冗 并 曰 5 格 4 Polycrystalline Cheer ~ 2500 angstroms, preferably thickness is about 8 〇 〇曰 〇曰 之 之 之 之 之 之 之 之 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以412 materials, after the photoresist material is covered, 瞧 , , 儿 儿 儿 儿 儿 儿 儿 儿 儿 光 光 光 光 光 光 光 光 光 光 光 光 光 光 光 光 光 光 光 光 光 光 光 光 光 光 光 光 光 光 光 光 光 光 光Electricity 4 = ^ ^ ^ ' As the brother 4 map does not. In the case where the gate electrode material is polycrystalline germanium == is the preferred implementation of oxygen (four), the process can be a t-directional or anisotropic button engraving process, but a better anti-isotropic dry engraving process. The source/drain region 418 is formed by an ion-distribution process, and an N-type dopant (such as a can, a nitrogen, a god, a recording, or the like) is implanted on the source/nano 418 to fabricate an NMOS device, or A p-type wayne °503-A33l66TWF/' 10 200849405 dopant (such as boron, indium, indium or the like) is implanted in the source/drain region to fabricate a PM〇S device. In another embodiment, multiple masks and ion implantation steps well known in the art are employed to implant N-type or P-type ions only in specific areas. The spacer 416 preferably includes tantalum nitride (Si3N4), other components of the nitrogen-containing layer (SixNy, excluding Si3N4), bismuth oxynitride (SiOxNy), silicon oxime (Si 〇xNy: Hz) or the like. A combination in which a spacer is formed is used for the second ion implantation in the source/drain region 418. In a preferred embodiment, a chemical vapor deposition process (using decane and ammonia as a precursor) is used to form a layer comprising tantalum nitride (Si3N4) to form spacers 416. An isotropic (e.g., soaked acid H3P04 solution) or an anisotropic process patterned spacer 416 is performed. In an example of isotropic etching to form a spacer, the isotropic etching is removed at the top of the gate electrode 414 since the nitrided (Si3N4) layer is located at a portion of the sidewall of the gate electrode 414 that is greater than the portion of the top of the adjacent gate electrode 414. A portion of the tantalum nitride (Si3N4) material, and the substrate 112 are not directly adjacent to another portion of the tantalum nitride (Si3N4) material of the gate electrode 414, while leaving the spacers 416 shown in FIG. Please note that this embodiment can still perform a process. The use of a deuteration process improves the conductivity of the conductive gate electrode 414 and reduces the impedance of the source/drain regions 418. The deuteration process may include the following steps: depositing a metal layer such as titanium, germanium, tungsten or cobalt by physical vapor deposition (PVD). A tempering process is then performed to cause the metal layer to react with the conductive idle electrode 414 and the source/> and the polar region 418 to form a metal chipped 0503-A33166TWF/wayne 11 200849405, and a portion is located on the insulating spacer 416. The metal layer is unreacted, and the unreacted portion of the metal layer can be selectively removed by, for example, a wet etching process. If necessary, an additional tempering process can be performed to change the phase of the deuteration zone to reduce the resistance. Note that the above description is an example of a transistor 410 applied to an embodiment of the present invention, and other transistors and semiconductor elements can be used in the present invention. For example, the transistor can include a raised source/drain, and the transistor can be a split gate transistor or a fin transistor (FinFET). Additionally, the invention may employ different materials and thicknesses. Further, the present invention can form a liner between the spacer and the gate electrode. The present invention may additionally utilize composite spacers, or use different doping profiles, or the like. FIG. 5 illustrates a wafer 100 after forming a high stress film 510 according to an embodiment of the present invention, wherein the high stress film covers the transistor 410 and the recess 310 of the insulating trench 110 (in this embodiment, the high stress film 510 may be contact etched) Barrier layer). Please note that the high stress film 510 can be tensile or compressive. The tensile stress film will generate tensile strain in the channel region, increasing the electron mobility of the N channel and the transistor, and the compressive stress film will generate compressive strain in the channel region, increasing the hole mobility of the P channel transistor. The high stress film 510 is formed by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or the like. The tensile stress film preferably has a thickness of about 5 nm to 500 nm, and it applies a stress of OGPa 〜5 GPa substantially in the source-to-polar direction. The compressive stress film preferably has a thickness of about 5 nm to 500 nm, and it generally applies a stress of OGPa to _5 GPa. Applicable to 0503-A33166TWF/wayne 12 200849405 The material of the tensile stress film includes silicon nitride (SiN), oxide, gas, sic, carbonitride (SiCN), nickel telluride, tantalum , a combination of the above or a similar substance. Suitable materials for compressive stress films include SiGe, SiGeN, Oxide, Antimony, or combinations thereof. Note that the high stress film 510 may comprise a plurality of layers of the same or different materials, or materials of the same or different stress characteristics. Embodiments of the present invention can be used to fabricate wafers including NMOS* PM devices, for example, NM0S transistors with tensile stress films and compressive stresses can be fabricated on the same wafer by well-known deposition and patterning techniques. Thin film: PMOS transistor allows the transistor to be fabricated with specific functions. After the performance, the standard process can be used to complete the fabrication and sealing of semiconductor components such as Shicheng and graphical contact | insect barrier layer (optional), inter-race dielectric layer and metal layer, and other circuits can be formed, cutting And seal ^ wafer. ^ "The figure reveals another embodiment of the wafer track of the embodiment 6_8, the initial element of the wafer 200 of this embodiment is disclosed, as disclosed in the dry example of the figure u, please note this embodiment and the first The same reference numerals are used for the same reference numerals in Fig. 2. Referring first to Fig. 6, there is shown an embodiment of the present invention, insulating = 2 2 〇 recessed wafer 2 〇〇. In this embodiment, although the insulating material The 210-type recesses 'are along the sidewalls of the insulating trenches (4) of the recess 31 (), and a portion of the insulating material 21 is retained. The recess 310 can be formed by, for example, the above-mentioned 4 shadow technique. Graphical photoresist material 0503-A33166TWF/wayne 13 200849405 , 'Insulating material 21〇 to the exposed insulating trench 11〇. The dry m process can be made to produce insulating material (4). For example, 2U edge material 2U) In the embodiment of about 2 angstroms to angstroms, the dry-stable process is about 30 seconds~! 5 sec., so that the insulating material of the insulating material 2] 〇 recessed groove 310 is preferably about 40 angstroms. ~150 angstroms. Also, the drawing of the brother 7 shows that the transistor 7 〇 is similarly formed in an embodiment of the present invention. 4, the transistor 710 of the method of the transistor 410, and similarly known as the 占田占4, for example, the same symbol is used as the sixth member. Please note that other types or structures may be used in the present invention. ^, Figure 8 discloses the formation of a high-stress film 81 of an embodiment of the present invention. The formation of the high-stress film 810 of this embodiment is similar to that described above: Figure 1 shows the formation of high stress _510 (high stress in this embodiment) The film 810 may be a contact (four) barrier layer. Since a portion of the insulating material 21Q along the sidewall of the insulating trench HQ remains, the high stress film contacts the side of the insulating trench U〇. This embodiment transmits a large amount of deer force. To the channel region of the transistor 710, the problem of leakage current can be avoided. ..., please note that the above process can be performed in different ways, for example, for convenience of description, the process described in the process is to form the gate dielectric 4121 electrode 414 and the gap. In front of the wall 416, the insulating material 21 of the recessed insulating trench 110 is recessed. The insulating material 210 of the recessed insulating trench is formed after forming the gate dielectric 412, the gate electrode 414 and the spacer 416. In an embodiment, if It is necessary to protect the underlying structure in the recess process, and a mask can be formed over the gate electrode 414 and the spacer 416. 050j-A33 166TWF/wayne 14 200849405 The embodiments provided above are used to describe different technical features of the present invention. However, in accordance with the teachings of the present invention, it may be included or used in the broader technical scope. It is noted that the embodiments are only used to disclose the specific methods of the process, apparatus, composition, manufacture and use of the present invention, and are not intended to limit the present invention. The invention may be modified and retouched by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. 05 03-A3 3166TWF/wayne 15 200849405 [Brief Description of the Drawings] Figs. 1 to 5 are views showing a method of manufacturing a semiconductor element including a strain path region according to an embodiment of the present invention. 6 to 8 are views showing a method of manufacturing a semiconductor element including a strain channel region according to another embodiment of the present invention. 11 〇 ~ insulating trench; 2 〇〇 ~ wafer; 310 ~ groove; 412 ~ gate dielectric · 416 ~ spacer; 510 ~ high stress film; 810 ~ stress film. [Main component symbol description] 100~ wafer; 112~ substrate; 210~ insulating material; 410~ transistor; 414~ gate electrode; 418~ source/drain region; 710~ transistor; 〇503-A33166TWF/wayne 16

Claims (1)

200849405 十、申請專利範園·· h ~種半導體結構，包括·· 一基底； 緣溝槽’形成於該基底中，其中至少部份該絕 電材^之、^電材料，且該絕緣溝槽中，至少部份該介 迅〆 頂部表面係凹陷至低於該基底之頂部表面； 甩晶體閘極，位於該基底上方；及 介電材刻阻擋層，位於該基底和該絕緣溝槽中之 姑分^如申請專利範圍第1項所述之半導體結構，並中 、/钇之側壁延伸至該基底之頂部表面。 該絕3緣S二=第1項所述之半導體結構，其中 該基底之了頁部表面Γ，丨電材料之頂部表面仙陷至低於 其中 該接4觸钱H專H圍第1項所述之半導體結構 j 1且狺層係為張應力薄膜。 其中 5.如申請專利範 其中 該接觸餘刻阻擒層係為壓應力薄膜。…構 6·如申請專利範圍第 該接觸钱刻阻擒層覆蓋該電晶體。 …構 其中 7.如申請專利範圍 至少部份該介雷鉍粗丄 卞 結構 包材枓大體上凹陷2〇〇埃〜5〇〇埃。 種半導體結構，包括： 、 050j-A〇3 166TWF/wayne 17 200849405 一基底； 緣包形成於該基底中，其中該淺溝槽嚷 深匕祜填入介電材料之溝槽； 曰、、、巴 凹槽，教於該淺溝槽絕緣中；及 —接觸_阻擋層’位於凹槽中和該基底上。 ，凹^彳專利範圍第8項所述之半導體結構，过办 相槽之侧壁係覆蓋該介電材料。 冑其中 ” 1 盖0揭t申請專利範圍第8項所述之半導體結構，过办 部表面。 特"⑨材科係凹陷至低於該基底之項 兮接Γ與如/請專利範圍第8項所述之半導體結構，龙由 箱杨i阻擋層係為張應力薄輸應力薄膜籌其中 2·如申請專利範圍第8項所 括一電晶體，位於該基底上。 +泠脰…構，更包 13. 如申請專利範圍第12項所述 中该接觸蝕刻阻擋層覆蓋該電晶體。 一冓，其 14. 如申請專利範圍第8項所述 该凹槽之深度大體上為細埃〜5⑻埃。¥脰、-構，其中 15· —種半導體結構，包括： —基底，具有一第一頂部側邊和— 側邊，該基底於第一頂部侧邊 ナ之弟—底部 溝槽至少部份填入一介電材料，至 2该絕緣 电曰日 頂部表面低於該絕緣溝槽之上部邊角；〜"電材料之 —兩日體，位於該基底上方；及 〇5〇j-A3 〇 J 66TWF/wayne 200849405 位於該介電材料和該基底上方。 中該絕缘知：專利範圍第15項所述之半導體結構，立 中1巴、、象冓槽之側壁係覆蓋該介電材料。 、 17.如申清專利範圍第】5 中該應力層直接之牛¥肢結構，其 ㈢1接接觸邊絕緣溝槽之一上部部份。 .如申請專利範圍第】5項所述之 中該應力層為張應力薄膜物力薄膜。 構，其 中部15項所述之半導體結構，其 底之弟一頂部側邊200埃〜500埃。 _於該基 中兮2ΛΓ請專利範圍第15項所述之半導體結構，盆 中5亥應力層覆蓋該電晶體。 八 21. —種半導體元件之製造方法，包括： 提供一基底； 形成一絕緣溝槽於該基底中； 填入一介電材料於該絕緣溝槽中； 凹陷該介電材料，使至少部份該介電材料 面凹陷至低於該基底之頂部表面； 、、 形成一電晶體閘極於該基底上方；及 形成-應力層，至少覆蓋部份該基底和該 22. 如申請專利範圍第21項所述之半導體^制 造方法，其中凹陷該介電材料之步驟使該絕緣溝 = 部該介電材料之頂部表面凹陷至低於該基底之㈢^王 面。（第一實施例） 土〜 頂部表 05 03-A3 3166TWF/wayne 19 200849405 造方法，发t專利耗圍弟22項所述之半導體元件之擎 製程陷該介電材料之步驟係為-濕式韻刻 、24.如申請專利範圍第幻項所述之半 仏方法，其t該濕絲㈣ & 之衣 度。(第-實施例） 才門拴制蝕刻之程 25.如申請專利範圍第门項 造方法，其中該介電材料為—氧化層。件之製 造方料利範圍第25項所述之半導體元件之製 '，、中該濕式蝕刻製程為浸泡氫氟酸。. 27. ”請專利範圍第21項所述之半導體元件之制 以法’其中凹_介電材料之步驟在沿著該: 之側壁仍保留部份該介電材料。（第二實施例）/ θ 28. ”請專利範圍第27項所述之半導體元件之制 =」’其中該應力層不直接接觸該絕緣溝槽之側壁= 二實施例） 土、乐 、告29· #申請專利範圍帛27賴述之半導體元件之製 ^法’其中該凹陷該介電材料之步驟採用-乾式蝕： ^ 3、0·如申請專利範圍第29項所述之半導體元件之製 二方去，其中該乾式蝕刻製程係採用時間控制蝕刻之程 ^ M ·如申凊專利範圍第21項所述之半導體元件之製 造方法，在凹陷該介電材料前，尚包括對該介電材料= 〇503-A33166TWF/wayne 20 200849405 行一平坦化步驟。 造方之：申φ請專利範圍第31項所述之半導體元件之製 /、邊平坦化步驟使該介電材料之表面 之頂部表面共面。 謂卄之表面與基底 造方:.，：t請專利範圍第21項所述之半導體元件之紫 〜500埃之深度。 基底表面約200埃 34. 如申請專利範圍第21項所 造方法，.其中該應力層覆蓋該電M= +V體凡件之製 35. 如申請專利範圍第21項所述之半 造方法，其中該應力層為-張應力薄膜。1 之製 請專利範圍第35項所述之半導 該張應力薄膜包括氮切、氧化物、氮； =物、兔切、碳氮切、魏鎳、魏鉛或上述之= 申請專利範圍第21項所述之半導 &方法，其中該應力層為一壓應力薄膜。 之衣 、生方去月專利耗圍第37項所述之半導體元件之f &方法」其中_力薄膜包括錯化石夕、氮、： 化物、氮氧化物或上述之組合。 、 氧 0503-A33166TWF/wayne200849405 X. Applying for a patent garden · h ~ a semiconductor structure, including a substrate; a trench trench formed in the substrate, at least a portion of the insulating material, the electrical material, and the insulating trench At least a portion of the top surface of the dielectric layer is recessed below the top surface of the substrate; a germanium crystal gate is located above the substrate; and a dielectric barrier layer is disposed in the substrate and the insulating trench A semiconductor structure as claimed in claim 1, wherein the side walls of the middle and/or the crucible extend to the top surface of the substrate. The semiconductor structure of the first item, wherein the surface of the substrate is Γ, the top surface of the enamel material is submerged below the first item of the The semiconductor structure j 1 and the germanium layer are tensile stress films. 5. In the patent application, the contact resist layer is a compressive stress film. ...6. If the scope of the patent application is the first, the contact money engraves the layer to cover the transistor. ... structure 7. If the scope of the patent application is at least partially, the material is rough and the structure is substantially recessed by 2 angstroms ~ 5 angstroms. The semiconductor structure comprises: , 050j-A〇3 166TWF/wayne 17 200849405 a substrate; a rim is formed in the substrate, wherein the shallow trench is deeply filled into the trench of the dielectric material; 曰, ,, The groove is taught in the shallow trench insulation; and the contact-barrier layer is located in the groove and on the substrate. The semiconductor structure described in the eighth aspect of the patent, wherein the side wall of the process cell covers the dielectric material.胄 胄 ” ” ” ” ” ” ” ” 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体In the semiconductor structure described in the eighth item, the block is made of a tensile stress and a thin stress-transfer film. 2. A transistor is included in the eighth item of the patent application scope, and is located on the substrate. And further comprising: 13. The contact etch barrier layer covers the transistor as described in claim 12 of the patent application. 1. The groove has a depth of substantially fine as described in claim 8 〜5(8) Å. The structure of the semiconductor structure comprises: a substrate having a first top side and a side, the substrate being on the first top side At least partially filled with a dielectric material, and the top surface of the insulated electric day is lower than the upper corner of the insulating trench; and the two-day body of the electrical material is located above the substrate; and 〇5〇 j-A3 〇J 66TWF/wayne 200849405 located in the dielectric material and the The bottom of the bottom. The insulation is known: the semiconductor structure described in the fifteenth patent range, the center of the 1 bar, the sidewall of the image groove covers the dielectric material. 17. As stated in the patent scope of the application, The stress layer is directly connected to the limb structure, and (3) 1 is connected to an upper portion of the insulating groove of the contact edge. The stress layer is a tensile stress film material film as described in the fifth paragraph of the patent application. The semiconductor structure of the above-mentioned item 15 has a top side of 200 Å to 500 Å. The semiconductor structure described in claim 15 is covered by the fifth layer of the stress layer in the basin. 8. The method of manufacturing a semiconductor device, comprising: providing a substrate; forming an insulating trench in the substrate; filling a dielectric material in the insulating trench; recessing the dielectric material to at least Part of the surface of the dielectric material is recessed below the top surface of the substrate; forming a transistor gate over the substrate; and forming a stress layer covering at least a portion of the substrate and the 22. Item 21 The semiconductor manufacturing method, wherein the step of recessing the dielectric material causes the insulating trench = portion to recess the top surface of the dielectric material below the (three) surface of the substrate. (First Embodiment) Soil ~ Top Table 05 03-A3 3166TWF/wayne 19 200849405 The method of manufacturing, the patent process of the semiconductor component described in the 22nd patents is 22-wet rhyme, 24. The semi-finished method described in the item, wherein the wet silk (four) & clothing (the first embodiment) is the process of etching the etch. 25. The method of the patent application, wherein the dielectric material It is an oxide layer. The manufacturing process of the device is in the form of the semiconductor device described in item 25, wherein the wet etching process is immersion of hydrofluoric acid. 27. The method of manufacturing a semiconductor device according to the scope of claim 21, wherein the step of recessing the dielectric material remains part of the dielectric material along the sidewall of the: (second embodiment) / θ 28. "Please refer to the semiconductor component described in item 27 of the patent scope = "' where the stress layer does not directly contact the sidewall of the insulating trench = two embodiments) 土,乐,告29·#Application Patent Range The method of manufacturing the semiconductor device of the above-mentioned semiconductor device, wherein the step of recessing the dielectric material is performed by dry etching: ^ 3, 0, as in the case of the semiconductor device described in claim 29, wherein The dry etching process is a time-controlled etching process. The manufacturing method of the semiconductor device described in claim 21, before the dielectric material is recessed, the dielectric material is further included = 〇 503- A33166TWF/wayne 20 200849405 Line one flattening step.造方: Shen φ Please select the semiconductor component described in the 31st patent range, and the edge flattening step makes the top surface of the surface of the dielectric material coplanar. It is said that the surface and the base of the crucible are: ., :t Please select the depth of the semiconductor component of the semiconductor component described in item 21 of the patent range of ~500 angstroms. The substrate surface is about 200 angstroms. 34. The method of claim 21, wherein the stress layer covers the electricity M=+V body parts. 35. The semi-finished method as described in claim 21 Wherein the stress layer is a tensile stress film. 1) The semi-conductive stress film described in item 35 of the patent scope includes nitrogen cut, oxide, nitrogen; = material, rabbit cut, carbon nitride cut, Wei nickel, Wei lead or the above = Patent application scope The semi-conductive & method of claim 21, wherein the stress layer is a compressive stress film. The f&method of the semiconductor device described in the 37th item of the patent, wherein the film comprises a miscible stone, a nitrogen, a compound, an oxynitride or a combination thereof. , oxygen 0503-A33166TWF/wayne
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US20080303102A1 (en) 2008-12-11
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