TWI591823B - 包含鰭狀結構之半導體元件及其製造方法 - Google Patents
包含鰭狀結構之半導體元件及其製造方法 Download PDFInfo
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- TWI591823B TWI591823B TW104127957A TW104127957A TWI591823B TW I591823 B TWI591823 B TW I591823B TW 104127957 A TW104127957 A TW 104127957A TW 104127957 A TW104127957 A TW 104127957A TW I591823 B TWI591823 B TW I591823B
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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Description
本發明是有關於一種半導體積體電路,且特別是有關於一種具有鰭狀結構之半導體元件及其製造方法。
隨著半導體工業進展為奈米技術製程節點,為追求更高的元件密度、更高的效能以及更低的成本,從製造與設計而來的挑戰,促成例如鰭狀場效電晶體(fin field effect transistor;Fin FET)之3D設計的發展。鰭狀場效電晶體元件通常包括具有高深寬比(Aspect Ratio)之半導體鰭片,並在鰭片中形成半導體電晶體元件的通道和源極/汲極區。閘極係於鰭狀結構之側邊上並沿著側邊形成(例如包覆)。上述閘極之形成係利用通道和源極/汲極區表面積增加之優點,以製造更快速、更可靠且更易於控制之半導體電晶體元件。在一些元件中,鰭狀場效電晶體之源極/汲極(S/D)部分中的應變材料使用例如矽鍺(SiGe)、碳化矽(SiC)及/或磷化矽(SiP),可增強載子流通性(Carrier
Mobility)。
因此,本發明之一態樣是在提供一種包含鰭狀結構之半導體元件,其係藉由設置應力源層減少短通道效應。
本發明之另一態樣是在提供一種包含鰭狀結構之半導體元件,其具有特定範圍之近接距離。
本發明之又一態樣是在提供一種包含鰭狀結構之半導體元件的製造方法,以製得前述之包含鰭狀結構之半導體元件。
根據本發明之一態樣,提供一種包含鰭狀結構之半導體元件。在一實施例中,上述之半導體元件包括鰭狀場效電晶體。鰭狀場效電晶體包括設於基材上的鰭狀結構。鰭狀結構包括通道層,且鰭狀結構係沿第一方向延伸。鰭狀場效電晶體也包括閘極結構,閘極結構包括閘極電極層和閘極介電層,閘極結構係覆蓋鰭狀結構的一部分,且閘極結構係沿垂直於第一方向之第二方向延伸。閘極結構更包括設於閘極電極層之二主側上的側壁絕緣層。鰭狀場效電晶體更包含源極和汲極,源極和汲極的每一者包括設於未被閘極結構覆蓋之凹陷中的應力源層。應力源層包括第一應力源層、於第一應力源層上的第二應力源層,和於第二應力源層上的第三應力源層。在源極中,第一應力源層和通道層間的界面係位於較靠近源極或閘極電極層側壁絕緣層中的一者下。
依據本發明之一實施例,半導體元件更包含從
基材延伸至應力源層之晶格差排(dislocation)結構。在半導體元件中,鰭狀場效電晶體為n型鰭狀場效電晶體,第一應力源層包括碳化矽磷(SiCP),第二應力源層包括碳化矽磷,第三應力源層包括磷化矽,且其中該第一應力源層之碳濃度係高於第二應力源層之碳濃度,第二應力源層之磷含量係高於第一應力源層之磷含量,且第三應力源層之磷含量高於第二應力源層之磷含量。
依據本發明之一實施例,其中鰭狀結構包括於
閘極結構下的多個鰭片,並為上述鰭片提供一個源極和一個汲極,且源極和汲極具有合併的鰭狀結構。
依據本發明之一實施例,其中上述界面係定義
為應力源層最靠近通道層之一點,且其中在源極中,界面係位於較靠近源極之側壁絕緣層之一者之正下方;或者,界面係位於平面上,且上述平面係延伸自閘極電極層和靠近源極之側壁絕緣層之一者的另一界面;抑或,界面係位於閘極電極層之正下方,且界面與平面之間的距離係等於或小於1奈米。
根據本發明之另一態樣,提供一種包含鰭狀結構之半導體元件。在一實施例中,上述之半導體元件包括鰭狀場效電晶體。鰭狀場效電晶體包括設於基材上的鰭狀結構。鰭狀結構包括通道層,且鰭狀結構係沿第一方向延伸。鰭狀場效電晶體也包括閘極結構,閘極結構包括閘極電極層和閘極介電層,閘極結構係覆蓋鰭狀結構的一部分,且閘極
結構係沿垂直於第一方向之第二方向延伸。閘極結構更包括設於閘極電極層之二主側上的側壁絕緣層。鰭狀場效電晶體更包含源極和汲極,源極和汲極的每一者包括設於未被閘極結構覆蓋之凹陷中的應力源層。應力源層包括第一應力源層、於第一應力源層上的第二應力源層,和於第二應力源層上的第三應力源層。通道層沿第一方向的寬係小於閘極電極層的寬和沿第一方向延伸之側壁絕緣層的寬的總合。
依據本發明之一實施例,其中通道層之寬度為
在閘極結構下之最小寬度。
根據本發明之又一態樣,提供一種包含鰭狀結
構之半導體元件的製造方法包括形成鰭狀結構於基材上。鰭狀結構包括從隔離絕緣層上暴露出的通道層,且鰭狀結構係沿第一方向延伸。閘極結構包括閘極電極層和閘極介電層,且閘極結構係形成於部分的鰭狀結構上。閘極結構沿垂直於第一方向之第二方向延伸。閘極結構更包括設於閘極電極層之二主側上的側壁絕緣層。藉由移除未被閘極結構覆蓋的部分鰭狀結構,以形成凹陷。源極和汲極係形成於凹陷中,源極和汲極的每一者包括應力源層。應力源層包括第一應力源層、於第一應力源層上的第二應力源層,和於第二應力源層上的第三應力源層。形成凹陷使得在源極中,第一應力源層和通道層間的界面係位於較靠近源極或閘極電極層之側壁絕緣層中的一者下。
依據本發明之一實施例,上述方法更包含在形成凹陷後,植入離子至凹陷的底部、形成應力源層於被植入
離子之凹陷的底部上,以及退火具有應力源層之基材,以形成晶格差排。
依據本發明之一實施例,其中鰭狀結構包括於
閘極結構下的多個鰭片,且在形成凹陷之步驟中,未被閘極結構覆蓋之鰭狀結構的一部分係被蝕刻至與基材水平,使得鰭片間不保留有隔離絕緣層。
依據本發明之一實施例,上述方法更包含形成
第四層於第三應力源層上,其中第一應力源層包括磊晶形成的碳化矽磷,第二應力源層包括磊晶形成的碳化矽磷,第三應力源層包括磊晶形成的磷化矽,第四層包括磷化矽,且其中第一應力源層之碳濃度係高於第二應力源層之碳濃度,第二應力源層之磷含量係高於第一應力源層之磷含量,第三應力源層之磷含量高於第二應力源層之磷含量,且第四層之磷含量小於第三應力源層之磷含量。
應用本發明之包含鰭狀結構的半導體元件,可
藉由減少閘極電極層和源極/汲極磊晶層(第一磊晶層)間的近接距離,但第一磊晶層中包括碳,可抑制因磷擴散至通道層所造成的短通道效應,以增加提供至通道層的應力。
S101、S103、S105、S107、
S109‧‧‧步驟
10‧‧‧基材
20‧‧‧鰭狀結構
20A‧‧‧通道層
20B‧‧‧井層
30‧‧‧閘極介電層
40‧‧‧閘極結構
45‧‧‧閘極電極層
50‧‧‧隔離絕緣層
60‧‧‧硬罩幕
62‧‧‧氮化矽層
64‧‧‧氧化層
70‧‧‧側壁絕緣層
80‧‧‧凹陷
82‧‧‧偏斜末端
90‧‧‧非晶化區
95‧‧‧應力薄膜
100‧‧‧再結晶區
105‧‧‧晶格差排
106‧‧‧夾止點
110‧‧‧第一磊晶層
120‧‧‧第二磊晶層
130‧‧‧第三磊晶層
140‧‧‧第四層
Px‧‧‧近接距離
a-a、b-b、c-c、d-d‧‧‧剖線
T1‧‧‧厚度
X、Y、Z‧‧‧方向
藉由以下詳細說明並配合圖式閱讀,可更容易理解本發明。在此強調的是,按照產業界的標準做法,各種特徵並未按比例繪製,僅為說明之用。事實上,為了清楚的討論,各種特徵的尺寸可任意放大或縮小。
[圖1]係繪示製造具有鰭狀結構之半導體場效電晶體元件(鰭狀場效電晶體)之例示製程流程圖。
[圖2]至[圖10C]係繪示根據本發明之一實施例之製造鰭狀場效電晶體的例示製程圖。
[圖11]至[圖12]係繪示根據本發明之另一實施例之製造鰭狀場效電晶體的例示製程圖。
下面的揭露提供了許多不同的實施例或例示,用於實現本發明的不同特徵。部件和安排的具體實例描述如下,以簡化本發明之揭露。當然,這些是僅僅是例示並且不意在進行限制。例如,在接著的說明中敘述在第二特徵上方或上形成第一特徵可以包括在第一和第二特徵形成直接接觸的實施例,並且還可以包括一附加特徵可以形成第一特徵的形成第一和第二特徵之間的實施例,從而使得第一和第二特徵可以不直接接觸。此外,本公開可以在各種例示重複元件符號和/或字母。這種重複是為了簡化和清楚的目的,並不在本身決定所討論的各種實施例和/或配置之間的關係。
此外,空間相對術語,如“之下”、“下方”、“低於”、“上方”、“高於”等,在本文中可以用於簡單說明如圖中所示元件或特徵對另一元件(多個)或特徵(多個特徵)的關係。除了在圖式中描述的位向,空間相對術語意欲包含元件使用或步驟時的不同位向。元件可以其他方式定位(旋轉90度或者在其它方位),並且本文中所使用的
相對的空間描述,同樣可以相應地進行解釋。
圖1係繪示製造具有鰭狀結構(鰭狀場效電晶
體)之半導體場效電晶體元件之例示流程圖。此流程圖僅繪示製造鰭狀場效電晶體之部分相關製程。可以理解的是,在圖1所示製程之前、之中以及之後可以提供額外的步驟,且在本方法的其他實施例中,以下所述之一些步驟可被取代或刪除。前述步驟/製程的順序也可互相調換。有關於具有應變材料(或應力源)之內凹式源極/汲極結構的一般製造方法係揭露於美國專利第8,440,517號中,其全文一併納入本案之參考文獻。
在圖1之步驟S101中,鰭狀結構係形成於基材
上,如圖2所示。圖2係繪示根據本發明之一實施例之製造鰭狀場效電晶體的各個階段之一的例示側視圖。
鰭狀結構20係形成於基材10上,且由隔離絕緣
層50突出。為製造鰭狀結構20,可利用例如熱氧化製程及/或化學氣相沉積(CVD)製程,將罩幕層形成於基材10上。
基材10可例如為摻質濃度約1×1015cm-3至約1×1018cm-3之p型矽基材。在其他實施例中,基材10為雜質濃度約1×1015cm-3至約1×1018cm-3之n型矽基材。在一些實施例中,罩幕層可包括例如墊氧化(例如氧化矽)層和氮化矽罩幕層。
另一種方式,基材10可包含其他元素的半導
體,例如鍺;半導體化合物包括例如碳化矽(SiC)和矽鍺(SiGe)之第IV族-第IV族化合物半導體,例如砷化鎵
(GaAs)、磷化鎵(GaP)、氮化鎵(GaN)、磷化銦(InP)、砷化銦(InAs)、銻化銦(InSb)、磷砷化鎵(GaAsP)、氮化鎵鋁(GaAlN)、砷化銦鋁(AlInAs)、砷化鎵鋁(AlGaAs)、砷化銦鎵(GaInAs)、磷化銦鎵(GaInP)及/或磷砷化銦鎵(GaInAsP)之第III族-第V族化合物半導體,或上述之組合。在一實施例中,基材10為絕緣層上覆矽(Silicon-on Insulator;SOI)之矽層。當使用絕緣層上覆矽基材時,鰭狀結構20可自絕緣層上覆矽基材之矽層突出,或可自絕緣層上覆矽基材的絕緣層突出。在後者的例子中,絕緣層上覆矽基材之矽層可用以形成鰭狀結構20。例如非晶矽或是非晶碳化矽之非晶矽基材,或例如氧化矽之絕緣材料,也可作為基材10。基材10可包括被適當摻有雜質(例如p型或n型導電性)之不同區域。
可使用熱氧化製程或化學氣相沉積製程來形成
墊氧化層。可使用例如濺鍍法之物理氣相沉積製程(PVD、化學氣相沉積、電漿加強化學氣相沉積(PECVD)、大氣壓化學氣相沉積(APCVD)、低壓化學氣相沉積(LPCVD)、高密度電漿化學氣相沉積(HDPCVD)、原子層沉積(ALD)及/或其他製程,來形成氮化矽罩幕層。
在一些實施例中,墊氧化層之厚度為約2奈米至約15奈米,且氮化矽罩幕層的厚度為約2奈米至約50奈米。罩幕圖案係進一步形成於罩幕層上。罩幕圖案可例如為利用微影步驟所形成之光阻圖案。
利用罩幕圖案作為蝕刻罩幕,以形成墊氧化層
之硬罩幕圖案和氮化矽罩幕層。在一些實施例中,硬罩幕圖案的寬度為約5奈米至約40奈米。在特定實施例中,硬罩幕圖案的寬度為約7奈米至約12奈米。
藉由使用硬罩幕圖案作為蝕刻罩幕,基材10係
被圖案化成鰭狀結構20,圖案化係使用亁式蝕刻法及/或溼式蝕刻法之溝渠蝕刻(Trench Etching)進行。鰭狀結構20之高度為約20奈米至約300奈米。在特定實施例中,上述高度為約30奈米至約60奈米。當鰭狀結構20之高度不平均時,可根據鰭狀結構20之平均高度的平面測量基材10的高度。鰭狀結構20之寬度為約7奈米至約15奈米。
在此實施例中,主體矽晶圓可作為起始材料並
構成基材10。然而,在一些實施例中,其他類型的基材也可作為基材10。例如:絕緣層上覆矽(SOI)晶圓可作為起始材料,絕緣層上覆矽晶圓之絕緣層構成基材10,而絕緣層上覆矽晶圓的矽層作為鰭狀結構20。
如圖2所示,三個鰭狀結構20係沿X方向延伸,
並沿Y方向彼此相鄰地設置。然而,鰭狀結構20的數量並不限於三個。鰭狀結構的數量可為一、二、四、五個或更多。
此外,可設置一個或更多的虛擬鰭狀結構(Dummy Fin Structure)與鰭狀結構20之二側相鄰,以改善圖案化製程中的圖案逼真度(Pattern Fidelity)。在一些實施例中,鰭狀結構20的寬度為約5奈米至40奈米,且在特定實施例中,可為約7奈米至約15奈米。在一些實施例中,鰭狀結構20的高度為約50奈米至約300奈米間,而在其他實施例中,高度可
為約50奈米至約100奈米。在一些實施例中,鰭狀結構20間的間隔為約5奈米至約80奈米,在其他實施例中,間隔可為約7奈米至約15奈米。然而,於本技術領域具有通常知識者應可了解,本案所揭露之尺寸及數值僅為舉例說明,且可配合適合的不同規模之積體電路變更上述之尺寸及數值。
在此實施例中,鰭狀場效電晶體為n型鰭狀場效電晶體。
形成鰭狀結構20後,將隔離絕緣層50形成於鰭狀結構20上。
隔離絕緣層50包括一或多層的絕緣材料,例如:氧化矽、氮氧化矽或氮化矽,並藉由低壓化學氣相沉積、電漿化學氣相沉積或可流動式化學氣相沉積形成。在可流動式化學氣相沉積中,沉積可流動介電材料而非氧化矽。正如其名,可流動介電材料在沉積過程中可「流動」,以填滿有高深寬比的空隙或間隔。一般而言,會添加各種化學物質至含矽先驅氣體中,以使沉積的薄膜流動。在一些實施例中,加入氮氫鍵。可流動介電先驅氣體,特別是可流動氧化矽先驅氣體之例子包括矽酸鹽、矽氧烷、甲基半矽氧烷(MSQ)、氫化半矽氧烷(HSQ)、甲基半矽氧烷/氫化半矽氧烷(MSQ/HSQ)、全氫矽氮烷(TCPS)、全氫聚矽氮烷(PSZ)、四乙氧基矽烷(TEOS)或如三矽烷基胺之矽烷基胺(TSA)。這些可流動氧化矽材料係在多重操作製程中形成。在可流動薄膜沉積後,進行硬化和退火來移除非預定的元素,以形成氧化矽。當非預定的元素被移除時,緻密化並收縮可流動薄膜。
在一些實施例中,進行多重退火製程。可流動薄膜係經過大於一次之硬化及退火。可流動薄膜可摻有硼及/或磷。在一些實施例中,隔離絕緣層50可藉由一或多層之旋轉塗佈玻璃(SOG)、氧化矽、氮氧化矽、碳氧氮化矽及/或氟摻質之矽酸鹽玻璃(FSG)來形成。
在形成隔離絕緣層50於鰭狀結構20上後,進行
平坦化步驟以移除部份之隔離絕緣層50以及罩幕層(墊氧化層和氮化矽罩幕層)。平坦化步驟可包括化學機械研磨(CMP)及/或回蝕製程。然後,再移除隔離絕緣層50,使得鰭狀結構20的上部分暴露出來,以將鰭狀結構20的上部分將變成通道層20A,如圖2所示。
在特定的實施例中,部分地移除隔離絕緣層50
之步驟可使用溼式蝕刻製程進行,例如:將基材浸泡於氫氟酸(HF)中。在其他實施例中,可使用亁式蝕刻製程,以部分地移除隔離絕緣層50。例如:可使用以三氟甲烷或三氟化硼作為蝕刻氣體之亁式蝕刻製程。
形成隔離絕緣層50後,可進行例如退火製程之
熱製程以改善隔離絕緣層50之品質。在特定實施例中,熱製程之進行係使用在如氮氣、氬氣或氦氣氣氛之惰性氣氛中,溫度為約900℃至約1050℃,持續時間為約1.5秒至約10秒之快速熱退火(RTA)。
在圖1之步驟S103中,閘極結構40係形成於部
分的鰭狀結構20上,如圖3所示。圖3係繪示根據本發明之一實施例之製造鰭狀場效電晶體的各個階段之一的例示側
視圖。圖4係繪示沿圖3之剖線a-a之例示剖面圖。
閘極介電層30和多晶矽層係形成於隔離絕緣
層50和暴露出的鰭狀結構20上。接著,進行圖案化步驟以得到閘極結構40,閘極結構40包括以多晶矽形成之閘極電極層45和閘極介電層30。在一些實施例中,可使用硬罩幕60進行多晶矽層之圖案化,其中硬罩幕60包括氮化矽層62和氧化層64。在其他實施例中,層62可為氧化矽,而層64可為氮化矽。閘極介電層30可為氧化矽,且以化學氣相沉積、物理氣相沉積、原子層沉積、電子束蒸發,或其他適合製程來形成。在一些實施例中,閘極介電層30可包括一或多層的氧化矽、氮化矽、氮氧化矽或高介電常數之介電材料。高介電常數之介電材料包含金屬氧化物。作為高介電常數之介電材料的金屬氧化物之例子包括鋰、鈹、鎂、鈣、鍶、鈧、釔、鋯、鉿、鋁、鑭、鈰、鐠、釹、釤、銪、釓、鋱、鏑、鈥、鉺、銩、鐿、鎦的氧化物及/或上述金屬氧化物之混合。在一些實施例中,閘極介電層30之厚度係約1奈米至約5奈米。在一些實施例中,閘極介電層30可包括由二氧化矽所形成之界面層(Interfacial layer)。
在一些實施例中,閘極電極層45可包含單層或
多層結構。閘極電極層45可為摻雜均勻或不均勻之摻雜多晶矽。在另一些實施例中,閘極電極層45可包括例如鋁、銅、鎢、鈦、鉭之金屬、氮化鈦、鈦鋁、氮化鈦鋁、氮化鉭、矽化鎳、矽化鈷、具有與基材材料相容之功函數的其他導電材料,或上述之組合。可使用例如原子層沉積、化學氣相沉
積、物理氣相沉積、電鍍或上述之組合等適合的製程來形成閘極電極層45。在此實施例中,閘極電極層45的寬度為約30奈米至約60奈米。在一些實施例中,閘極電極層45的厚度為約30奈米至約50奈米。
在圖1之步驟S105中,未被閘極結構40覆蓋之
鰭狀結構20係被向下蝕刻,以形成凹陷80,如圖5所示。圖5係繪示根據本發明之一實施例之製造鰭狀場效電晶體的各個階段之一的例示側視圖。圖6A係繪示沿圖5之剖線b-b之例示剖面圖。圖6B係繪示沿圖5之剖線c-c切入其中一個鰭狀結構20之例示剖面圖。而圖6C係繪示沿圖5之鰭狀結構20間的剖線d-d之例示剖面圖。
形成如圖4所示之閘極結構40後,側壁絕緣層
70也形成於閘極電極層45之二主側。側壁絕緣層70可包括氧化矽、氮化矽、氮氧化矽或其他適合的材料。側壁絕緣層70可包含單一層或多層結構。側壁絕緣材料之毯覆層可藉由化學氣相沉積、物理氣相沉積、原子層沉積或其他適合的技術所形成。然後,在側壁絕緣材料上進行非等向性蝕刻,以形成一對側壁絕緣層(間隙壁)70於閘極結構40之二主側上。在一實施例中,側壁絕緣層70之厚度T1為約5奈米至約15奈米。
未被閘極結構40覆蓋之部分的鰭狀結構20係
蝕刻至形成凹陷80,如圖5所示。鰭狀結構20係被蝕刻至與基材10等高,以完全地移除源極/汲極區之鰭狀結構20間的隔離絕緣層50。藉由蝕刻至與基材10等高,在源極/汲極區
之鰭狀結構20變成「合併」的鰭狀結構。在特定的實施例中,使用一對側壁絕緣層70作為硬罩幕,進行偏壓蝕刻製程(Biased Etching Process)使未受保護或暴露出的鰭狀結構20之頂面凹陷,以形成凹陷80。
上述形成凹陷80的蝕刻製程包括非等向性蝕
刻伴隨等向性蝕刻。非等向性蝕刻主要對鰭狀結構20的垂直方向(Z方向)進行蝕刻。在非等向性蝕刻後,進行等向性蝕刻,以蝕刻閘極結構40下的鰭狀結構20。
圖7A至圖7C繪示等向性蝕刻鰭狀結構20後之
鰭狀場效應電晶體的例示剖面圖。
藉由調整蝕刻條件(例如蝕刻時間),可控制閘
極結構40下之蝕刻量,並控制閘極電極層45和源極/汲極磊晶層(Source/Drain Epitaxial Layer)之間的近接距離Px(Proximity)。閘極電極層45和源極/汲極磊晶層間的近接距離Px係定義為從閘極電極層45之側壁所延伸之直線至凹陷80中的鰭狀結構20的表面之距離。
在圖7A中,近接距離Px為正值,且為大於0至
小於10奈米。在一些實施例中,近接距離Px為約1奈米至約7奈米。
在圖7B中,近接距離Px實質為0奈米。
在圖7C中,近接距離Px為負值,且為大於約-2奈米至小於0奈米。在一些實施例中,近接距離Px為等於或大於約-1奈米至小於0奈米(-1奈米≦Px<0奈米)。
在本發明之一實施例中,凹陷蝕刻製程的蝕刻
條件係依照預定達到的蝕刻圖案進行調整。例如:使用製程氣體包括甲烷、三氟甲烷、氧氣、溴化氫、氦氣、氯氣、三氟化氮及/或氮氣的變壓耦合電漿製程(Transform Coupled Plasma;TCP),並改變其功率及/或偏壓條件。
變壓耦合電漿蝕刻包括非等向性蝕刻伴隨等向性蝕刻。在等向性蝕刻中,偏壓電壓係設定為小於非等向性蝕刻之偏壓電壓。藉由等向性蝕刻,鰭狀結構20可在閘極結構40下被水平地蝕刻。
在圖1之步驟S107中,晶格差排結構
(dislocation structure)形成於基材10上。
如圖8所示,進行預非晶植入(Pre-Amorphous
Implantation;PAI)步驟。利用預非晶植入步驟將離子植入基材10中,破壞基材10之晶格結構,並形成非晶化區90。
在本實施例中,非晶化區90係形成於鰭狀場效電晶體200之源極和汲極區中,且些微穿透至閘極結構40下。非晶化區90之深度係根據設計決定,且可為約10奈米至約150奈米。在本實施例中,非晶化區90的深度係小於約100奈米。
非晶化區90之深度可藉由側壁絕緣層70的厚度來控制,因為側壁絕緣層70係用以集中遠離閘極結構40中心之植入能量,因此可達到較深的非晶化深度。此外,非晶化區90的深度可由植入能量、植入離子之種類及/或植入離子之劑量來控制。在本實施例中,植入離子之種類為矽(Si)及/或鍺(Ge)。另一種方式,植入離子之種類可為氬、氙、二氟化硼、砷、銦、其他適合的植入種類,或上述之組合。在本實
施例中,矽或鍺係以約20KeV至約60KeV之植入能量、植入劑量為約1×1014原子/平方公分(atoms/cm2)至約2×1015atoms/cm2來植入,以上條件係取決於植入溫度。
越低的植入溫度會加強植入非晶的效率。
可使用圖案化的光阻層定義非晶化區90的形
成區域,並保護鰭狀場效電晶體的其他區域免於離子植入時的傷害。例如:圖案化光阻層暴露出源極/汲極區,使得源極/汲極區暴露出來以進行預非晶植入步驟,而閘極結構40(或鰭狀場效電晶體的其他部分)係被保護而不進行非晶植入步驟。另一種方式,使用例如氮化矽或氮氧化矽層之圖案化硬罩幕層,以定義非晶化區90。圖案化光阻層或圖案化硬罩幕層可為目前製程(例如形成輕度摻質汲極(Lightly Doped Drain;LDD)或源極/汲極)的一部分,因此在預非晶植入步驟中,不需使用額外的光阻層或硬罩幕而減少花費。
如圖9所示,應力薄膜95係沉積於上述所得之
結構上。可使用化學氣相沉積、物理氣相沉積、原子層沉積、高密度電漿化學氣相沉積、電鍍、其他適合之製程及/或上述之組合,以形成應力薄膜95。應力薄膜95可包括例如氮化矽、氧化矽、氮氧化矽、其他適合材料及/或上述之組合的介電材料。應力薄膜95係用以提供應力,以在後續的退火步驟中再結晶非晶化區90。
請再參照圖9,對圖9所示之結構進行退火步
驟。退火步驟造成非晶化區90再結晶,以形成再結晶區
100。退火步驟可為快速熱退火(RTA)製程或毫秒熱退火(MSA)製程(例如:毫秒雷射熱退火步驟)。
退火步驟可包括遠程預熱(Long Range
Pre-Heat),以減少或甚至消除射程末端(End of Range)缺陷。遠程預熱可於約200℃至約700℃之溫度下進行。遠程預熱可進行約50秒至約300秒。退火步驟可於約500℃至約1400℃之溫度下進行。此外,視所使用的退火步驟的類型和溫度而定,退火步驟可進行約1毫秒至約5秒。在此實施例中,遠程預熱係在約550℃之溫度下進行約180秒。此外,在本實施例中,退火步驟為快速熱退火製程,且使用大於約1000℃之溫度並進行大於1.5秒。在一些實施例中,退火步驟為毫秒雷射熱退火製程,且使用最高至矽熔點之約1400℃之溫度並進行幾毫秒或更少,例如:約0.8毫秒至約100毫秒。
在退火步驟的過程中,由於非晶化區90再結
晶,晶格差排105係形成於再結晶區100中。晶格差排105係形成於矽基材10之<111>方向上。根據平行於基材10之表面的軸測量,前述<111>方向具有約45度至約65度之角度。在本實施例中,根據平行於基材10之表面的軸測量,晶格差排105之<111>方向的角度為約55度。
晶格差排105係於夾止點(Pinchoff
Point)106開始形成。夾止點106係形成於再結晶區100之深度為約10奈米至約150奈米處,上述之深度係從凹陷80之底面進行測量。可形成夾止點106,並且夾止點106不設
於閘極結構40或鰭狀結構20(通道層20A)之下。
在退火步驟後,應力薄膜95係以例如溼式蝕刻
移除。在溼式蝕刻中可使用磷酸或氫氟酸。在一些實施例中,也可使用亁式蝕刻。
在圖1之步驟S109中,以適合的材料磊晶生長
形成源極和汲極。藉由使用不同於通道層20A的材料作為源極和汲極,通道層20A係適當地應變(Strained),因此可增加通道層20A中的載子流通性。
圖10A至圖10C分別繪示形成源極和汲極之磊
晶層於如圖7A至圖7C之結構後之例示剖面圖。
第一磊晶層110係形成於凹陷80的底部,也就
是暴露出的基材10。第一磊晶層110係作為通道應力源,提供拉伸應力至通道層20A。在此實施例中,第一磊晶層110包括碳化矽磷(SiCP)。碳化矽磷中的碳濃度係由X射線繞射分析法(XRD)進行測量,且碳濃度為約1%至約5%。在一些實施例中,碳濃度為約1.2%至約4%,且在另一實施例中可為約2%至約3%。碳化矽磷中的磷含量為約1×1018cm-3至約1×1020cm-3。在此實施例中,第一磊晶層110的厚度可為約5奈米至約20奈米,且在其他實施例中,第一磊晶層110的厚度可為約5奈米至約15奈米。
如圖10A至圖10C所示,第一磊晶層110係直接
接觸鰭狀結構20(通道層20A和井層(Well Layer)20B),且因為第一磊晶層110含有碳,碳可牽制矽和磷的間隙(Interstitial),並抑制碳化矽磷第一磊晶層110的磷擴散至
通道層20A中,因此可抑制短通道效應。第一磊晶層110的電阻值為約0.8mΩ‧cm至約1.2mΩ‧cm。
大體而言,當近接距離Px減少時,會增加通道
應力源的效果,使得短通道效應變得更嚴重。然而,當碳化矽磷第一磊晶層110包括碳時,可抑制磷的擴散,則可能減少近接距離Px,如圖10A至圖10C所示。
在圖10A中,近接距離Px為正值,且近接距離
Px為大於0至小於10奈米。在一些實施例中,近接距離Px為約1奈米至約7奈米。在圖10A中,通道層20A和源極/汲極磊晶層(例如第一磊晶層110)間的界面係位於側壁絕緣層70之正下方。
在圖10B中,近接距離Px實質為0奈米。在圖
10B中,通道層20A和源極/汲極磊晶層(例如第一磊晶層110)間的界面係位於側壁絕緣層70和閘極電極層45間的界面之正下方。
在圖10C中,近接距離Px為負值,且近接距離
Px為大於約-2奈米至小於0奈米。在一些實施例中,近接距離Px為等於或大於約-1奈米至小於0奈米(-1奈米≦Px<0奈米)。在圖10C中,通道層20A和源極/汲極磊晶層(例如第一磊晶層110)間的界面係位於閘極電極層45之正下方。
閘極電極層45和源極/汲極磊晶層間的近接距
離Px可用另一種方式定義。例如:在近接距離Px>0的情況下,近接距離Px與通道層20A的寬Wc滿足“閘極電極層之寬Wg”<Wc<Wg+2ד側壁絕緣層的厚度T”。在近接距離
Px=0的情況下,Wc等於Wg。而在近接距離Px<0的情況下,Wc小於Wg。
在形成第一磊晶層110後,第二磊晶層120係形
成於第一磊晶層110上。第二磊晶層120係用作主要通道應力源,以提供拉伸應力至通道層20A。在此實施例中,第二磊晶層120包括碳化矽磷。碳化矽磷第二磊晶層120的碳濃度係以X射線繞射分析法測量,碳化矽磷第二磊晶層120的碳濃度係小於碳化矽磷第一磊晶層110的碳濃度,且碳化矽磷第二磊晶層120的碳濃度可為約0.7%至約3%。在一些實施例中,碳濃度可為約1%至約3%,且在另一實施例中碳濃度可為約1.2%至約2.5%。碳化矽磷第二磊晶層120的磷含量係高於碳化矽磷第一磊晶層110的磷含量,且碳化矽磷第二磊晶層120的磷含量可為1×1020cm-3至2×1020cm-3。在此實施例中,第二磊晶層120的厚度可為約20奈米至約40奈米,或在其他實施例中,第二磊晶層120的厚度可為約25奈米至約35奈米。第二磊晶層120的電阻值可為約0.3mΩ‧cm至約1.0mΩ‧cm。
在形成第一磊晶層110和第二磊晶層120的過
程中,形成於基材10的晶格差排105會生長至第一磊晶層110和第二磊晶層120中。形成於第一磊晶層110和第二磊晶層120中的晶格差排105為對通道層20A額外的應力源來源。
在形成第二磊晶層120後,第三磊晶層130也可
形成於第二磊晶層120上。第三磊晶層130亦係用作通道應
力源,以提供拉伸應力至通道層20A。在此實施例中,第三磊晶層130包括磷化矽(SiP)。磷化矽層可包括虛擬立方(Pseudocubic)的磷化矽(Si3P4)。磷化矽第三磊晶層130的磷含量係高於碳化矽磷第二磊晶層120的磷含量,且在一些實施例中,磷化矽第三磊晶層130的磷含量可為約1×1021cm-3至約1×1022cm-3。在其他實施例中,磷化矽第三磊晶層130的磷含量可為約2×1021cm-3至約5×1021cm-3。在一些實施例中,第三磊晶層130的厚度為約1奈米至約25奈米,在其他實施例中,第三磊晶層130的厚度可為約2奈米至約10奈米。
第三磊晶層130的頂面可與在閘極結構40下之
鰭狀結構20的頂面之高度相同,或可位於較閘極結構40下的鰭狀結構20高一點(約1奈米至約5奈米)的地方。
藉由使用多層應力源結構的第一磊晶層110、
第二磊晶層120至第三磊晶層130,可抑制短通道效應,以增加提供給通道層的應力。
在上述實施例中,磊晶層的數量僅為三個。在
一些實施例中,可形成額外的磊晶層於第三磊晶層上。額外的磊晶層可包括含硼的磷化矽。額外的磊晶層之硼含量可高於第三磊晶層130之硼含量。
此外,可形成第四層140於第三磊晶層130上。
第四層140可包括磷化矽磊晶層。第四層140為犧牲層,以於源極/汲極中形成矽化物(Silicide)。磷化矽第四層140的磷含量係小於磷化矽第三磊晶層130之磷含量,且在一些實
施例中,磷化矽第四層140的磷含量可為約1×1018cm-3至約1×1020cm-3。
在至少一實施例中,第一磊晶層110、第二磊
晶層120、第三磊晶層130和第四層140係以低壓化學氣相沉積(LPCVD)製程或原子層沉積方法磊晶生長。低壓化學氣相沉積係於約400℃至約800℃之溫度和約1至200Torr之壓力下進行,並使用如甲矽烷(SiH4)、乙矽烷(Si2H6)或丙矽烷(Si3H8)之矽源氣體,如甲烷或單甲基矽烷(SiH3CH)之碳源氣體和如磷化氫(PH3)之磷源氣體。
在上述實施例中,在凹陷蝕刻中,鰭狀結構之
蝕刻係以乾式蝕刻進行。亦可進行溼式蝕刻來取代乾式蝕刻。
溼式蝕刻可使用四甲基氫氧化銨(TMAH)來進
行。在以四甲基氫氧化銨進行矽的溼式蝕刻中,矽(100)面的蝕刻速率快於矽(111)面的蝕刻速率。因此,當基材10為(100)矽晶體基材且鰭狀結構20以四甲基氫氧化銨蝕刻時,凹陷80的剖面圖具有如圖11所示之偏斜末端82。藉由調整蝕刻條件,偏斜末端82的所在位置可被調整,因此調整近接距離Px。
如圖12所示,第一磊晶層110、第二磊晶層
120、第三磊晶層130和第四層140係由四甲基氫氧化銨溼式蝕刻,形成於凹陷80中。在一些實施例中,可結合乾式蝕刻和溼式蝕刻。
在上述實施例中,在凹陷蝕刻中的複數個鰭狀
結構被合併。然而,如前所述之結構和製造步驟過程可應用於單一鰭狀結構的鰭狀場效電晶體或具有複數個鰭片但未合併源極/汲極結構的鰭狀場效電晶體。在具有複數個鰭片但未合併源極/汲極結構的鰭狀場效電晶體中,可進行凹陷蝕刻至與基材等高,或可在與基材等高前完成。
於本技術領域具有通常知識者應可知,鰭狀場
效電晶體可更進一步進行互補式金氧半場效電晶體(CMOS)製程,以形成例如接觸/接觸窗、內連金屬層、介電層、鈍化層等之各種特徵。經過修飾的絕緣和應變結構提供預定數量的應變(Strain)至鰭狀場效電晶體的通道層20A中,因此增強了裝置的效能。
在此所舉出的實施例或例示提供較先前技術優
異之諸多優點。例如:藉由減少閘極電極層和源極/汲極磊晶層(第一磊晶層)間的近接距離,但第一磊晶層中包括碳,可抑制因磷擴散至通道層所造成的短通道效應,以增加提供至通道層的應力。
值得一提的是,並非所有優點皆於此處提及,
並非所有實施例或例示必須具有特定的優點,且其他實施例或例示可能提供不同的優點。
根據本發明之一態樣,半導體元件包括鰭狀場
效電晶體。鰭狀場效電晶體包括設於基材上的鰭狀結構。鰭狀結構包括通道層,且鰭狀結構係沿第一方向延伸。鰭狀場效電晶體也包括閘極結構,閘極結構包括閘極電極層和閘極介電層,閘極結構係覆蓋鰭狀結構的一部分,且閘極結構係
沿垂直於第一方向之第二方向延伸。閘極結構更包括設於閘極電極層之二主側上的側壁絕緣層。鰭狀場效電晶體更包含源極和汲極,源極和汲極的每一者包括設於未被閘極結構覆蓋之凹陷中的應力源層。應力源層包括第一應力源層、於第一應力源層上的第二應力源層,和於第二應力源層上的第三應力源層。在源極中,第一應力源層和通道層間的界面係位於較靠近源極或閘極電極層之一者的側壁絕緣層的下方。
根據本發明之另一態樣,半導體元件包括鰭狀
場效電晶體。鰭狀場效電晶體包括設於基材上的鰭狀結構。
鰭狀結構包括通道層,且鰭狀結構係沿第一方向延伸。鰭狀場效電晶體也包括閘極結構,閘極結構包括閘極電極層和閘極介電層,閘極結構係覆蓋鰭狀結構的一部分,且閘極結構係沿垂直於第一方向之第二方向延伸。閘極結構更包括設於閘極電極層之二主側上的側壁絕緣層。鰭狀場效電晶體更包含源極和汲極,源極和汲極的每一者包括設於未被閘極結構覆蓋之凹陷中的應力源層。應力源層包括第一應力源層、於第一應力源層上的第二應力源層,和於第二應力源層上的第三應力源層。在源極中,第一應力源層和通道層間的界面係位於較靠近源極或閘極電極層之側壁絕緣層中的一者下。通道層沿第一方向的寬係小於閘極電極層的寬和沿第一方向延伸之側壁絕緣層的寬的總合。
根據本發明之又一態樣,製造半導體元件的方
法包括形成鰭狀結構於基材上。鰭狀結構包括從隔離絕緣層上暴露出的通道層,且鰭狀結構係沿第一方向延伸。閘極結
構包括閘極電極層和閘極介電層,且閘極結構係形成於部分的鰭狀結構上。閘極結構沿垂直於第一方向之第二方向延伸。閘極結構更包括設於閘極電極層之二主側上的側壁絕緣層。藉由移除未被閘極結構覆蓋的部分鰭狀結構,以形成凹陷。源極和汲極係形成於凹陷中,源極和汲極的每一者包括應力源層。應力源層包括第一應力源層、於第一應力源層上的第二應力源層,和於第二應力源層上的第三應力源層。形成凹陷使得在源極中,第一應力源層和通道層間的界面係位於較靠近源極或閘極電極層之側壁絕緣層中的一者下。
雖然本發明參考所繪示的實施例進行說明,但其並非用以限制本發明。熟悉此技藝者應可輕易利用所繪示的實施例、其他本發明的實施例以及本發明之說明,進行各種潤飾及結合。因此所附加之申請專利範圍係包含任何上述之潤飾或實施例。
105‧‧‧晶格差排
110‧‧‧第一磊晶層
120‧‧‧第二磊晶層
130‧‧‧第三磊晶層
140‧‧‧第四層
Px‧‧‧近接距離
Claims (19)
- 一種包含鰭狀結構之半導體元件,包含一鰭狀場效電晶體,包括一鰭狀結構,設於一基材上,其中該鰭狀結構包括一通道層,且該鰭狀結構係沿一第一方向延伸;一閘極結構,包括一閘極電極層和一閘極介電層,其中該閘極結構覆蓋該鰭狀結構的一部分,該閘極結構係沿垂直於該第一方向之一第二方向延伸,且該閘極結構更包括複數個側壁絕緣層,該些側壁絕緣層係設於該閘極電極層之二主側上;以及一源極和一汲極,其中該源極和該汲極之每一者包括一應力源層,該應力源層設於一凹陷中,且該凹陷係於未被該閘極結構覆蓋之該鰭狀結構中,其中該應力源層包括一第一應力源層、於該第一應力源層上的一第二應力源層,以及於該第二應力源層上的一第三應力源層,該第一應力源層之碳濃度係高於該第二應力源層之碳濃度,且在該源極中,該第一應力源層和該通道層間的一界面係位於靠近該源極或該閘極電極層之該些側壁絕緣層之一者下,該第一應力源層係直接接觸該些側壁絕緣層之一者的一底部,以及該第二應力源層與該第三應力源層之間的一界面係不位於該閘極結構下。
- 如申請專利範圍第1項所述之包含鰭狀結構之半導體元件,其中該第一應力源層包括碳化矽磷 (SiCP),以及該第二應力源層包括碳化矽磷。
- 如申請專利範圍第2項所述之包含鰭狀結構之半導體元件,其中該第二應力源層之磷含量係高於該第一應力源層之磷含量。
- 如申請專利範圍第3項所述之包含鰭狀結構之半導體元件,其中該第三應力源層包括磷化矽,且該第三應力源層之磷含量高於該第二應力源層之磷含量。
- 如申請專利範圍第1項所述之包含鰭狀結構之半導體元件,其中該鰭狀結構包括多個鰭片於該閘極結構下,並為該些鰭片提供一個該源極和一個該汲極。
- 如申請專利範圍第5項所述之包含鰭狀結構之半導體元件,其中該源極和該汲極具有一合併鰭狀結構。
- 如申請專利範圍第1項所述之包含鰭狀結構之半導體元件,更包含一晶格差排,從該基材延伸至該應力源層。
- 如申請專利範圍第1項所述之包含鰭狀結構之半導體元件,其中該鰭狀場效電晶體為一n型鰭狀場效電晶體。
- 如申請專利範圍第1項所述之包含鰭狀結構之半導體元件,其中該界面係定義為該應力源層最靠近該通道層之一點。
- 如申請專利範圍第1項所述之包含鰭狀結構之半導體元件,其中在該源極中,該界面係位於靠近該源極之該側壁絕緣層之一者的正下方。
- 如申請專利範圍第1項所述之包含鰭狀結構之半導體元件,其中在該源極中,該界面係位於一平面上,且該平面係延伸自該閘極電極層和靠近該源極之該側壁絕緣層之一者的一界面。
- 如申請專利範圍第1項所述之包含鰭狀結構之半導體元件,其中在該源極中,該界面係位於該閘極電極層之正下方,該界面和一平面間的距離係等於或小於1奈米,且該平面係延伸自該閘極電極層和靠近該源極之該側壁絕緣層之一者的一界面。
- 一種包含鰭狀結構之半導體元件,包含:一鰭狀場效電晶體,包括:一鰭狀結構,設於一基材上,其中該鰭狀結構包括一通道層,且該鰭狀結構係沿一第一方向延伸;一閘極結構,包括一閘極電極層和一閘極介電層, 其中該閘極結構覆蓋該鰭狀結構之一部分,該閘極結構係沿垂直於該第一方向之一第二方向延伸,該閘極結構更包括複數個側壁絕緣層,且該些側壁絕緣層係設於該閘極電極層之二主側上;以及一源極和一汲極,該源極和該汲極之每一者包括一應力源層,該應力源層設於一凹陷中,且該凹陷係於未被該閘極結構覆蓋之該鰭狀結構中,其中該應力源層包括一第一應力源層、於該第一應力源層上的一第二應力源層,以及於該第二應力源層上的一第三應力源層,該通道層沿該第一方向之一寬度係小於該閘極電極層之一寬度以及該些側壁絕緣層沿該第一方向之寬度的總合,且該第一應力源層之碳濃度係高於該第二應力源層之碳濃度。
- 如申請專利範圍第13項所述之包含鰭狀結構之半導體元件,其中該通道層之該寬度為在該閘極結構下之一最小寬度。
- 一種包含鰭狀結構之半導體元件的製造方法,包含:形成一鰭狀結構於一基材上,其中該鰭狀結構包括自一隔離絕緣層暴露出的一通道層,且該鰭狀結構係沿一第一方向延伸;形成一閘極結構於該鰭狀結構的一部分上,該閘極結構包括一閘極電極層和一閘極介電層,其中該閘極結構係 沿垂直於該第一方向之一第二方向延伸,且該閘極結構更包括複數個側壁絕緣層,該些側壁絕緣層係設於該閘極電極層之二主側上;藉由移除未被該閘極結構覆蓋之該鰭狀結構的一部分,以形成一凹陷;植入離子至該凹陷的底部;形成一源極和一汲極於該凹陷中,其中該源極和該汲極之每一者包括一應力源層,且該應力源層係形成於被植入該離子之該凹陷的該底部上;以及退火具有該應力源層之該基材,以形成一晶格差排,其中該應力源層包括一第一應力源層、於該第一應力源層上的一第二應力源層,以及於該第二應力源層上的一第三應力源層,且所形成之該凹陷使得在該源極中,該第一應力源層和該通道層間的一界面係位於靠近該源極或該閘極電極層之該些側壁絕緣層之一者下。
- 如申請專利範圍第15項所述之包含鰭狀結構之半導體元件的製造方法,其中該鰭狀結構包括多個鰭片於該閘極結構下,且在形成該凹陷之步驟中,未被該閘極結構覆蓋之該鰭狀結構的一部分係被蝕刻至與該基材水平,使得該些鰭片間不保留有該隔離絕緣層。
- 如申請專利範圍第15項所述之包含鰭狀結構之半導體元件的製造方法,其中該第一應力源層包括磊晶形成的碳化矽磷,該第二應力源層包括磊晶形成的碳 化矽磷,且該第一應力源層之碳濃度係高於該第二應力源層之碳濃度。
- 如申請專利範圍第17項所述之包含鰭狀結構之半導體元件的製造方法,其中該第三應力源層包括磊晶形成的磷化矽,該第二應力源層之磷含量係高於該第一應力源層之磷含量,且該第三應力源層之磷含量高於該第二應力源層之磷含量。
- 如申請專利範圍第18項所述之包含鰭狀結構之半導體元件的製造方法,更包含形成一第四層於該第三應力源層上,其中該第四層包括磷化矽,且該第四層之磷含量小於該第三應力源層之磷含量。
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US20180254346A1 (en) | 2018-09-06 |
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