TW202220101A - 半導體裝置的形成方法 - Google Patents

半導體裝置的形成方法 Download PDF

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TW202220101A
TW202220101A TW110129914A TW110129914A TW202220101A TW 202220101 A TW202220101 A TW 202220101A TW 110129914 A TW110129914 A TW 110129914A TW 110129914 A TW110129914 A TW 110129914A TW 202220101 A TW202220101 A TW 202220101A
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Taiwan
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layer
distance
dielectric
gate
metal layer
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TW110129914A
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朱龍琨
黃懋霖
徐崇威
余佳霓
江國誠
王志豪
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台灣積體電路製造股份有限公司
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Abstract

製作裝置的方法包括：提供自基板延伸的鰭狀物，且鰭狀物包括多個半導體層，其中相鄰的半導體層之間具有第一距離。方法更包括提供自基板延伸並與半導體層相鄰的介電鰭狀物，其中每一半導體層的末端與介電鰭狀物的第一側壁之間具有第二距離。第二距離大於第一距離。沉積介電層於半導體層與介電鰭狀物的第一側壁上。形成第一金屬層於半導體層與介電鰭狀物的第一側壁上的該介電層上，其中位於相鄰的半導體層之上與之間的第一金屬層的部分合併在一起。最後移除第一金屬層。

Description

半導體裝置的形成方法
本發明實施例一般關於積體電路裝置，更特別關於多閘極裝置如全繞式閘極裝置。
電子產業對更小且更快的電子裝置的需求持續成長，且電子裝置可同時支援大量的複雜功能。為符合這些需求，積體電路產業中的持續趨勢為製造低成本、高效能、與低能耗的積體電路。因此達成這些目標的主要方法為減少積體電路尺寸(如最小積體電路結構尺寸)，進而改善產能與降低相關成本。然而尺寸縮小通常會增加積體電路製造製程的複雜度。因此為了實現積體電路裝置與其效能的進展，積體電路的製造製程與技術需要類似進展。
近來已導入多閘極裝置以改善閘極控制。多閘極裝置具有閘極結構於通道區的至少兩側上，可增加閘極通道耦合、降低關閉狀態電流、及/或減少短通道效應。多閘極裝置之一為全繞式閘極裝置，其閘極結構可延伸以完全包覆通道區。全繞式閘極裝置可大幅減少積體電路尺寸、維持閘極控制、並緩解短通道效應，且可無縫整合至習知的積體電路製造製程。隨著全繞式閘極裝置持續縮小，越來越難以由現有的金屬閘極蝕刻技術增加裝置密度。
本發明實施例之例示性的半導體裝置的形成方法，包括：提供自基板延伸的鰭狀物，且鰭狀物包括多個半導體層。相鄰的半導體層之間具有第一距離。方法更包括提供自基板延伸並與半導體層相鄰的介電鰭狀物。每一半導體層的末端與介電鰭狀物的第一側壁之間具有第二距離。第二距離大於第一距離。方法更包括沉積介電層於半導體層與介電鰭狀物的第一側壁上。方法更包括形成第一金屬層於半導體層與介電鰭狀物的第一側壁上的介電層上，其中位於相鄰的半導體層之上與之間的第一金屬層的部分合併在一起。方法更包括移除第一金屬層。
另一例示性的半導體裝置的形成方法包括形成自基板延伸的第一半導體層堆疊，其中第一半導體層堆疊的相鄰半導體層之間具有第一距離。形成自基板延伸的介電鰭狀物，其中第一半導體層堆疊與介電鰭狀物的第一側壁相鄰，且第一半導體層堆疊的半導體層的末端與介電鰭狀物的第一側壁之間具有第二距離。方法更包括形成自基板延伸並與介電鰭狀物的第二側壁相鄰的第二半導體層堆疊，第二側壁與第一側壁相對，且第二半導體層堆疊的相鄰半導體層之間具有第一距離。方法更包括沉積金屬層於第一半導體層堆疊、第二半導體層堆疊、與介電鰭狀物上。
例示性的半導體裝置包括介電鰭狀物自基板延伸。第一通道層位於基板上並與介電鰭狀物的第一側壁相鄰。第二通道層位於第一通道層上，其中第一通道層與第二通道層之間具有第一距離。第三通道層位於基板上並與介電鰭狀物的第二側壁相鄰，其中介電鰭狀物的第二側壁與第三通道層的末端之間具有第二距離，且介電鰭狀物的第一側壁與第二側壁相對。
下述詳細描述可搭配圖式說明，以利理解本發明的各方面。值得注意的是，各種結構僅用於說明目的而未按比例繪製，如本業常態。實際上為了清楚說明，可任意增加或減少各種結構的尺寸。
下述內容提供的不同實施例或實例可實施本發明的不同結構。此外，本發明之多個實例可重複採用相同標號以求簡潔，但多種實施例及/或設置中具有相同標號的元件並不必然具有相同的對應關係。下述特定構件與排列的實施例係用以簡化本發明內容而非侷限本發明。舉例來說，形成第一構件於第二構件上的敘述包含兩者直接接觸的實施例，或兩者之間隔有其他額外構件而非直接接觸的實施例。此外，本發明實施例之結構形成於另一結構上、連接至另一結構、及/或耦接至另一結構中，結構可直接接觸另一結構，或可形成額外結構於結構及另一結構之間。
此外，空間性的相對用語如「下方」、「其下」、「下側」、「上方」、「上側」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件，而非侷限於圖示方向。元件亦可轉動90°或其他角度，因此方向性用語僅用以說明圖示中的方向。
值得注意的是，本發明實施例以多閘極電晶體作說明。多閘極裝置的閘極結構可形成於通道區的至少兩側上。這些多閘極裝置可包含p型金氧半多閘極裝置或n型金氧半多閘極裝置。此處的具體例子因鰭狀結構而可視作鰭狀場效電晶體，此處所述的實施例中的多閘極電晶體可視作全繞式閘極裝置。全繞式閘極裝置包括閘極結構或其部分形成於通道區的四側上(比如圍繞通道區的一部分)的任何裝置。此處所述的實施例中的裝置亦可包含位於奈米片通道、奈米線通道、棒狀通道、及/或其他合適通道設置中的通道區。此處所述的實施例中的裝置可具有一或多個通道區(如奈米線或奈米片)以與單一的連續閘極結構相關。然而本技術領域中具有通常知識者應理解，此教示可用於單一通道(如單一奈米線或奈米片)或任何數目的通道。本技術領域中具有通常知識者應理解其他例子的半導體裝置亦可得利於本發明實施例。
本發明實施例比現有技術提供更多優點，但應理解其他實施例可提供不同優點，此處不必說明所有優點，且所有實施例不必具有特定優點。舉例來說，此處所述的實施例包含的方法與結構可提供進階的空間方案，有助於自對準閘極圖案化。在多種實施例中，揭露的空間方案可使裝置更靠近在一起並具有更緊密的空間需求，以形成更多裝置於單一晶圓上。在一些實施例中，下述的空間需求可使自對準金屬閘極圖案化步驟，優於採用習知技術的先前可行方法。本技術領域中具有通常知識者可依據本發明實施例的內容達到其他實施例與優點。
圖1係本發明多種實施例中，製作多閘極裝置的方法100之流程圖。在一些實施例中，方法100可採用自對準金屬閘極圖案化製程以製作多閘極裝置。下述方法100與製作全繞式閘極裝置相關。然而應理解方法100的實施例在未偏離本發明實施例的範疇時，同樣可實施至其他種類的多閘極裝置，或多閘極裝置所實施的其他種類裝置。
應理解的是，方法100包括具有互補式金氧半技術製程流程特徵的步驟，因此僅簡述這些步驟於此。此外，可在方法100之前、之後、及/或之中進行額外步驟。
方法100一開始的步驟102提供部分製作的多閘極裝置200。如圖2A至2C所示，一實施例的步驟102提供部分製作的多閘極裝置200。圖2A係多閘極裝置200在X-Y平面中的上視圖，圖2B係多閘極裝置200沿著圖2A的平面A-A'的X-Z平面之剖視圖，且圖2C係多閘極裝置200沿著圖2A的平面B-B'的Y-Z平面之剖視圖。如圖2A所示，多閘極裝置200形成於基板上，且包含多個鰭狀物204、多個介電鰭狀物208、與多個閘極間隔物210。為了簡化圖式，圖2A只顯示兩個鰭狀物204、三個介電鰭狀物208、與兩個閘極間隔物210。然而應理解多閘極裝置200可依需求含有更多鰭狀物、介電鰭狀物、與閘極間隔物。鰭狀物204垂直於閘極間隔物210，且閘極間隔物210隔有介電鰭狀物。此外，鰭狀物204沿著平面B-B'隔有介電鰭狀物208，如下所述。
圖2B及2C所示，多閘極裝置200包括鰭狀物204，其具有基板部分202 (由基板形成)與半導體層206。在所述實施例中，基板與基板部分202可包含矽。基板與基板部分可改為或額外包含另一半導體元素如鍺、半導體化合物(如碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦)、半導體合金(如矽鍺、磷砷化鎵、砷化鋁銦、砷化鋁鎵、砷化鎵銦、磷化鎵銦、及/或磷砷化鎵銦)、或上述之組合。基板可為絕緣層上半導體基板如絕緣層上矽基板、絕緣層上矽鍺基板、或絕緣層上鍺基板。絕緣層上半導體基板的製作方法可採用分開佈植氧、晶圓接合、及/或其他合適方法。基板與基板部分202可包含多種摻雜區，端視多閘極裝置200的設計需求而定。
鰭狀物204自多閘極裝置200的通道區中的基板202延伸並位於其上。通道區位於多閘極裝置200的個別源極/汲極區之間。如圖2C所示，鰭狀物204包括沿著z方向垂直堆疊的多個半導體層206。在一些實施例中，鰭狀物204的形成方法係以交錯設置的方式磊晶成長第一種半導體層(如半導體層206)與第二種半導體層。舉例來說，可磊晶成長第二種半導體層的第一者於鰭狀物204的基板部分202上，磊晶成長半導體層206的第一者於第二種半導體層的第一者上，磊晶成長第二種半導體層的第二者於半導體層206的第一者上，並以此類推，直到鰭狀物204具有所需數目的第一種半導體層(如半導體層206)與第二種半導體層。在一些實例中，第一種半導體層與第二種半導體層可視作磊晶層。在一些實施例中，磊晶成長第一種半導體層與第二種半導體層的方法可為分子束磊晶製程、化學氣相沉積製程、有機金屬化學氣相沉積製程、其他合適的磊晶成長製程、或上述之組合。
如圖2C所示，接著自多閘極裝置200的通道區選擇性移除第二種半導體層，可保留半導體層206以定義多閘極裝置200所用的通道層。在所述實施例中，移除第二種半導體層可提供三個通道層(如半導體層206)，且在操作多閘極裝置200時的電流可流經個別的磊晶源極/汲極結構之間的通道層。在一些實施例中，移除第二種半導體層的步驟可是作通道釋放製程。在一些實施例中，每一通道層(如半導體層206)可具有奈米尺寸，且可視作奈米線。奈米通道層(如半導體層206)的部分懸空，使金屬閘極可物理接觸通道層的至少兩側。在全繞式閘極電晶體中，金屬閘極可物理接觸通道層的至少四側(如圍繞通道層)。在這些實施例中，懸空通道層的垂直堆疊可視作奈米結構。在一些實施例中，移除第二種半導體層之後，可進行蝕刻製程調整通道層如半導體層206的輪廓，以達所需的尺寸及/或所需的形狀(比如圓柱形如奈米線、矩形如奈米棒、片狀如奈米片、或類似形狀)。本發明的實施例更包括通道層如半導體層206 (奈米線)具有次奈米尺寸，端視多閘極裝置200的設計需求而定。
在一些實施例中，蝕刻製程可選擇性蝕刻第二種半導體層，並最小化地蝕刻(或不蝕刻)半導體層206。可調整多種蝕刻參數以選擇性蝕刻第二種半導體層，比如蝕刻劑組成、蝕刻溫度、蝕刻溶液濃度、蝕刻時間、蝕刻壓力、源功率、射頻偏電壓、射頻偏功率、蝕刻劑流速、其他合適的蝕刻參數、或上述之組合。舉例來說，選擇蝕刻製程所用的蝕刻劑，以較高速率蝕刻第二種半導體層(如矽鍺)的材料，並以較低速率蝕刻半導體層206的材料，比如蝕刻劑對第二種半導體層的材料具有高蝕刻選擇性。蝕刻製程為乾蝕刻製程、濕蝕刻製程、其他合適蝕刻製程、或上述之組合。在一些實施例中，乾蝕刻製程(如反應性離子蝕刻製程)採用含氟氣體(如六氟化硫)以選擇性蝕刻第二種半導體層。在一些實施例中，可調整含氟氣體與含氧氣體(如氧氣)的比例、蝕刻溫度、及/或射頻功率，以選擇性蝕刻矽鍺。在一些實施例中，濕蝕刻製程採用的蝕刻溶液包括氫氧化銨與水，以選擇性蝕刻第二種半導體層。在一些實施例中，化學氣相蝕刻製程採用氯化氫以選擇性蝕刻第二種半導體層。雖然圖式中有三層的半導體層206，應理解鰭狀物204中的半導體層206可更多或更少。
在一些實施例中，介電鰭狀物208與圖2C所示的通道區中的鰭狀物204相鄰。在一些實施例中，介電鰭狀物208的形成方法為填入溝槽以與鰭狀物204相鄰 (比如沉積於每一鰭狀物上)。在多種例子中，介電鰭狀物208的沉積方法可為化學氣相沉積製程、原子層沉積製程、物理氣相沉積製程、及/或其他合適製程。在一些例子中，沉積介電鰭狀物208的材料之後，可進行化學機械研磨製程以移除多餘的材料部分並平坦化多閘極裝置200的上表面。在一些實施例中，介電鰭狀物208可包含低介電常數的材料如碳氮化矽、碳氧化矽、碳氮氧化矽、或另一低介電常數的材料(如介電常數小於7的材料)。在一些例子中，介電鰭狀物208可包含高介電常數的材料如氧化鉿、氧化鋯、氧化鉿鋁、氧化鉿矽、氧化鋁、或另一高介電常數的材料(如介電常數大於7的材料)。介電鰭狀物208具有寬度wd。在一些實施例中，寬度wd介於約7 nm至約14 nm之間。在一些實施例中，介電鰭狀物208有助於自對準金屬閘極的蝕刻製程，如下詳述。
閘極間隔物210可與介電鰭狀物208相鄰，並位於頂部的半導體層206上。在一些實施例中，可在形成介電鰭狀物208之前形成閘極間隔物210。閘極間隔物210的形成方法可為任何合適製程，且可包含介電材料。介電材料可包含矽、氧、碳、氮、其他合適材料、或上述之組合(如氧化矽、氮化矽、氮氧化矽、碳化矽、碳氮化矽、碳氧化矽、或碳氮氧化矽)。舉例來說，可沉積包括矽與氮的介電層(如氮化矽層)於多閘極裝置200上，接著蝕刻(如非等向蝕刻)介電層以形成閘極間隔物210。在一些實施例中，閘極間隔物210包括多層結構，比如含氮化矽的第一介電層與含氧化矽的第二介電層。在一些實施例中，形成超過一組間隔物如密封間隔物、補償間隔物、犧牲間隔物、虛置間隔物、及/或主要間隔物，以與介電鰭狀物208相鄰。在這些實施方式中，多組間隔物包含的材料可具有不同的蝕刻速率。舉例來說，沉積並蝕刻含矽與氧的第一介電層(如氧化矽)，可提供第一組間隔物以與介電鰭狀物208相鄰。沉積並蝕刻含矽與氮的第二介電層(如氮化矽)，可形成第二組間隔物以與第一組間隔物相鄰。
圖2C顯示區域V t1與區域V t2。在一些實施例中，區域V t1與區域V t2具有相同的閘極組成。在一些實施例中，下述的方法與技術沉積第一金屬層於區域V t1及V t2上。接著沉積第二金屬層於區域V t1及V t2上。接著形成硬遮罩於區域V t1及V t2上。圖案化硬遮罩以自區域V t1上移除硬遮罩的一部分，而硬遮罩維持保護區域V t2。進行蝕刻製程以自區域V t1移除第二金屬層。在移除硬遮罩之後，區域V t1及V t2可各自具有不同的金屬閘極堆疊。在一些實施例中，不同的金屬閘極堆疊使形成於區域V t1與區域V t2的每一者中的裝置所用的臨界電壓不同。
圖3A至7A與圖3B至7B係本發明多種實施例的多種製作階段(比如與圖1的方法100相關的製作階段)中，多閘極裝置200的部分或全部的剖視圖。具體而言，圖3A至7A係多閘極裝置200沿著圖2A的平面A-A’的X-Z 平面之剖視圖， 而圖3B至7B 係多閘極裝置 200沿著圖2A的平面B-B’的Y-Z平面之剖視圖，以顯示圖2C中含有單一鰭狀物204與區域V t1的部分212。應注意的是，圖3B至7B顯示對應區域V t1的圖2C的部分212，但此只為了圖式清楚與說明目的。下述的方法與技術可用於製造區域V t2或任何其他裝置，其可為多閘極裝置200的部分。本發明實施例與此處所述的技術可用於多閘極裝置200的所有鰭狀物與區域。
圖3A顯示多閘極裝置200沿著圖2A的平面A-A’的X-Z平面之剖視圖，如上所述。圖3A顯示多閘極裝置200的上側部分(特別是鰭狀物204的頂部半導體層206)。在所述實施例中，閘極間隔物210位於鰭狀物204的頂部半導體層206上。閘極間隔物210延伸於第一方向(如Y方向)中，其與基板的上表面平行。
圖3B顯示多閘極裝置200沿著圖2A的平面B-B’的Y-Z平面之剖視圖，如上所述。圖3B顯示圖2C的部分212，其包含鰭狀物204位於基板上，如上所述。鰭狀物204包括基板部分202與半導體層206垂直(如Z方向)堆疊於基板部分202上。半導體層206具有第一距離d1 (或片對片的距離)於相鄰的半導體層206之間。在所述實施例中，鰭狀物204的基板部分202的上表面與最底部的半導體層206的下表面之間，隔有第一距離d1。選擇第一距離d1以確保後續沉積的金屬閘極層可合併於相鄰的半導體層206之間，如下所述。合併的金屬閘極層可確保適當的蝕刻，如下所述。此外，第一距離d1為確認其他距離所用的基本距離，如下所述。在一些實施例中，每一半導體層206之間的第一距離d1可為約8 nm至約13 nm。在一些實施例中，調整半導體層206的磊晶成長製程，以確保第一距離d1達到足夠尺寸。在一些實施例中，可調整移除第二半導體層的蝕刻製程，以確保第一距離d1達到足夠尺寸。
在一些實施例中，介電鰭狀物208與鰭狀物204相鄰，而閘極間隔物210與介電鰭狀物208相鄰(如沿著介電鰭狀物208的側壁)。在一些實施例中，第二距離d2或末端蓋距離，可分開鰭狀物204的每一半導體層206與閘極間隔物210。選擇第二距離d2以大於第一距離d1，可確保後續沉積的閘極金屬層合併於相鄰的半導體層206之間，如下所述。合併的金屬閘極層可確保適當的蝕刻，如下所述。第二距離d2比第一距離d1大了至少2 nm。在一些實施例中，鰭狀物204的半導體層206與閘極間隔物210之間的第二距離d2可為約10 nm至約15 nm。在一些實施例中，調整介電鰭狀物208的形成製程以確保第二距離d2具有足夠的尺寸。在一些實施例中，調整閘極間隔物210的沉積製程以確保第二距離d2具有足夠的尺寸。
如圖3A所示，閘極間隔物210實質上彼此平行且隔有第三距離d3。在一些實施例中，第三距離d3 (或閘極長度LG)可在第二方向(如X方向)中自第一閘極間隔物210延伸至第二閘極間隔物210，而第二方向垂直於第一方向並平行於基板的上表面。
選擇第三距離d3以大於第一距離d1，可確保後續沉積的金屬閘極層合併於相鄰的半導體層206之間，如下所述。合併的金屬閘極層可確保適當的蝕刻，如下所述。第三距離d3可比第一距離d1大至少1 nm。在一些實施例中，第三距離d3可為約9 nm至約14 nm。在一些實施例中，調整閘極間隔物210的沉積製程，以確保第三距離d3具有足夠的尺寸。
如上所述，第一距離d1、第二距離d2、與第三距離d3之間的關係可確保後續沉積的金屬層可合併於相鄰的半導體層206之間，如下所述。在一例中，若第一距離d1為N，則第二距離d2為N+2且第三距離d3為N+1。換言之，第二距離d2比第一距離d1大了約2 nm，且第三距離d3比第一距離d1大了約1 nm。在一些實施例中，第三距離d3比第一距離d1 大了約1 nm，而第二距離d2比第三距離d3大了約1 nm。在一些實施例中，第三距離d3比第一距離d1大至少1 nm，且第二距離d2比第一距離d1大至少2 nm。
方法100的步驟104接著沉積界面層於半導體層上。如圖4A及4B所示，形成界面層218於半導體層206上，包括包覆(圍繞)通道區中的半導體層206與基板部分202。在多種實施例中，界面層218不形成於閘極間隔物210上。雖然圖式中只有一個鰭狀物204與一個介電鰭狀物208，界面層218可沉積於多閘極裝置200的所有通道區上，比如圖2C所示的區域V t1與區域V t2。在一些實施例中，界面層218可包含介電材料如氧化矽、氧化鋁、氧化鉿矽、氮氧化矽、上述之組合、或其他合適材料。界面層218的形成方法可為化學氧化、熱氧化、原子層沉積、化學氣相沉積、及/或其他合適方法。在一些實施例中，界面層218的厚度可為約1 nm。在其他實施例中，界面層218的厚度可介於約0.5 nm至約2 nm。位於半導體層206上的界面層218的一部分，可垂直地(如Z方向)隔有第四距離d4，其小於第一距離d1。在一些實施例中，第四距離d4比第一距離d1小了約2 nm。在一些實施例中，第四距離d4比第一距離d1小了界面層218的約兩倍厚度。界面層218位於半導體層206上的一部分與閘極間隔物210水平地(如Y方向)隔有第五距離d5，其小於第二距離d2。在一些實施例中，第五距離d5約比第二距離d2小了界面層218的厚度。
方法100的步驟106接著沉積高介電常數的介電層於界面層上。如圖5A及5B所示，形成高介電常數的介電層220於界面層218上與閘極間隔物210 上(如沿著閘極間隔物210的側壁)。高介電常數的介電層220包括高介電常數的介電材料，比如氧化鉿、氧化鉿矽、矽酸鉿、氮氧化鉿矽、氧化鉿鑭、氧化鉿鉭、氧化鉿鈦、氧化鉿鋯、氧化鉿鋁、氧化鋯、二氧化鋯、氧化鋯矽、氧化鋁、氧化鋁矽、三氧化二鋁、氧化鈦、二氧化鈦、氧化鑭、氧化鑭矽、三氧化二鉭、五氧化二鉭、氧化釔、鈦酸鍶、氧化鋇鋯、鈦酸鋇、鈦酸鋇鍶、氮化矽、氧化鉿-氧化鋁合金、其他合適的高介電常數的介電材料、或上述之組合。高介電常數的介電材料通常可視作介電常數大於氧化矽的介電常數(約3.9)的介電材料。高介電常數的介電層220之形成方法可為此處所述的任何製程，比如原子層沉積、化學氣相沉積、物理氣相沉積、氧化為主的沉積製程、其他合適製程、或上述之組合。在一些實施例中，高介電常數的介電層220之厚度為約1.5 nm。在一些實施例中，高介電常數的介電層220之厚度介於約1 nm至約2.5 nm之間。
在一些實施例中，位於半導體層206的下表面上的高介電常數的介電層220的第一部分，與位於相鄰的半導體層206的上表面上的高介電常數的介電層220的第二部分隔有第六距離d6，其中第六距離d6小於第四距離d4。在一些實施例中，第六距離d6比第四距離d4小了高介電常數的介電層220的約兩倍厚度。在一些實施例中，半導體層206的側壁上的高介電常數的介電層220的第三部分，與閘極間隔物210的側壁上的高介電常數的介電層220的第四部分隔有第七距離d7，其小於第五距離d5。在一些實施例中，第七距離d7比第五距離d5小了高介電常數的介電層220的約兩倍厚度。在一些實施例中，閘極間隔物210的兩側側壁上的高介電常數的介電層220的第四部分與第五部分之間的距離為第八距離d8，其小於第三距離d3。在一些實施例中，第八距離d8比第三距離d3小了高介電常數的介電層220的約兩倍厚度。
方法100的步驟108接著沉積金屬層於高介電常數的介電層上。如圖6A及6B所示，形成金屬層222於多閘極裝置200上，特別是通道區中的高介電常數的介電層220上，以包覆(圍繞)半導體層206。在一些實施例中，可形成金屬層222直到其合併於相鄰的半導體層206之間與最底部的半導體層206與鰭狀物204的基板部分202之間。金屬層222的厚度可由下式表示：
Figure 02_image001
。在一些實施例中，金屬層222的厚度介於約6 nm至約8.5 nm之間。此厚度保證金屬層222可在相鄰的半導體層206之間合併，並保留足夠空間(如第十距離d10與第十一距離d11)以進行後續蝕刻製程，如下所述。在一些實施例中，金屬層222的第一部分與第二部分隔有第十距離d10。在一些實施例中，第十距離d10比第七距離d7小了金屬層222的約兩倍厚度。在一些實施例中，金屬層222的第二部分與第三部分隔有第十一距離d11。在一些實施例中，第十一距離d11為約2 nm。在一些實施例中，第十一距離d11大於約2 nm。
在一些實施例中，金屬層222可包含p型功函數層，其可包含任何合適的p型功函數材料，比如氮化鈦、氮化鉭、氮化鉭矽、釕、鉬、鋁、氮化鎢、碳氮化鎢、鋯矽化物、鉬矽化物、鉭矽化物、鎳矽化物、其他p型功函數材料、或上述之組合。在一些實施例中，當金屬層222包括p型功函數層時，金屬層222的形成方法可採用另一合適的沉積製程如化學氣相沉積、物理氣相沉積、高密度電漿化學氣相沉積、有機金屬化學氣相沉積、遠端電漿化學氣相沉積、電漿輔助化學氣相沉積、低壓化學氣相沉積、原子層化學氣相沉積、常壓化學氣相沉積、電鍍、其他沉積製程、或上述之組合。
在一些實施例中，金屬層222可包含n型功函數層，其可包含任何合適的n型功函數材料如鈦、鋁、銀、錳、鋯、鈦鋁、碳化鈦鋁、碳化鈦鋁矽、碳化鉭、碳氮化鉭、氮化鉭矽、鉭鋁、碳化鉭鋁、碳化鉭鋁矽、氮化鈦鋁、其他n型功函數材料、或上述之組合。在一些實施例中，當金屬層222包含n型功函數層時，金屬層222的形成方法可採用另一合適的沉積製程，比如化學氣相沉積、物理氣相沉積、高密度電漿化學氣相沉積、有機金屬化學氣相沉積、遠端電漿化學氣相沉積、電漿輔助化學氣相沉積、低壓化學氣相沉積、原子層化學氣相沉積、常壓化學氣相沉積、電鍍、其他沉積製程、或上述之組合。
在一些實施例中，金屬層222可包含兩個不同金屬層。舉例來說，一些實施例的第一金屬層可為p型功函數層，且沉積於第一金屬層上的第二金屬層可為n型功函數層。在一些實施例中，第一金屬層可為n型功函數層，且沉積於第一金屬層上的第二金屬層可為p型功函數層。在一些實施例中，第一金屬層不合併於相鄰的半導體層206之間，但第二金屬層合併於相鄰的半導體層206之間。
方法100的步驟110接著移除金屬層。如圖7A及7B所示，進行蝕刻製程224以移除金屬層222。在一些實施例中，蝕刻製程為濕蝕刻製程，其採用的蝕刻溶液對金屬層222具有高蝕刻選擇性。在一些實施例中，濕蝕刻製程實施一或多種濕蝕刻化學劑，以選擇性蝕刻金屬層222。可控制蝕刻製程的參數以確保完全移除金屬層222，比如蝕刻溫度、蝕刻溶液濃度、蝕刻時間、其他合適的濕蝕刻參數、或上述之組合。舉例來說，可調整蝕刻時間(比如暴露金屬層222至濕蝕刻溶液的時間)以完全移除金屬層222，而最小地蝕刻(或不蝕刻)高介電常數的介電層220。在所述實施例中，完全移除金屬層222而露出高介電常數的介電層220。在一些實施例中，金屬層222包括第一金屬層與第二金屬層，且只移除第二金屬層而露出第一金屬層。在一些實施例中，自第一裝置區(如區域V t1)移除金屬層222，而不自第二裝置區(如區域V t2)移除金屬層222。在多種例子中，自第一裝置區移除金屬層222的步驟造成每一區域V t1及V t2中的臨界電壓不同。在一些實施例中，圖案化的遮罩層可形成於第二裝置區(如區域V t2)上，以在自第一裝置區移除金屬層222的蝕刻製程時保護第二裝置區。在這些實施例中，蝕刻製程之後可移除圖案化的遮罩層，且移除方法可為光阻剝除製程或其他合適製程。
一般而言，可對多閘極裝置200進行後續製程以形成本技術領域已知的多種結構與區域。舉例來說，後續製程可形成多種接點/通孔/線路與多層內連線結構(如金屬層與層間介電層)於基板上，其設置以連接多種結構以形成含有一或多個多閘極裝置(如一或多個全繞式閘極電晶體)的功能電路。在此例中，多層內連線可包含垂直內連線如通孔或接點，與水平內連線如金屬線路。多種內連線結構可採用多種導電材料如銅、鎢、及/或矽化物。在一例中，採用鑲嵌及/或雙鑲嵌製程以形成銅相關的多層內連線結構。此外，可在方法100之前、之中、與之後實施額外製程步驟，且方法100的多種實施例可調整、置換、或省略一些上述步驟。
如上所述，半導體層206之間的垂直距離(沿著Z方向)、半導體層206與介電鰭狀物208之間的水平距離(沿著Y方向)，與第一閘極間隔物210與第二閘極間隔物210之間的水平距離(沿著X方向)，對自對準的蝕刻製程224而言很重要。特定距離可用於完全移除金屬層222，而不過蝕刻多閘極裝置20的其他區域。上述的特定距離可用於蝕刻金屬層222而不需額外光微影步驟。上述製程的額外優點為減少設計佈局中的單元空間，因此可形成更多結構於相同空間中。
本發明實施例之例示性的半導體裝置的形成方法，包括：提供自基板延伸的鰭狀物，且鰭狀物包括多個半導體層。相鄰的半導體層之間具有第一距離。方法更包括提供自基板延伸並與半導體層相鄰的介電鰭狀物。每一半導體層的末端與介電鰭狀物的第一側壁之間具有第二距離。第二距離大於第一距離。在一些實施例中，第一距離沿著第一方向，第二距離沿著第二方向，且第一方向垂直於第二方向。方法更包括沉積介電層於半導體層與介電鰭狀物的第一側壁上。在一些實施例中，沉積介電層的步驟包括形成界面層於半導體層上，並沉積高介電常數的介電層於界面層上。一些實施例在沉積介電層之前，沉積第一閘極間隔物以與介電鰭狀物的第一側壁相鄰；以及在沉積介電層之前，沉積第二閘極間隔物以與介電鰭狀物的第二側壁相鄰，其中第二側壁與第一側壁相對。在這些實施例中，且其中第一閘極間隔物與第二閘極間隔物之間具有第三距離，第一距離沿著第一方向，第二距離沿著第二方向，第三距離沿著第三方向，第一方向垂直於第二方向，且第一方向與第二方向垂直於第三方向。方法更包括形成第一金屬層於半導體層與介電鰭狀物的第一側壁上的介電層上，其中位於相鄰的半導體層之上與之間的第一金屬層的部分合併在一起。在一些實施例中，位於每一半導體層的末端上的第一金屬層的一部分，與位於介電鰭狀物的第一側壁上的第一金屬層的一部分隔有第三距離，以形成溝槽於兩者之間。在一些實施例中，第三距離沿著第三方向，且第一方向與第二方向垂直於第三方向。一些實施例在形成第一金屬層之前，形成第二金屬層於介電層上。方法更包括移除第一金屬層。
另一例示性的半導體裝置的形成方法包括形成自基板延伸的第一半導體層堆疊，其中第一半導體層堆疊的相鄰半導體層之間具有第一距離。形成自基板延伸的介電鰭狀物，其中第一半導體層堆疊與介電鰭狀物的第一側壁相鄰，且第一半導體層堆疊的半導體層的末端與介電鰭狀物的第一側壁之間具有第二距離。在一些實施例中，第一距離延伸於第一方向中，第二距離延伸於第二方向中，且第一方向垂直於第二方向。方法更包括形成自基板延伸並與介電鰭狀物的第二側壁相鄰的第二半導體層堆疊，第二側壁與第一側壁相對，且第二半導體層堆疊的相鄰半導體層之間具有第一距離。方法更包括沉積金屬層於第一半導體層堆疊、第二半導體層堆疊、與介電鰭狀物上。在一些實施例中，沉積金屬層的步驟持續到金屬層合併於第一半導體層堆疊的第一半導體層與相鄰的第一半導體層堆疊的第二半導體層之間。在一些實施例中，金屬層為第一金屬層，並形成第二金屬層於第一金屬層上；沉積遮罩於第二金屬層上；蝕刻第一半導體層堆疊上的遮罩以露出第一半導體層堆疊上的第二金屬層；以及蝕刻第二金屬層以露出第一半導體層堆疊上的第一金屬層。在一些實施例中，方法更包括在沉積金屬層之前，形成閘極介電層於第一半導體層堆疊與第二半導體層堆疊上。在一些實施例中，形成閘極介電層的步驟包括：沉積界面層於第一半導體層堆疊與第二半導體層堆疊上；以及沉積高介電常數的介電層於界面層上。在一些實施例中，方法更包括：形成第一閘極間隔物以與介電鰭狀物的第三側壁相鄰；以及形成第二閘極間隔物以與介電鰭狀物的第四側壁相鄰，其中第四側壁與第三側壁相對，且第一閘極間隔物與第二閘極間隔物之間具有第三距離。
例示性的半導體裝置包括介電鰭狀物自基板延伸。第一通道層位於基板上並與介電鰭狀物的第一側壁相鄰。第二通道層位於第一通道層上，其中第一通道層與第二通道層之間具有第一距離。第三通道層位於基板上並與介電鰭狀物的第二側壁相鄰，其中介電鰭狀物的第二側壁與第三通道層的末端之間具有第二距離，且介電鰭狀物的第一側壁與第二側壁相對。在一些實施例中，第一距離沿著第一方向，第二距離沿著第二方向，且第一方向垂直於第二方向。在一些實施例中，第二距離大於第一距離。在一些實施例中，第一金屬層位於第一通道層、第二通道層、與第三通道層上，且第二金屬層位於第三通道層上。在一些實施例中，第一金屬層與第二金屬層不同。在一些實施例中，介電層位於第一通道層與第一金屬層之間。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本發明。本技術領域中具有通常知識者應理解可採用本發明作基礎，設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解，這些等效置換並未脫離本發明精神與範疇，並可在未脫離本發明之精神與範疇的前提下進行改變、替換、或更動。
A-A',B-B':平面 d1:第一距離 d2:第二距離 d3:第三距離 d4:第四距離 d5:第五距離 d6:第六距離 d7:第七距離 d8:第八距離 d10:第十距離 d11:第十一距離 V t1,V t2:區域 wd:寬度 20:多閘極裝置 100:方法 102,104,106,108,110:步驟 202:基板部分 204:鰭狀物 206:半導體層 208:介電鰭狀物 210:閘極間隔物 212:部分 218:界面層 220:高介電常數的介電層 222:金屬層 224:蝕刻製程
圖1係本發明多種實施例中，製作多閘極裝置的方法之流程圖。 圖2A係一些實施例中，多閘極裝置的簡化上視佈局圖。 圖2B、3A、4A、5A、6A、及7A係一實施例中，多閘極裝置200沿著圖2A的平面A-A'的剖視圖。 圖2C、3B、4B、5B、6B、及7B係一實施例中，多閘極裝置200沿著圖2A的平面B-B'的剖視圖。
100:方法
102,104,106,108,110:步驟

Claims (1)

  1. 一種半導體裝置的形成方法，包括： 提供自一基板延伸的一鰭狀物，且該鰭狀物包括多個半導體層，其中相鄰的該些半導體層之間具有一第一距離； 提供自該基板延伸並與該些半導體層相鄰的一介電鰭狀物，其中每一該些半導體層的末端與該介電鰭狀物的一第一側壁之間具有一第二距離，且該第二距離大於該第一距離； 沉積一介電層於該些半導體層與該介電鰭狀物的該第一側壁上； 形成一第一金屬層於該些半導體層與該介電鰭狀物的該第一側壁上的該介電層上，其中位於相鄰的該些半導體層之上與之間的該第一金屬層的部分合併在一起；以及 移除該第一金屬層。
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