CN114556546A - 通过选择性外延再生长的环绕式栅极输入/输出的形成方法 - Google Patents

通过选择性外延再生长的环绕式栅极输入/输出的形成方法 Download PDF

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CN114556546A
CN114556546A CN202080071944.1A CN202080071944A CN114556546A CN 114556546 A CN114556546 A CN 114556546A CN 202080071944 A CN202080071944 A CN 202080071944A CN 114556546 A CN114556546 A CN 114556546A
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semiconductor device
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本杰明·科伦坡
马蒂亚斯·鲍尔
纳韦德·艾哈迈德·西迪基
菲利普·斯托特
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Applied Materials Inc
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Applied Materials Inc
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Abstract

描述了具有环绕式栅极非I/O装置和I/O装置的鳍状结构的电子装置和形成方法。蚀刻多个虚拟栅极，以暴露出包括第一材料和第二材料交替层的鳍片。第二材料层被移除以产生开口，而剩下的第一材料层经外延生长以形成鳍状结构。

Description

通过选择性外延再生长的环绕式栅极输入/输出的形成方法
技术领域
本公开内容的实施方式大体涉及半导体装置，更特定言之涉及水平环绕式栅极装置结构和形成水平环绕式栅极装置结构的方法和设备。
背景技术
晶体管是大多数集成电路的关键部件。由于晶体管的驱动电流以及因此速度与晶体管的栅极宽度成正比，因此较快的晶体管通常需要较大的栅极宽度。因此，晶体管的大小和速度之间存在有妥协，且已经开发出“鳍式”场效应晶体管(finFET)来解决晶体管具有最大驱动电流和最小尺寸的矛盾目标。finFET的特点是在不显著增加晶体管的占地面积的情况下，通过鳍片形沟道区域大大增加了晶体管的尺寸，目前已在许多集成电路中得到应用。然而，finFET也有其自身的缺点。
由于晶体管装置的特征尺寸不断缩小，以达到更大的电路密度和更高的性能，因此需要改善晶体管装置的结构，以改善静电耦合，减少寄生电容和截止状态漏电等负面效应。晶体管装置结构的实例包括平坦结构、鳍式场效应晶体管(finFET)结构和水平环绕式栅极(hGAA)结构。hGAA装置结构包括多个以堆叠方式悬浮的晶格匹配沟道，并由源/漏区连接。相信hGAA结构能提供良好的静电控制，并能在互补金属氧化物半导体(CMOS)晶片制造中得到广泛的应用。
逻辑栅极性能与所使用的材料特性以及结构层的厚度和面积有关。然而，当一些栅极特性被调整以适应装置缩放时，就会出现挑战。此外，水平环绕式栅极(hGAA)装置的支柱之间的空间限制了I/O晶体管的栅极介电材料的厚度。
在hGAA结构的工艺流程的自然过程中，I/O装置需要较高的驱动电流，已经发现到若像常规工艺流程那样有一个Si/SiGe的序列，将对I/O性能不利，特别是在NMOS装置的情况下。GAA结构对于I/O装置也是不合适的。因此，需要改进形成水平环绕式栅极装置的方法，使其能够形成类似鳍片的结构。
发明内容
本公开内容的一个或多个实施方式是针对形成半导体装置的方法。从基板表面蚀刻在多个鳍片上的多个虚拟栅极。多个鳍片沿第一方向延伸，而虚拟栅极沿与第一方向交叉的第二方向延伸。蚀刻多个虚拟栅极使多个鳍片的部分暴露出来，使基板表面上的鳍片的数个部分被虚拟栅极覆盖，且鳍片的数个部分暴露出来。鳍片包括第一材料和第二材料的交替层。穿过蚀刻虚拟栅极所形成的沟槽移除栅极氧化物。穿过沟槽从多个鳍片上蚀刻第二材料层，从而有交替的第一材料层和开口。第一材料外延生长穿过沟槽以合并第一材料层成第一材料的接点。
公开内容的额外实施方式是针对包括非I/O栅极区域、I/O栅极区域、源-漏极非I/O区域、pFET区域和nFET区域的半导体装置。
本公开内容的进一步实施方式是针对包含具有环绕式栅极结构的非I/O栅极区域和非I/O栅极接点的半导体装置。环绕式栅极结构包括多个间隔的纳米片。装置包括I/O栅极区域，I/O栅极区域包含finFET和I/O接点；源-漏极非I/O区域，源-漏极非I/O区域包含源极接点和漏极接点；以及pFET区域，pFET区域包含外延生长的第一材料和pFET接点。外延生长的第一材料具有长度、宽度和高度。宽度具有与间隔的纳米片对齐的多个间隔突起。装置进一步包括nFET区域，nFET区域包含外延生长的第二材料和nFET接点。
附图说明
为了能够详细理解上述本公开内容的特征，可以通过参考实施方式对上方简述的公开内容有更特定的描述，其中一些实施方式在附图中示出。然而，要注意的是，附图仅图示了本公开内容的典型实施方式，因此不应认为是对其范围的限制，因为本公开内容可接纳其他等效实施方式。
图1至图11F展示了根据本公开内容的一个或多个实施方式的电子装置的制造阶段；
图12A至图12F展示了根据公开内容的一个或多个实施方式的电子装置；和
图13展示了图12E中所示的区域XII的扩展视图。
为了便于理解，在可能的情况下，使用了相同的附图标记来表示各图共有的相同元件。图没有按比例绘制，且为清楚起见可加以简化。一个实施方式的元件和特征可有利地并入其他实施方式中，无需进一步复述。
具体实施方式
在描述本公开内容的几个示例性实施方式之前，要理解的是，本公开内容并不局限于以下描述中列出的构造或工艺步骤的细节。本公开内容能够以各种方式实施或进行其他实施方式。
如在本说明书和所附权利要求中所使用的，术语“基板”指的是上方有一个工艺作用的一个表面，或一个表面的一部分。本技术领域的技术人员还将理解，除非上下文明确指出，否则提及基板也可以仅指基板的一部分。此外，提及沉积在基板上时，既可指裸基板，也可指在其上沉积或形成一个或多个膜或特征的基板。
本文使用的“基板”是指在制造工艺中于上方进行膜处理任何基板或基板上形成的材料表面。例如，可在其上进行处理的基板表面包括的材料诸如硅、氧化硅、应变硅、绝缘体上硅(SOI)、掺杂碳的氧化硅、非晶硅、掺杂的硅、锗、砷化镓、玻璃、蓝宝石以及任何其它材料(如金属、金属氮化物、金属合金和其它导电材料)，这取决于应用。基板包括但不限于半导体晶片。基板可以暴露于预处理过程中，以进行抛光、蚀刻、还原、氧化、羟基化、退火和/或烘烤基板表面。除了直接在基板本身的表面上进行膜处理外，在本公开内容中，所公开的任何膜处理步骤也可在形成于基板上的底层上进行，如下文所详细公开的那样，而术语“基板表面”意在包括上下文所示的这种底层。因此，例如，当膜/层或部分膜/层已沉积到基板表面上时，新沉积的膜/层的暴露表面成为基板表面。
在本说明书和所附权利要求中，术语“前驱物”、“反应物”、“反应性气体”等可互换使用，指任何能与基板表面反应的气体物种。
如本文所使用的，术语“环绕式栅极(GAA)”用于指栅极材料在所有侧面环绕沟道区域的电子装置(例如，晶体管)。GAA晶体管的沟道区域可包括纳米线或纳米板、条形沟道或本领域技术人员已知的其它合适沟道配置。在一个或多个实施方式中，GAA装置的沟道区域具有多个垂直间隔的水平纳米线或水平条，使得GAA晶体管成为堆叠式水平环绕式栅极(hGAA)晶体管。
本公开内容的一个或多个实施方式针对用于形成逻辑中的I/O装置的传统鳍片状结构的方法。一些实施方式有利地保持非I/O装置作为后finFET技术的纳米片/纳米板。本公开内容的一些实施方式有利地提供了传统hGAA工艺流程的额外工艺，在栅极氧化物层被蚀刻后，SiGe板被移除用于GAA功函数金属沉积。在一些实施方式中，SiGe去除之后是ODL(或SOH)沉积，之后非I/O区域被掩盖掉。在暴露的I/O区域中，ODL被剥离，并在纳米板之间和纳米板上使用外延重新生长硅，直到它们被夹掉。一旦硅被充分生长，回蚀工艺(例如，使用HCl)被执行，以凹陷纳米板的侧壁，并使侧壁垂直，导致I/O装置中结晶硅制成的类似于鳍片的结构。在一些实施方式中，将硬掩模和ODL从非I/O装置上去除，在非I/O侧和I/O装置上重新生长的鳍片的外表面沉积功函数金属作为GAA。
参照附图描述了公开内容的一个或多个实施方式。图1图示了根据公开内容的一个或多个实施方式的电子装置100。电子装置100包括基板表面102上的多个鳍片110。图中的每个图示出了具有由沟槽111分隔的三个鳍片110的实施方式；然而，本领域技术人员将认识到，可以有多于或少于三个的鳍片110。鳍片110具有沿第一方向191(也称为X方向)延伸的长度、沿第二方向192(也称为Y方向)延伸的宽度以及沿第三方向193(也称为Z方向)延伸的高度。使用术语“水平”是指由第一方向191和第二方向192形成的平面(也称为X-Y平面)。使用术语“垂直”是指沿第三方向193。术语“水平”和“垂直”用于说明相对的方向性，而不应被解释为相对于引力的任何特定关系。在一些实施方式中，鳍片110的数量是三的倍数。
鳍片110包括第一材料112和第二材料114的交替层。一些实施方式的第一材料112和第二材料114是不同的材料。在一些实施方式中，第一材料112包括至少一种III-V材料，且第二材料114包括至少一种III-V材料，因此第一材料112和第二材料114包括不同的材料。在一些实施方式中，第一材料112包括硅(Si)。在一些实施方式中，第二材料114包括硅锗(SiGe)。第一材料112和第二材料114可以是任何合适的厚度，并且可以由本领域技术人员已知的任何合适的技术来沉积。第一材料112和第二材料114的层也被称为纳米片。
鳍片110是在由包括多种材料的基板101上形成的。本领域技术人员将认识到，这里所述的材料仅仅是可能的材料的代表，而不应限于这些材料。在图示的实施方式中，在p型掺杂硅117上形成两个鳍片110，且在n型掺杂硅118上形成一个鳍片110。在p型掺杂硅117和n型掺杂硅118之间是一个浅沟槽隔离(STI)氧化物119。
栅极氧化物120形成在基板101的表面102上，覆盖多个鳍片110。栅极氧化物120可以是由本领域技术人员已知的任何合适的技术沉积的任何合适材料。在一些实施方式中，通过原子层沉积(ALD)工艺沉积栅极氧化物120为保形层。在一些实施方式中，栅极氧化物120是热生长的氧化物。在一个或多个实施方式中，栅极氧化物包括氧化硅。
图2展示了图1的实施方式在多个虚拟栅极200的图样化及移除外露的栅极氧化物120后的情况。虚拟栅极200沿第二方向192延伸，以一定角度与第一方向191交叉。一些实施方式的角度，是在30°至150°的范围内，或在45°至135°的范围内，或在60°至120°的范围内，或在75°至105°的范围内，或在80°至100°的范围内。在一些实施方式中，第一方向191和第二方向192的交点形成的角度为90°。多个虚拟栅极200形成在多个鳍片110上，使得鳍片110的部分210被虚拟栅极200覆盖，而鳍片110的部分220暴露在虚拟栅极200之间的间隙215中。一些实施方式的虚拟栅极200通过任何合适的技术沉积，掩盖以进行图案化和蚀刻。在一些实施方式中，蚀刻虚拟栅极200形成沟槽215，暴露出具有栅极氧化物120的鳍片110的部分220。在图示的实施方式中，虚拟栅极200示出了顶部具有硬掩模204的虚拟栅极材料202。虚拟栅极材料202可以是本领域技术人员已知的任何合适材料。在一些实施方式中，虚拟栅极材料202包括非晶硅。硬掩模204可以是通过任何合适的技术沉积并通过任何合适的技术(例如，光刻)图案化的任何合适材料。在一些实施方式中，硬掩模包括氮化硅。
在一些实施方式中，如图2所示，从暴露在沟槽215中的鳍片110的顶部蚀刻栅极氧化物120。栅极氧化物120可以由本领域技术人员已知的任何合适技术进行蚀刻。在一些实施方式中，使用各向异性蚀刻工艺蚀刻栅极氧化物120。在一些实施方式中，使用反应性离子蚀刻(RIE)工艺蚀刻栅极氧化物120。
图3图示与图2相似的实施方式，在蚀刻不在虚拟栅极200之下的第一材料112及第二材料114之后且形成内间隔物116。暴露的第一材料112和第二材料114(板块或纳米片中不在虚拟栅极下面的部分)由本领域技术人员已知的任何合适的技术进行蚀刻。在一些实施方式中，通过各向异性蚀刻工艺蚀刻第一材料112和第二材料114。在一些实施方式中，第一材料112和第二材料114与栅极氧化物120同时蚀刻。在一些实施方式中，第一材料112和第二材料114与栅极氧化物120分开蚀刻。
穿过沟槽将第二材料114凹入虚拟栅极200下的凹槽距离215。凹槽距离可以是任何合适的距离。在一些实施方式中，凹槽距离在1至10nm的范围内，或在2至8nm的范围内，或在3至7nm的范围内，或在4至5nm的范围内。可以由本领域技术人员已知的任何合适技术来使第二材料114凹入。
在一些实施方式中，通过原子层沉积将内间隔物116沉积为覆盖凹陷的第二材料114、第一材料112和虚拟栅极200和STI氧化物119的暴露部分的保形膜。在保形沉积之后，使用各向异性蚀刻工艺(例如，RIE)从虚拟栅极200的顶部、底部和侧壁清理内间隔物116，将内间隔物116留在凹陷第二材料114所留下的凹陷区域内。在一些实施方式中，内间隔物116从顶部和底部表面移除，并作为侧壁间隔物302留在虚拟栅极的侧壁上(如图4所示)。侧壁间隔物302可由与内间隔物116相同的材料或不同的材料302分别形成。
图4图示了与图3相似的实施方式，在沉积、遮蔽和图案化侧壁间隔物302和硬掩模300之后。图案化后，穿过硬掩模300暴露的第二材料114经外延生长以形成源-漏极非I/O区域的pFET。硬掩模300形成在基板上，并经图案化以在电子装置的源-漏极非I/O区域上产生开口301。穿过一些实施方式的开口可以接触到的鳍片110在虚拟栅极200之间被蚀刻，以从鳍片110上去除第一材料112。在蚀刻之后，第二材料114被外延生长以形成源-漏极非I/O区域310的pFET320。
图标的实施方式显示了在nFET之前形成pFET的工艺。然而，本领域技术人员将认识到nFET可以在pFET之前形成，并将理解附图的重新排列以适应这样的实施方式。
在一些实施方式中，侧壁间隔物302作为保形膜与内间隔物116分开沉积，并从水平表面蚀刻掉，使得虚拟栅极200的侧壁覆盖有侧壁间隔物302。在一些实施方式中，侧壁间隔物302防止了硬掩模300和虚拟栅极材料202之间的直接接触。可以由本领域技术人员已知的任何合适技术沉积和/或蚀刻侧壁间隔物302。侧壁间隔物302可以是本领域技术人员已知的任何合适材料。在一些实施方式中，侧壁间隔物302包括低k电介质。硬掩模300可以是由本领域技术人员已知的任何合适技术沉积的任何合适硬掩模。
图5图示了在移除硬掩模300、形成新的硬掩模400、掩蔽和图案化硬掩模400之后的图4的实施方式；接着是在nFET区域410中外延生长nFET 420。可以由本领域技术人员已知的任何合适技术去除硬掩模300。在一些实施方式中，通过蚀刻工艺去除硬掩模300。由本领域技术人员已知的任何合适技术形成和图案化第二硬掩模400，以在nFET区域410上产生开口401。在一些实施方式中，nFET是在pFET形成之前形成的。本领域技术人员将认识并理解如何形成nFET，然后形成pFET，而不需要进行不适当的实验。
图6图示在形成可选的栅极切割支柱502(在图6中可见)之后的图5的实施方式。由本领域技术人员已知的任何合适技术去除硬掩模204和硬掩模400。沉积氧化物层500以填充虚拟栅极200之间的空间。由本领域技术人员已知的任何合适技术沉积氧化物层500，包括但不限于可流动化学气相沉积(FCVD)。在一些实施方式中，氧化物层500是通过覆盖沉积(blanket deposition)工艺沉积的氧化硅，然后通过合适的平坦化工艺(例如，化学机械平坦化)以穿过氧化物层500暴露虚拟栅极200的顶部208。
在一些实施方式中，在氧化物层500沉积之前，在去除硬掩模204和硬掩模400之后，在暴露的表面上沉积衬垫510。衬垫510也被称为接触蚀刻终止层(CESL)。一些实施方式的衬垫510包括氮化硅。一些实施方式的衬垫510通过原子层沉积沉积为保形层。在一些实施方式中，形成栅极切割支柱502包括沉积和图案化硬掩模520以形成开口525以暴露非晶硅层500的顶部501和侧壁间隔物302的顶部303以及衬垫510的顶部512。栅极切割支柱502可以是任何合适的材料，包括但不限于氮化物。在一些实施方式中，省略了栅极切割支柱502的形成，因此电子装置中没有栅极切割支柱。图7图示了在执行了几个工艺以去除虚拟栅极材料202(例如，非晶硅栅极)之后的图6的实施方式。在形成栅极切割支柱502的实施方式中，硬掩模520被移除以暴露侧壁间隔物302的顶部303、衬垫510的顶部512和氧化物层500的顶部501。
去除虚拟栅极200(可选择性地包括虚拟栅极材料202)，结果形成沟槽600。可以由本领域技术人员已知的任何合适技术去除虚拟栅极200和虚拟栅极材料202。在一些实施方式中，通过反应性离子蚀刻(RIE)去除氧化层500。可以由本领域技术人员已知的任何合适技术去除虚拟栅极材料202。在一些实施方式中，通过在对氧化物层500和虚拟栅极材料202有选择性的工艺中去除硬掩模204来去除虚拟栅极200，然后在对氧化物层500有选择性的工艺中去除虚拟栅极材料202。在一些实施方式中，去除虚拟栅极材料202可去除少于50％的氧化物层500。
穿过沟槽600移除第二材料114层(纳米片)。如图所示，这些层被遮蔽以打开I/O区域，同时保护非I/O区域以允许制备I/O区域。穿过沟槽600自多个鳍片110蚀刻第二材料114的层，形成交替的第一材料112层和沿第一方向191两侧由内间隔物116限定的开口610。可以由本领域技术人员已知的任何合适技术去除第二材料114。在一些实施方式中，第二材料114相对于第一材料112被选择性地蚀刻。去除第二材料114可允许填充纳米片之间的间隙。在一些实施方式中，去除第二材料114可允许形成纯硅装置。在一些实施方式中，第一材料包括结晶硅(Si)而第二材料包括硅锗(SiGe)，并且使用对结晶硅具选择性的蚀刻工艺来去除SiGe。
图7至图11中的每幅图均按照六视图的类似图案说明电子装置。每个图的“A”视图呈现了根据本公开内容的一个或多个实施方式的电子装置的等角视图。“B”至“F”视图说明了在“A”视图中所示的电子装置沿图7A中所示的线取得的切片。在每个图中，“B”视图图示了“A”视图的电子装置的切片，其中图标了非I/O栅极。在每个图中，“C”视图图示了“A”视图的电子装置的一个切片，其中图示了I/O栅极。在每个图中，“D”视图图示了“A”视图的电子装置的切片，其中图标了源-漏极非I/O。在每个图中，“E”视图图示了“A”视图的电子装置的切片，其中图标了pFET。在每个图中，“F”视图图示了“A”视图中电子装置的切片，其中图标了nFET。为了便于查看，代表“B”至“F”切片的线仅图示在图7A上，但本领域技术人员将在图8至图11中的每个图中识别这些视图。提到图号时，若没有下面的字母，则指的是所指示的图的所有六个视图。例如，对图7的提述是指图7A至图7F的全部。
图8A图示在自旋硬掩模(SOH)700和硬掩模层710沉积后的图7的实施方式。SOH700可以是通过任何合适的技术沉积的任何合适的硬掩模。在一些实施方式中，SOH 700包括或基本上由旋涂碳(SOC)组成。硬掩模层710可以是任何合适的材料，包括但不限于氧氮化硅(SiON)，并由本领域技术人员已知的任何合适技术沉积。
形成穿过硬掩模层710和SOH 700的开口720。开口暴露了电子装置的I/O区域，同时保护了晶体管栅极。可以由本领域技术人员已知的任何合适技术形成开口720。在一些实施方式中，额外的硬掩模被沉积在抗蚀剂的顶部并经图案化。以在额外的硬掩模中形成开口。然后将开口转移到硬掩模层710和SOH700中。在一些实施方式中，通过穿过额外的硬掩模中的开口掩蔽和蚀刻硬掩模层710和SOH 700而形成开口720。在一些实施方式中，硬掩模层710和SOH700同时被蚀刻。在一些实施方式中，硬掩模层710和SOH 700采用不同的工艺进行蚀刻。如图8E和图8F所示，一些实施方式的开口720分别形成在电子装置的pFET和nFET区域上。
图9图示了在移除硬掩模层710并穿过开口600在第一材料112上进行外延再生长工艺后的图8的实施方式。一些实施方式的外延再生长工艺是选择性外延工艺。在一些实施方式中，选择性外延工艺穿过开口600(也称为沟槽)外延生长第一材料112层。一些实施方式的外延生长导致第一材料112层合并成第一材料112的接点800。在一些实施方式中，第一材料112包括硅，而外延导致第一材料112的纳米片合并并夹断开口610。在一些实施方式中，外延工艺导致Si<100>的生长。在一些实施方式中，外延工艺导致Si<110>的生长。在一些实施方式中，外延工艺导致接点800具有圆锥状(如图9C所示)平顶或截头圆锥状(frustoconical)(如图9E所示)。
图10图示了在经过蚀刻工艺修整鳍片(接点800)并穿过沟槽910剥离硬掩模层710后的图9的实施方式。在一些实施方式中，在经由循环式外延生长-蚀刻工艺来塑造I/O装置之后发生蚀刻工艺。在一些实施方式中，蚀刻工艺包括HCl回蚀工艺。在一些实施方式中，回蚀工艺增加侧壁的垂直度。在一些实施方式中，回蚀工艺重塑纳米片以降低在接点800顶部形成的点的严重性，以形成I/O装置由结晶硅制成的鳍状结构(finFET)。在一些实施方式中，通过重复的顺序生长和蚀刻工艺重塑接点800，然后移除SOH 700以产生开口910。
图11图示了在经过几个工艺后的图10的实施方式。层间电介质1300形成在暴露的表面上。一些实施方式的层间电介质1300是由原子层沉积的保形膜。层间电介质1300可以是本领域技术人员已知的任何合适材料。
在形成层间电介质1300之后，在层间电介质1300上形成高k电介质1310。高k电介质1310可以是本领域技术人员已知的任何合适材料。在一些实施方式中，高k电介质1310包括或基本上由铪氧化物组成。在一些实施方式中，高k电介质是由原子层沉积的保形膜。
可选的功函数金属(WFM)1320形成在高k电介质1310上。可选的功函数金属1320可以是通过任何合适技术沉积的本领域技术人员已知的任何合适材料。在一些实施方式中，功函数金属1320是由原子层沉积或物理气相沉积沉积的保形膜。
栅极金属1330形成在可选的功函数金属1320上。栅极金属可以是通过任何合适的技术沉积的任何合适材料。在一些实施方式中，栅极金属1330包括钴、钨、铜、钼或钌中的一种或多种。在一些实施方式中，通过覆盖沉积工艺沉积栅极金属1330。在一些实施方式中，通过原子层沉积、化学气相沉积或物理气相沉积中的一种或多种来沉积栅极金属1330。
栅极金属1330形成后，电子装置被平坦化以降低栅极金属1330的表面1332，以暴露非晶硅层500的顶面501。在一些实施方式中，通过蚀刻或化学机械平坦化(CMP)进行平坦化。
图12图示了形成各种接点后的图11的实施方式。本领域技术人员将理解图案化和形成各种接点的工艺。简而言之，在一些实施方式中，通过任何合适的技术形成和图案化硬掩模层和抗蚀剂。
穿过图案化的掩模开口的蚀刻为接点开孔。在一些实施方式中，蚀刻工艺包括各向异性蚀刻工艺。在一些实施方式中，蚀刻工艺产生开孔并对pFET和nFET具有选择性。
层间电介质1300被移除，而金属层则被沉积及平坦化。可以由本领域技术人员已知的任何合适技术去除层间电介质1300。在一些实施方式中，金属层1700包括与栅极金属1330相同的材料。在一些实施方式中，金属层1700包括钴、钨、铜或钌中的一种或多种。沉积金属层1700后，将电子装置进行平坦化，以降低金属层1700的表面1702，以露出非晶硅层500的顶面501。在一些实施方式中，通过蚀刻或化学机械平坦化(CMP)进行平坦化。
如图12A至图12F所示，本公开内容的一些实施方式是针对包含非I/O栅极区1110(图12B)、I/O栅极区1120(图12C)、源-漏极非I/O区1130(图12D)、pFET区1140(图12E)及nFET区(图12F)的半导体装置1100。
电子装置1100的一些实施方式具有带有环绕式栅极结构1112的非I/O栅极区域1110。在一些实施方式中，环绕式栅极结构1112具有由第一材料112制成的纳米片1111芯，且具有层间电介质1300与第一材料112接触。在一些实施方式中，高k电介质1310在与第一材料112相反的一侧与层间电介质1300接触。在一些实施方式中，功函数金属1320在与层间电介质1310相反的一侧接触高k电介质1310。
在一些实施方式中，由第一材料112制成的每个纳米片1111都沿第三方向193与p型掺杂硅117间隔一定的距离。例如，图12B图示了图中右侧的两列纳米片1111，每列与p型掺杂硅117材料间隔一定距离。在一些实施方式中，由第一材料112制成的每个纳米片1111沿第三方向193与n型掺杂硅118间隔一定距离。例如，图12B图示了图中左侧的一列纳米片1111；该列与n型掺杂硅118材料间隔一定距离。在一些实施方式中，每个纳米片1111沿第三方向193与相邻的纳米片1111间隔一定的距离，从而使每个环绕式栅极结构1112之间有栅极金属1330的区域。
纳米片1111和/或环绕式栅极结构1112的数量可具有变化。在一些实施方式中，有2至7个纳米片1111，或2至5个纳米片，或3至4个纳米片，或3个纳米片的范围。
一些实施方式进一步包括在非I/O栅极区域1110(图12B)或I/O栅极区域1120(图12C)中的一个或多个中的可选栅极切割支柱502。
在一些实施方式中，如图12C所示，电子装置1100包括带有finFET 1122的I/O栅极区域1120。一些实施方式的finFET 1122包括由第一材料112制成的接点800。在一些实施方式中，I/O栅极区域1120的finFET 1122具有一个截头圆锥状顶部部分。
在一些实施方式中，pFET区域1140(图12E)或nFET区域1150(图12F)中的一个或多个包含作为pFET 320和/或nFET 420的外延生长的第一材料112。在图标的实施方式中，pFET区域1140(图12E)具有外延生长的第二材料114作为pFET320，而nFET区域1150(图12F)具有外延生长的第一材料112作为nFET 420。
参考图12E和图13，形成pFET 320的外延生长的第一材料112具有沿第二方向192延伸的长度。图12E和图13图示了在第一方向191和第三方向193形成的平面(X-Z平面)上沿第二方向192观察的电子装置。外延生长的第一材料112具有沿第一方向191延伸的宽度W和沿第三方向193延伸的高度H。形成接点800的外延生长的第一材料112的宽度W沿高度H变化。在一些实施方式中，外延生长的第一材料112的宽度具有多个间隔突起。
权利要求14的半导体装置，其中外延生长的第一材料具有长度、宽度和高度，而宽度具有多个间隔突起115。每个突起115与相邻的突起115之间由内间隔物116(也称为内间隔物电介质)隔开。在一些实施方式中，每个间隔突起与图12E右侧所示的晶体管的环绕式栅极结构1112的纳米片1111对齐。在一些实施方式中，内间隔物具有1至10nm的宽度，或2至8nm的宽度，或3至7nm的宽度，或4至5nm的宽度。
一些实施方式进一步包括与非I/O栅极区域1110电连通的非I/O栅极接点1115、与I/O栅极区域1120电连通的I/O栅极接点1125、与源-漏极非I/O区域1130的源极(pFET 320或nFET 420之一)电连通的源极接点1135、与源-漏极非I/O区域1130的漏极(pFET 320或nFET 420之一)电连通的漏极接点1135、与pFET区域1140电连通的pFET接点1145和与nFET区域1150电连通的nFET接点1155中的一个或多个。在一些实施方式中，I/O装置(图11E和图11F的左侧所示)的宽度比晶体管栅极(图11E和图11F的右侧所示)的宽度宽。I/O装置的宽栅极允许应用更高的电压和/或更大的电流。在一些实施方式中，I/O栅极的宽度大于非I/O栅极的1.5倍、2倍、4倍、7倍或10倍。
本说明书通篇提及“一个实施方式”、“某些实施方式”、“一个或多个实施方式”或“一实施方式”意味着与实施方式相关的所述特定特征、结构、材料或特性包含在公开内容的至少一个实施方式中。因此，在本说明书中的不同地方出现的诸如“在一个或多个实施方式中”、“在某些实施方式中”、“在一个实施方式中”或“在一实施方式中”的短语不一定是指公开内容的同一个实施方式。此外，特定的特征、结构、材料或特性可在一个或多个实施方式中以任何合适的方式组合。
尽管本文的公开内容已经参照特定的实施方式进行了描述，但本领域的技术人员将理解，所描述的实施方式仅仅是对本公开内容的原理和应用的说明。对于本领域的技术人员来说很明显可在不偏离本公开内容的精神和范围的情况下，对本公开内容的方法和设备进行各种修改和变化。因此，本公开内容可以包括在所附权利要求及其等效范围内的修改和变化。

Claims (20)

1.一种形成半导体装置的方法，包括以下步骤：
从基板表面蚀刻多个鳍片上方的多个虚拟栅极以提供沿第二方向延伸的多个沟槽，所述多个鳍片沿第一方向延伸且所述第二方向与所述第一方向交叉，以暴露所述多个鳍片的数个部分，使所述基板表面上的所述鳍片的数个部分被所述虚拟栅极覆盖，而所述鳍片的数个部分暴露出来，所述鳍片包括第一材料和第二材料的交替层；
移除穿过所述沟槽暴露的栅极氧化物；
穿过所述沟槽自所述多个鳍片上蚀刻所述第二材料层，使得所述第一材料层和开口交替出现；和
外延生长所述第一材料层穿过所述沟槽，以将所述第一材料层合并成第一材料接点。
2.如权利要求1所述的方法，进一步包括以下步骤：图案化基板表面上的多个鳍片。
3.如权利要求1所述的方法，进一步包括以下步骤：在所述基板表面上形成栅极氧化物覆盖所述多个鳍片，通过蚀刻所述虚拟栅极而形成的所述沟槽暴露上方具有所述栅极氧化物的所述鳍片的数个部分。
4.如权利要求1所述的方法，进一步包括以下步骤：在所述多个鳍片上形成沿所述第二方向延伸的所述多个虚拟栅极，使得所述鳍片的数个部分被所述虚拟栅极覆盖，而所述鳍片的数个部分暴露出来。
5.如权利要求4所述的方法，进一步包括以下步骤：蚀刻所述鳍片暴露在所述虚拟栅极之间的数个部分。
6.如权利要求5所述的方法，进一步包括以下步骤：在所述虚拟栅极与所述虚拟栅极之间的暴露基板表面上沉积氧化物层。
7.如权利要求6所述的方法，进一步包括以下步骤：在所述基板上沉积非晶硅层，所述非晶硅层允许所述虚拟栅极的顶部被暴露出来。
8.如权利要求7所述的方法，其中形成所述非晶硅层的步骤包括覆盖沉积工艺，接着为化学-机械平坦化以暴露所述虚拟栅极的所述顶部。
9.如权利要求1所述的方法，其中所述第一材料包括至少一种III-V族材料而所述第二材料包括至少一种III-V族材料，所述第一材料与所述第二材料包括不同的材料。
10.如权利要求9所述的方法，其中所述第一材料包括硅(Si)而所述第二材料包括硅锗(SiGe)。
11.一种半导体装置，包括非I/O栅极区、I/O栅极区、源-漏极非I/O区、pFET区与nFET区。
12.如权利要求11所述的半导体装置，其中所述非I/O栅极区包括环绕式栅极结构。
13.如权利要求12所述的半导体装置，其中所述I/O栅极区包括finFET。
14.如权利要求13所述的半导体装置，其中所述pFET区或所述nFET区中的一个或多个包括外延生长第一材料。
15.如权利要求14所述的半导体装置，其中所述外延生长第一材料具有长度、宽度与高度，所述宽度具有多个间隔突起。
16.如权利要求15所述的半导体装置，其中所述间隔突起对齐于所述环绕式栅极结构的纳米片。
17.如权利要求16所述的半导体装置，其中有2至7个范围内的纳米片。
18.如权利要求17所述的半导体装置，进一步包括所述非I/O栅极区或所述I/O栅极区中的一个多个中的栅极切割支柱。
19.如权利要求11所述的半导体装置，进一步包括与所述非I/O栅极区电连通的非I/O栅极接点、与所述I/O栅极区电连通的I/O栅极接点、与所述源-漏极非I/O区的源极电连通的源极接点、与所述源-漏极非I/O区的漏极电连通的漏极接点、与所述pFET区电连通的pFET接点、及与所述nFET区电连通的nFET接点。
20.一种半导体装置，包括：
非I/O栅极区，具有环绕式栅极结构与非I/O栅极接点，所述环绕式栅极结构包括多个间隔纳米片；
I/O栅极区，包括finFET与I/O接点；
源-漏极非I/O区，包括源极接点与漏极接点；
pFET区，包括外延生长第一材料与pFET接点，所述外延生长第一材料具有长度、宽度与高度，所述宽度具有多个间隔突起，所述突起对齐于所述间隔纳米片；和
nFET区，包括外延生长第二材料与nFET接点。
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