FR3043837B1 - Procede de realisation de transistor a nanofil semi-conducteur et comprenant une grille et des espaceurs auto-alignes - Google Patents

Procede de realisation de transistor a nanofil semi-conducteur et comprenant une grille et des espaceurs auto-alignes

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Publication number
FR3043837B1
FR3043837B1 FR1561044A FR1561044A FR3043837B1 FR 3043837 B1 FR3043837 B1 FR 3043837B1 FR 1561044 A FR1561044 A FR 1561044A FR 1561044 A FR1561044 A FR 1561044A FR 3043837 B1 FR3043837 B1 FR 3043837B1
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France
Prior art keywords
producing
parts
dielectric layer
semiconductor
transistor
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Active
Application number
FR1561044A
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English (en)
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FR3043837A1 (fr
Inventor
Sylvain Barraud
Emmanuel Augendre
Sylvain Maitrejean
Nicolas Posseme
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Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Priority to FR1561044A priority Critical patent/FR3043837B1/fr
Priority to US15/352,198 priority patent/US9853124B2/en
Publication of FR3043837A1 publication Critical patent/FR3043837A1/fr
Application granted granted Critical
Publication of FR3043837B1 publication Critical patent/FR3043837B1/fr
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    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
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    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
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  • Chemical Kinetics & Catalysis (AREA)
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  • Inorganic Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Nanotechnology (AREA)
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Abstract

Procédé de réalisation d'un transistor (100) à nanofil semi-conducteur, comportant les étapes : - réaliser, sur un support (102), un nanofil semi-conducteur dont une portion (123) est recouverte d'une grille sacrificielle entourée, avec le nanofil, d'une couche diélectrique, - retirer la grille sacrificielle, formant un premier espace entouré de premières parties de la couche diélectrique, - implanter ioniquement une deuxième partie de la couche diélectrique sous ladite première portion, lesdites premières parties protégeant des troisièmes parties (136) de la couche diélectrique, - graver ladite deuxième partie, formant un deuxième espace, - réaliser une grille (140, 142) dans les espaces, et une portion diélectrique (148) sur la grille et lesdites premières parties, - implanter ioniquement des quatrièmes parties de la couche diélectrique entourant des deuxièmes portions du nanofil, la portion diélectrique protégeant lesdites premières et troisièmes parties, - graver lesdites quatrièmes parties.
FR1561044A 2015-11-17 2015-11-17 Procede de realisation de transistor a nanofil semi-conducteur et comprenant une grille et des espaceurs auto-alignes Active FR3043837B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR1561044A FR3043837B1 (fr) 2015-11-17 2015-11-17 Procede de realisation de transistor a nanofil semi-conducteur et comprenant une grille et des espaceurs auto-alignes
US15/352,198 US9853124B2 (en) 2015-11-17 2016-11-15 Method for fabricating a nanowire semiconductor transistor having an auto-aligned gate and spacers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1561044A FR3043837B1 (fr) 2015-11-17 2015-11-17 Procede de realisation de transistor a nanofil semi-conducteur et comprenant une grille et des espaceurs auto-alignes

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FR3043837A1 FR3043837A1 (fr) 2017-05-19
FR3043837B1 true FR3043837B1 (fr) 2017-12-15

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FR (1) FR3043837B1 (fr)

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FR3051970B1 (fr) 2016-05-25 2020-06-12 Commissariat A L'energie Atomique Et Aux Energies Alternatives Realisation d'une structure de canal formee d'une pluralite de barreaux semi-conducteurs contraints
US9831324B1 (en) 2016-08-12 2017-11-28 International Business Machines Corporation Self-aligned inner-spacer replacement process using implantation
US10340340B2 (en) * 2016-10-20 2019-07-02 International Business Machines Corporation Multiple-threshold nanosheet transistors
US10297663B2 (en) 2017-04-19 2019-05-21 International Business Machines Corporation Gate fill utilizing replacement spacer
US10541318B2 (en) * 2017-04-28 2020-01-21 International Business Machines Corporation Prevention of extension narrowing in nanosheet field effect transistors
US10193090B2 (en) * 2017-06-20 2019-01-29 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a semiconductor device and a semiconductor device
US10418493B2 (en) * 2017-12-19 2019-09-17 International Business Machines Corporation Tight pitch stack nanowire isolation
EP3567003A1 (fr) * 2018-05-11 2019-11-13 IMEC vzw Procédé de fabrication auto-aligné d'un transistor avec plusiers caneaux nanofil ou nanosheet, avec un espaceur comprenant du résine exposé au euv et du résine non-exposé
FR3088480B1 (fr) 2018-11-09 2020-12-04 Commissariat Energie Atomique Procede de collage avec desorption stimulee electroniquement
FR3091619B1 (fr) 2019-01-07 2021-01-29 Commissariat Energie Atomique Procédé de guérison avant transfert d’une couche semi-conductrice
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