ATE549748T1 - Verfahren zur herstellung eines dual-gate fet - Google Patents

Verfahren zur herstellung eines dual-gate fet

Info

Publication number
ATE549748T1
ATE549748T1 AT06710721T AT06710721T ATE549748T1 AT E549748 T1 ATE549748 T1 AT E549748T1 AT 06710721 T AT06710721 T AT 06710721T AT 06710721 T AT06710721 T AT 06710721T AT E549748 T1 ATE549748 T1 AT E549748T1
Authority
AT
Austria
Prior art keywords
dual
layer
gate fet
protrusion
gate
Prior art date
Application number
AT06710721T
Other languages
English (en)
Inventor
Noort Wibo Van
Franciscus Widdershoven
Radu Surdeanu
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE549748T1 publication Critical patent/ATE549748T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • H01L29/7854—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection with rounded corners
AT06710721T 2005-01-28 2006-01-23 Verfahren zur herstellung eines dual-gate fet ATE549748T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP05100571 2005-01-28
PCT/IB2006/050238 WO2006079964A2 (en) 2005-01-28 2006-01-23 Method of fabricating a dual-gate fet

Publications (1)

Publication Number Publication Date
ATE549748T1 true ATE549748T1 (de) 2012-03-15

Family

ID=36570476

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06710721T ATE549748T1 (de) 2005-01-28 2006-01-23 Verfahren zur herstellung eines dual-gate fet

Country Status (8)

Country Link
US (1) US7741182B2 (de)
EP (1) EP1844498B1 (de)
JP (1) JP2008529295A (de)
KR (1) KR20070099671A (de)
CN (1) CN100583452C (de)
AT (1) ATE549748T1 (de)
TW (1) TW200711000A (de)
WO (1) WO2006079964A2 (de)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100573835C (zh) * 2006-11-01 2009-12-23 中国科学院半导体研究所 一种制作纵向双栅金属-氧化物-半导体器件的方法
FR2910999B1 (fr) * 2006-12-28 2009-04-03 Commissariat Energie Atomique Cellule memoire dotee de transistors double-grille, a grilles independantes et asymetriques
US8288756B2 (en) * 2007-11-30 2012-10-16 Advanced Micro Devices, Inc. Hetero-structured, inverted-T field effect transistor
EP2311072B1 (de) 2008-07-06 2013-09-04 Imec Verfahren zum dotieren von halbleiterstrukturen
CN103107088B (zh) * 2011-11-11 2016-06-01 中芯国际集成电路制造(上海)有限公司 具有周围栅极结构的鳍型场效应晶体管及其制造方法
CN103295900B (zh) * 2012-03-02 2016-08-10 中芯国际集成电路制造(上海)有限公司 形成鳍部及鳍式场效应晶体管的方法
US8987790B2 (en) 2012-11-26 2015-03-24 International Business Machines Corporation Fin isolation in multi-gate field effect transistors
US9147682B2 (en) 2013-01-14 2015-09-29 Taiwan Semiconductor Manufacturing Company, Ltd. Fin spacer protected source and drain regions in FinFETs
US9318606B2 (en) 2013-01-14 2016-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and method of fabricating same
KR102220806B1 (ko) * 2013-06-20 2021-02-26 인텔 코포레이션 도핑된 서브-핀 영역을 갖는 비평면 반도체 디바이스 및 그 제조 방법
US10468528B2 (en) 2014-04-16 2019-11-05 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device with high-k metal gate stack
US9178067B1 (en) 2014-04-25 2015-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for FinFET device
US9721955B2 (en) 2014-04-25 2017-08-01 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for SRAM FinFET device having an oxide feature
US9224736B1 (en) 2014-06-27 2015-12-29 Taiwan Semicondcutor Manufacturing Company, Ltd. Structure and method for SRAM FinFET device
US9263555B2 (en) 2014-07-03 2016-02-16 Globalfoundries Inc. Methods of forming a channel region for a semiconductor device by performing a triple cladding process
CN105514163B (zh) * 2014-09-26 2018-09-07 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管及其形成方法
CN105870014B (zh) * 2015-01-19 2019-06-14 中国科学院微电子研究所 一种鳍的形成方法
CN105990172B (zh) * 2015-01-30 2018-07-31 上海华力微电子有限公司 嵌入式SiGe外延测试块的设计
TWI595650B (zh) * 2015-05-21 2017-08-11 蘇烱光 適應性雙閘極金氧半場效電晶體
CN105047717A (zh) * 2015-06-30 2015-11-11 上海华力微电子有限公司 鳍式场效应晶体管结构及其制作方法
CN104934480B (zh) * 2015-06-30 2017-11-24 上海华力微电子有限公司 鳍式场效应晶体管结构及其制作方法
CN108141215B9 (zh) 2015-07-29 2020-11-06 电路种子有限责任公司 互补电流场效应晶体管装置及放大器
WO2017019978A1 (en) 2015-07-30 2017-02-02 Circuit Seed, Llc Low noise trans-impedance amplifiers based on complementary current field-effect transistor devices
US10514716B2 (en) 2015-07-30 2019-12-24 Circuit Seed, Llc Reference generator and current source transistor based on complementary current field-effect transistor devices
WO2017019973A1 (en) 2015-07-30 2017-02-02 Circuit Seed, Llc Multi-stage and feed forward compensated complementary current field effect transistor amplifiers
US9818873B2 (en) * 2015-10-09 2017-11-14 Globalfoundries Inc. Forming stressed epitaxial layers between gates separated by different pitches
CN111816610A (zh) 2015-12-14 2020-10-23 电路种子有限责任公司 场效应晶体管
CN106057678B (zh) * 2016-06-17 2019-07-30 中国科学院微电子研究所 基于外延层的半导体器件及其制造方法及包括其的电子设备
US10014303B2 (en) * 2016-08-26 2018-07-03 Globalfoundries Inc. Devices with contact-to-gate shorting through conductive paths between fins and fabrication methods
FR3114686B1 (fr) * 2020-09-30 2023-03-31 St Microelectronics Rousset Transistor MOS à triple grille et procédé de fabrication d’un tel transistor

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1091413A3 (de) * 1999-10-06 2005-01-12 Lsi Logic Corporation Vollständig verarmter und invertierter CMOSFET mit vertikalem Kanal und dualem Gate
JP2002151688A (ja) * 2000-08-28 2002-05-24 Mitsubishi Electric Corp Ｍｏｓ型半導体装置およびその製造方法
US7163864B1 (en) * 2000-10-18 2007-01-16 International Business Machines Corporation Method of fabricating semiconductor side wall fin
US6716684B1 (en) * 2000-11-13 2004-04-06 Advanced Micro Devices, Inc. Method of making a self-aligned triple gate silicon-on-insulator device
US6630388B2 (en) * 2001-03-13 2003-10-07 National Institute Of Advanced Industrial Science And Technology Double-gate field-effect transistor, integrated circuit using the transistor and method of manufacturing the same
US6818952B2 (en) * 2002-10-01 2004-11-16 International Business Machines Corporation Damascene gate multi-mesa MOSFET
US7259425B2 (en) * 2003-01-23 2007-08-21 Advanced Micro Devices, Inc. Tri-gate and gate around MOSFET devices and methods for making same
US6815738B2 (en) * 2003-02-28 2004-11-09 International Business Machines Corporation Multiple gate MOSFET structure with strained Si Fin body
US7087506B2 (en) * 2003-06-26 2006-08-08 International Business Machines Corporation Method of forming freestanding semiconductor layer
US7078299B2 (en) * 2003-09-03 2006-07-18 Advanced Micro Devices, Inc. Formation of finFET using a sidewall epitaxial layer
KR100578130B1 (ko) * 2003-10-14 2006-05-10 삼성전자주식회사 핀 전계효과 트랜지스터를 위한 다중 실리콘 핀 및 그형성 방법

Also Published As

Publication number Publication date
CN100583452C (zh) 2010-01-20
WO2006079964A3 (en) 2006-11-02
EP1844498A2 (de) 2007-10-17
EP1844498B1 (de) 2012-03-14
JP2008529295A (ja) 2008-07-31
WO2006079964A2 (en) 2006-08-03
KR20070099671A (ko) 2007-10-09
US7741182B2 (en) 2010-06-22
US20080318375A1 (en) 2008-12-25
CN101142686A (zh) 2008-03-12
TW200711000A (en) 2007-03-16

Similar Documents

Publication Publication Date Title
ATE549748T1 (de) Verfahren zur herstellung eines dual-gate fet
ATE544178T1 (de) Halbleiterbauelemente und verfahren zur herstellung
TWI256728B (en) A recessed polysilicon gate structure for a stained silicon MOSFET device
ATE509374T1 (de) Herstellungsverfahren eines vertikalen mosfets mit graben-gate
DE602004029060D1 (de) Verfahren zur herstellung eines halbleiterbauelements mit ultraschmalem kanal
ATE490560T1 (de) Verfahren zur herstellung eines dünnschichttransistors mit einem oxidhalbleiter
ATE441938T1 (de) Herstellungsverfahren für finfets mit verringertem widerstand
TW200629418A (en) Method of making a double gate semiconductor device with self-aligned gates and structure thereof
ATE461526T1 (de) Hochdichtes finfet-integrationsverfahren
EP2302668A3 (de) Halbleiterbauelement mit spitzenlosen epitaktischen Source-/Drain-Bereichen
TW200633076A (en) FinFETs with long gate length at high density
JP2009267021A5 (de)
JP2006186303A5 (de)
JP2013544021A5 (de)
TW200802617A (en) Etched nanofin transistors
WO2009042981A3 (en) Method to introduce uniaxial strain in multigate nanoscale transistors by self aligned si to sige conversion processes and structures formed thereby
US20150097197A1 (en) Finfet with sigma cavity with multiple epitaxial material regions
JP2009224386A5 (de)
ATE496394T1 (de) Mos-vorrichtung und verfahren zu seiner herstellung
DE60211396D1 (de) Verfahren zur Herstellung von einem Gatter-Dielektrikum mit veränderlicher Dielektrizitätskonstante
ATE457525T1 (de) Verfahren zur herstellung selbstausgerichteter schottky-dioden für halbleiterbauelemente
WO2007110507A3 (fr) Procede de realisation d'un transistor a effet de champ a grilles auto-alignees
JP2011519469A5 (de)
TW200615612A (en) Array substrate for use in TFT-LCD and fabrication method thereof
ATE536634T1 (de) Verfahren zur herstellung eines halbleiterbauelements