ATE457525T1 - Verfahren zur herstellung selbstausgerichteter schottky-dioden für halbleiterbauelemente - Google Patents

Verfahren zur herstellung selbstausgerichteter schottky-dioden für halbleiterbauelemente

Info

Publication number
ATE457525T1
ATE457525T1 AT06831945T AT06831945T ATE457525T1 AT E457525 T1 ATE457525 T1 AT E457525T1 AT 06831945 T AT06831945 T AT 06831945T AT 06831945 T AT06831945 T AT 06831945T AT E457525 T1 ATE457525 T1 AT E457525T1
Authority
AT
Austria
Prior art keywords
junction
aligned
self
semiconductor components
schottky diodes
Prior art date
Application number
AT06831945T
Other languages
English (en)
Inventor
Markus Muller
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE457525T1 publication Critical patent/ATE457525T1/de

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66636Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66575Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/66583Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66643Lateral single gate silicon transistors with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7839Field effect transistors with field effect produced by an insulated gate with Schottky drain or source contact
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Light Receiving Elements (AREA)
AT06831945T 2005-11-28 2006-11-27 Verfahren zur herstellung selbstausgerichteter schottky-dioden für halbleiterbauelemente ATE457525T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP05300971 2005-11-28
PCT/IB2006/054446 WO2007060641A1 (en) 2005-11-28 2006-11-27 Method of fabricating self aligned schottky junctions for semiconductors devices

Publications (1)

Publication Number Publication Date
ATE457525T1 true ATE457525T1 (de) 2010-02-15

Family

ID=37865896

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06831945T ATE457525T1 (de) 2005-11-28 2006-11-27 Verfahren zur herstellung selbstausgerichteter schottky-dioden für halbleiterbauelemente

Country Status (7)

Country Link
US (1) US7884002B2 (de)
EP (1) EP1958244B1 (de)
JP (1) JP5001295B2 (de)
CN (1) CN101317253B (de)
AT (1) ATE457525T1 (de)
DE (1) DE602006012215D1 (de)
WO (1) WO2007060641A1 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2931294B1 (fr) 2008-05-13 2010-09-03 Commissariat Energie Atomique Procede de realisation d'un transistor a source et drain metalliques
US7989824B2 (en) * 2009-06-03 2011-08-02 Koninklijke Philips Electronics N.V. Method of forming a dielectric layer on a semiconductor light emitting device
FR2947384B1 (fr) * 2009-06-25 2012-03-30 Commissariat Energie Atomique Procede de realisation d'un transistor a source et drain metalliques
FR2976122A1 (fr) * 2011-05-31 2012-12-07 St Microelectronics Crolles 2 Transistor mosfet, composant incluant plusieurs tels transistors et procede de fabrication
KR101873911B1 (ko) 2011-06-07 2018-07-04 삼성전자주식회사 콘택 구조체를 포함하는 반도체 소자와 그 제조방법, 및 그것을 포함하는 전자 시스템
CN104769720B (zh) * 2012-10-23 2018-02-13 奥林巴斯株式会社 摄像装置、内窥镜、半导体装置以及半导体装置的制造方法
CN103745929A (zh) * 2013-12-24 2014-04-23 上海新傲科技股份有限公司 肖特基势垒mosfet的制备方法
EP3120388A4 (de) * 2014-03-21 2017-11-29 Intel Corporation Verfahren zur integration von ge-reichen p-mos-source/drainkontakten
DE102016119799B4 (de) 2016-10-18 2020-08-06 Infineon Technologies Ag Integrierte schaltung, die einen vergrabenen hohlraum enthält, und herstellungsverfahren
CN112018076A (zh) * 2020-07-28 2020-12-01 中国科学院微电子研究所 一种半导体结构及其制备方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0763095B2 (ja) * 1986-04-09 1995-07-05 株式会社東芝 半導体装置
JPH02188967A (ja) * 1989-01-18 1990-07-25 Nissan Motor Co Ltd 半導体装置
JP3444931B2 (ja) * 1993-08-25 2003-09-08 株式会社日立製作所 半導体装置及びその製造方法
JPH0974188A (ja) * 1995-09-05 1997-03-18 Mitsubishi Electric Corp 半導体装置及びその製造方法
JPH09312391A (ja) * 1996-05-22 1997-12-02 Toshiba Corp 半導体装置およびその製造方法
JPH10233451A (ja) * 1997-02-21 1998-09-02 Fujitsu Ltd 半導体装置の製造方法
TW439102B (en) * 1998-12-02 2001-06-07 Nippon Electric Co Field effect transistor and method of manufacturing the same
US6479843B2 (en) * 2000-04-27 2002-11-12 Motorola, Inc. Single supply HFET with temperature compensation
JP3833903B2 (ja) * 2000-07-11 2006-10-18 株式会社東芝 半導体装置の製造方法
US20020155721A1 (en) * 2001-04-03 2002-10-24 Macronix International Co., Ltd Method of forming shallow trench isolation structure
KR100434697B1 (ko) * 2001-09-05 2004-06-07 주식회사 하이닉스반도체 반도체소자의 제조방법
CN1206711C (zh) * 2002-03-28 2005-06-15 华邦电子股份有限公司 金属-氧化物-半导体晶体管的自对准硅化物的制备方法
DE102004012630A1 (de) 2004-03-16 2005-06-30 Infineon Technologies Ag Feldeffekttransistor mit geringem Leckstrom und Verfahren zu seiner Herstellung
JP3910971B2 (ja) * 2004-03-26 2007-04-25 株式会社東芝 電界効果トランジスタ
JP2006054423A (ja) * 2004-07-13 2006-02-23 Toshiba Corp 半導体装置及びその製造方法
US20060252191A1 (en) * 2005-05-03 2006-11-09 Advanced Micro Devices, Inc. Methodology for deposition of doped SEG for raised source/drain regions

Also Published As

Publication number Publication date
EP1958244B1 (de) 2010-02-10
WO2007060641A1 (en) 2007-05-31
EP1958244A1 (de) 2008-08-20
JP2009517860A (ja) 2009-04-30
JP5001295B2 (ja) 2012-08-15
US7884002B2 (en) 2011-02-08
CN101317253B (zh) 2010-10-27
CN101317253A (zh) 2008-12-03
DE602006012215D1 (de) 2010-03-25
US20080299715A1 (en) 2008-12-04

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