CN106252231A - 包括鳍结构的半导体器件及其制造方法 - Google Patents
包括鳍结构的半导体器件及其制造方法 Download PDFInfo
- Publication number
- CN106252231A CN106252231A CN201610004626.9A CN201610004626A CN106252231A CN 106252231 A CN106252231 A CN 106252231A CN 201610004626 A CN201610004626 A CN 201610004626A CN 106252231 A CN106252231 A CN 106252231A
- Authority
- CN
- China
- Prior art keywords
- layer
- fin structure
- dummy gate
- upper strata
- channel layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 68
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 36
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000009413 insulation Methods 0.000 claims abstract description 28
- 230000000717 retained effect Effects 0.000 claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 19
- 229910006990 Si1-xGex Inorganic materials 0.000 claims description 14
- 229910007020 Si1−xGex Inorganic materials 0.000 claims description 14
- 150000001875 compounds Chemical class 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 12
- 229910052732 germanium Inorganic materials 0.000 claims description 8
- 150000003377 silicon compounds Chemical class 0.000 claims description 8
- 239000012212 insulator Substances 0.000 claims description 7
- 230000005611 electricity Effects 0.000 claims 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 8
- 239000010410 layer Substances 0.000 description 262
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 37
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 19
- 230000008569 process Effects 0.000 description 15
- 229910052581 Si3N4 Inorganic materials 0.000 description 14
- 229910052814 silicon oxide Inorganic materials 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 13
- 238000005229 chemical vapour deposition Methods 0.000 description 12
- 230000009969 flowable effect Effects 0.000 description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 11
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 9
- 238000005530 etching Methods 0.000 description 8
- 238000005240 physical vapour deposition Methods 0.000 description 8
- 239000003989 dielectric material Substances 0.000 description 7
- 238000001039 wet etching Methods 0.000 description 7
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 6
- 239000007789 gas Substances 0.000 description 6
- 239000000126 substance Substances 0.000 description 6
- -1 AlInAs Inorganic materials 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 5
- 230000008901 benefit Effects 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 5
- 239000000203 mixture Substances 0.000 description 5
- 229910010271 silicon carbide Inorganic materials 0.000 description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 230000008439 repair process Effects 0.000 description 4
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 229910010038 TiAl Inorganic materials 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- 229910003818 SiH2Cl2 Inorganic materials 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 229910010041 TiAlC Inorganic materials 0.000 description 2
- KOOADCGQJDGAGA-UHFFFAOYSA-N [amino(dimethyl)silyl]methane Chemical compound C[Si](C)(C)N KOOADCGQJDGAGA-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 229910052756 noble gas Inorganic materials 0.000 description 2
- 239000002243 precursor Substances 0.000 description 2
- 239000011435 rock Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- ITWBWJFEJCHKSN-UHFFFAOYSA-N 1,4,7-triazonane Chemical compound C1CNCCNCCN1 ITWBWJFEJCHKSN-UHFFFAOYSA-N 0.000 description 1
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910004191 HfTi Inorganic materials 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910004200 TaSiN Inorganic materials 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- MJGARAGQACZIPN-UHFFFAOYSA-N aluminum hafnium(4+) oxygen(2-) Chemical compound [O--].[O--].[Al+3].[Hf+4] MJGARAGQACZIPN-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- IJKVHSBPTUYDLN-UHFFFAOYSA-N dihydroxy(oxo)silane Chemical compound O[Si](O)=O IJKVHSBPTUYDLN-UHFFFAOYSA-N 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 229910052986 germanium hydride Inorganic materials 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 1
- DOTMOQHOJINYBL-UHFFFAOYSA-N molecular nitrogen;molecular oxygen Chemical compound N#N.O=O DOTMOQHOJINYBL-UHFFFAOYSA-N 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 238000011017 operating method Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 150000002927 oxygen compounds Chemical class 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920001709 polysilazane Polymers 0.000 description 1
- FZHAPNGMFPVSLP-UHFFFAOYSA-N silanamine Chemical compound [SiH3]N FZHAPNGMFPVSLP-UHFFFAOYSA-N 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000012686 silicon precursor Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 229910003468 tantalcarbide Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66818—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the channel being thinned after patterning, e.g. sacrificial oxidation on fin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7849—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being provided under the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
- Materials Engineering (AREA)
Abstract
制造半导体FinFET的方法包括在衬底上方形成鳍结构。鳍结构包括部分从隔离绝缘层暴露的上层。在部分鳍结构上方形成伪栅极结构。伪栅极结构包括伪栅电极层和伪栅极介电层。形成源极和漏极。去除伪栅电极以使由伪栅极介电层覆盖的上层暴露。去除鳍结构的上层以产生由伪栅极介电层形成的凹槽。部分上层保留在凹槽的底部处。在凹槽中形成沟道层。去除伪栅极介电层。在沟道层上方形成栅极结构。本发明的实施例还涉及包括鳍结构的半导体器件及其制造方法。
Description
技术领域
本发明涉及半导体集成电路,以及更具体地,涉及具有鳍结构的半导体器件及其制造工艺。
背景技术
随着半导体工业在追求更高的器件密度、更高的性能和更低的成本的过程中进入纳米技术工艺节点,来自制造和设计问题的挑战已经引起了诸如鳍式场效应晶体管(FinFET)的三维设计的发展。FinFET器件通常包括具有高高宽比的半导体鳍,并且在该半导体鳍中形成半导体晶体管器件的沟道和源极/漏极区域。在鳍结构上方以及沿着鳍结构的侧面(例如,包裹)形成栅极,利用沟道和源极/漏极区域的增大的表面积的优势,以产生更快、更可靠和更易控制的半导体晶体管器件。在一些器件中,FinFET的源极/漏极(S/D)部分中的应变材料(例如,利用硅锗(SiGe)、碳化硅(SiC)和/或磷化硅(SiP))可以用于增强载流子迁移率。例如,施加至PMOS器件的沟道的压缩应力有利地增强沟道中的空穴迁移率。类似地,施加至NMOS器件的沟道的拉伸应力有利地增强沟道中的电子迁移率。然而,在互补金属氧化物半导体(CMOS)制造中实现这样的部件和工艺存在挑战。
发明内容
本发明的实施例提供了一种制造包括FinFET的半导体器件的方法,所述方法包括:在衬底上方形成鳍结构,所述鳍结构在第一方向上延伸并且包括上层,部分所述上层从隔离绝缘层暴露;在部分所述鳍结构上方形成伪栅极结构,所述伪栅极结构包括伪栅电极层和伪栅极介电层,所述伪栅极结构在垂直于所述第一方向的第二方向上延伸;形成源极和漏极;在所述伪栅极结构、所述鳍结构和所述隔离绝缘层上方形成界面绝缘层;去除所述伪栅电极层以使由所述伪栅极介电层覆盖的所述上层暴露;使所述上层凹进以产生由所述伪栅极介电层形成的凹槽,部分所述上层保留在所述凹槽的底部处;在所述凹槽中形成沟道层;去除所述伪栅极介电层;以及在所述沟道层上方形成栅极结构。
本发明的另一实施例提供了一种制造包括FinFET的半导体器件的方法,所述方法包括:在衬底上方形成鳍结构,所述鳍结构在第一方向上延伸并且包括上层,部分所述上层从隔离绝缘层暴露;在部分所述鳍结构上方形成伪栅极结构,所述伪栅极结构包括伪栅电极层和伪栅极介电层,所述伪栅极结构在垂直于所述第一方向的第二方向上延伸;形成源极和漏极;在所述伪栅极结构、所述鳍结构和所述隔离绝缘层上方形成界面绝缘层;去除所述伪栅电极层以使由所述伪栅极介电层覆盖的所述上层暴露;在暴露的伪栅极介电层上方形成硬掩模层;图案化所述硬掩模层和所述伪栅极介电层以使所述上层的上表面暴露;使所述上层凹进以产生由所述伪栅极介电层形成的凹槽,部分所述上层保留在所述凹槽的底部处;在所述凹槽中形成沟道层;去除所述硬掩模层和所述伪栅极介电层;以及在所述沟道层上方形成栅极结构。
本发明的又一实施例提供了一种包括FinFET的半导体器件,包括:鳍结构,设置在衬底上方,所述鳍结构在第一方向上延伸并且包括应力源层以及设置在所述应力源层上方的沟道层;栅极结构,包括栅电极层和栅极介电层,覆盖部分所述鳍结构并且在垂直于所述第一方向的第二方向上延伸;源极和漏极,均包括应力源材料,其中,在所述应力源层和所述沟道层之间的界面处的所述鳍结构的侧表面上未形成梯级。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳理解本发明的各个方面。应该强调,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1是用于制造具有鳍结构(FinFET)的半导体FET器件的示例性工艺流程图。
图2至图12示出了根据本发明的一个实施例的用于制造FinFET器件的示例性工艺。
图13至图16示出了根据本发明的另一个实施例的用于制造FinFET器件的示例性工艺。
图17和图18示出了根据本发明的另一个实施例的用于制造FinFET器件的示例性工艺。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实施例或实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,元件的尺寸不限于公开的范围或值,但可能依赖工艺条件和/或器件的期望的性质。更多地,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实例。为了简单和清楚的目的,各个部件可以任意地以不同的比例绘制。
此外,为便于描述,在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”和类似的空间相对术语,以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其它方式定向(旋转90度或在其它方位上),而本文使用的空间相对描述符可以同样地作出相应的解释。此外,术语“由…制成”可以意味着“包括”或“由…组成”。
图1是用于制造具有鳍结构的半导体FET器件(FinFET)的示例性流程图。该流程图仅示出了用于FinFET器件的整个制造工艺的相关部分。应该理解,在由图1示出的工艺之前、期间和之后可以提供额外的操作,并且对于方法的额外实施例,可以替换或消除以下描述的一些操作。操作/工艺的顺序可以互换。
在图1的S101中,如图2所示,在衬底10上方制造鳍结构。图2是根据一个实施例的处于制造工艺的各个阶段的一个阶段的FinFET器件的示例性立体图。
鳍结构20形成在衬底10上方并且突出于隔离绝缘层50。在一个实施例中,每个鳍结构20包括基层20B、中间层25和上层20A。在本实施例中,基层20B和上层20A包括硅,以及中间层25包括Si1-xGex,其中,x为0.1至0.9。在下文中,Si1-xGex可以简称为SiGe。在一些实施例中,中间层25是可选的。
根据一个实施例,为了制造鳍结构,在设置在衬底10上方的Si/SiGe/Si多层的堆叠件上方形成掩模层。掩模层通过例如热氧化工艺和/或化学汽相沉积(CVD)工艺形成。衬底10是例如杂质浓度在从约1×1015cm-3至约1×1018cm-3范围内的p-型硅衬底。在其他实施例中,衬底10是杂质浓度在从约1×1015cm-3至约1×1018cm-3范围内的n-型硅衬底。Si/SiGe/Si的堆叠件的每层都通过外延生长形成。在一些实施例中,例如,掩模层包括垫氧化物(例如,氧化硅)层和氮化硅掩模层。
可选地,衬底10可以包括诸如锗的另一元素半导体;化合物半导体,包括IV-IV族化合物半导体(诸如SiC和SiGe)、III-V族化合物半导体(诸如GaAs、GaP、GaN、InP、InAs、InSb、GaAsP、AlGaN,、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP);或它们的组合。在一个实施例中,衬底10是SOI(绝缘体上硅)衬底的硅层。当使用SOI衬底时,鳍结构可以突出于SOI衬底的硅层或可以突出于SOI衬底的绝缘层。在后一种情况下,SOI衬底的硅层用于形成鳍结构。诸如非晶Si或非晶SiC的非晶衬底或诸如氧化硅的绝缘材料也可以用作衬底10。衬底10可以包括已适当掺杂有杂质(例如,p-型或n-型电导率)的各个区域。
垫氧化物层可以通过使用热氧化或CVD工艺形成。氮化硅掩模层可以通过诸如溅射法的物理汽相沉积(PVD)、CVD、等离子体增强化学汽相沉积(PECVD)、常压化学汽相沉积(APCVD)、低压CVD(LPCVD)、高密度等离子体CVD(HDPCVD)、原子层沉积(ALD)和/或其它工艺形成。
在一些实施例中,垫氧化物层的厚度在从约2nm至约15nm的范围内,并且氮化硅掩模层的厚度在从约2nm至约50nm的范围内。在掩模层上方还形成掩模图案。例如,掩模图案为通过光刻操作形成的光刻胶图案。
通过使用掩模图案作为蚀刻掩模,形成了垫氧化物层和氮化硅掩模层的硬掩模图案。在一些实施例中,硬掩模图案的宽度在从约5nm至约40nm的范围内。在某些实施例中,硬掩模图案的宽度在从约7nm至约12nm的范围内。
通过使用硬掩模图案作为蚀刻掩模,通过使用干蚀刻方法和/或湿蚀刻方法的沟槽蚀刻将Si/SiGe/Si的堆叠件图案化成鳍结构20。鳍结构20的高度在从约20nm至约300nm的范围内。在某些实施例中,鳍结构20的高度在从约30nm至约60nm的范围内。当鳍结构的高度不均匀时,从衬底的高度可以从对应于鳍结构的平均高度的平面测量。鳍结构20的宽度在从约7nm至约15nm的范围内。
在这个实施例中,块状硅晶圆用作衬底10。然而,在一些实施例中,其它类型的衬底可以用作衬底10。例如,绝缘体上硅(SOI)晶圆可以用作起始材料,并且SOI晶圆的绝缘层构成衬底10以及SOI晶圆的硅层用于鳍结构20。Si/SiGe/Si堆叠件的每层均被适当地掺杂。
如图2所示,在X方向上延伸的三个鳍结构20设置为在Y方向上彼此邻近。然而,鳍结构的数量不限于三个。数量可以是一个、两个、四个、五个或更多。此外,一个或多个伪鳍结构可以设置为邻近鳍结构20的两侧以提高图案化工艺中的图案保真度。在一些实施例中,鳍结构20的宽度在从约5nm至约40nm的范围内,以及在某些实施例中,鳍结构20的宽度可以在从约7nm至约15nm的范围内。在一些实施例中,鳍结构20的高度在从约100nm至约300nm的范围内,以及在其它实施例中,鳍结构20的高度可以在从约50nm至约100nm的范围内。在一些实施例中,鳍结构20之间的间隔在从约5nm至约80nm的范围内,以及在其它实施例中,鳍结构20之间的间隔可以在从约7nm至约15nm的范围内。然而,本领域技术人员将认识到,贯穿说明书列举的尺寸和值仅仅是实例,并且可以改变以适应不同规模的集成电路。
在这个实施例中,FinFET器件是p-型FinFET。然而,在此处公开的技术也适用于n-型FinFET。
在形成鳍结构20之后,在鳍结构20上方形成隔离绝缘层50。
隔离绝缘层50包括一层或多层绝缘材料,例如,通过LPCVD(低压化学汽相沉积)、等离子体CVD或可流动CVD形成的二氧化硅、氮氧化硅和/或氮化硅。在可流动CVD中,沉积可流动介电材料,而不是氧化硅。顾名思义,可流动介电材料可以在沉积期间“流动”以填充具有高高宽比的间隙或间隔。通常,各种化学物质添加至含硅前体以允许沉积的膜流动。在一些实施例中,添加氮氢键。可流动介电前体(特别地,可流动氧化硅前体)的实例包括硅酸盐、硅氧烷、甲基倍半硅氧烷(MSQ)、氢倍半硅氧烷(HSQ)、MSQ/HSQ、全氢硅氮烷(TCPS)、全氢-聚硅氮烷(PSZ)、正硅酸乙酯(TEOS)或诸如三甲硅烷基胺(TSA)的甲硅烷基胺。这些可流动氧化硅材料在多个操作工艺中形成。在沉积可流动膜之后,将可流动膜固化并且之后使可流动膜退火以去除不期望的元素以形成氧化硅。当去除不期望的元素时,可流动膜致密和收缩。在一些实施例中,实施多个退火工艺。使可流动膜固化和退火多于一次。可流动膜可以由硼和/或磷掺杂。在一些实施例中,隔离绝缘层50可以由SOG、SiO、SiON、SiOCN或氟掺杂的硅酸盐玻璃(FSG)的一层或多层形成。
在鳍结构20上方形成隔离绝缘层50之后,实施平坦化操作以去除隔离绝缘层50的部分和掩模层(垫氧化物层和氮化硅掩模层)。平坦化操作可以包括化学机械抛光(CMP)和/或回蚀刻工艺。之后,如图2所示,进一步去除隔离绝缘层50以暴露鳍结构20的上层20A。
在某些实施例中,可以使用湿蚀刻工艺实施部分地去除隔离绝缘层50,例如,通过将衬底浸在氢氟酸(HF)中。在另一个实施例中,可以使用干蚀刻工艺实施部分地去除隔离绝缘层50。例如,可以使用CHF3或BF3用作蚀刻气体的干蚀刻工艺。
在形成隔离绝缘层50之后,可以实施例如退火工艺的热工艺以提高隔离绝缘层50的质量。在某些实施例中,通过在诸如N2、Ar或He环境的惰性气体环境中在从约900℃至约1050℃的范围内的温度下使用快速热退火(RTA)实施热工艺约1.5秒至约10秒。
在图1的S102中,如图3所示,在部分鳍结构20上方形成伪栅极结构40。图3是根据一个实施例的处于制造工艺的各个阶段的一个阶段的FinFET器件的示例性立体图。图4是沿着图3的线a-a的示例性截面图。
在隔离绝缘层50和暴露的鳍结构20A上方形成介电层和多晶硅层,以及之后实施图案化操作以获得包括由多晶硅制成的伪栅电极层45和伪栅极介电层30的伪栅极结构40。在一些实施例中,多晶硅层的图案化通过使用包括在氧化物层上方形成的氮化硅层的硬掩模实施。在其它实施例中,硬掩模可以包括在氮化物层上方形成的氧化硅层。伪栅极介电层30可以是通过CVD、PVD、ALD、电子束蒸发或其它合适的工艺形成的氧化硅。在一些实施例中,栅极介电层30可以包括氧化硅、氮化硅、氮氧化硅或高k电介质的一层或多层。在一些实施例中,栅极介电层的厚度在从约5nm至约20nm的范围内,在其它实施例中,栅极介电层的厚度在从约5nm至约10nm的范围内。
在一些实施例中,伪栅电极层45可以包括单层或多层结构。伪栅电极层45可以是均匀或非均匀掺杂的掺杂多晶硅。伪栅电极层45可以使用诸如ALD、CVD、PVD、镀或它们的组合的合适的工艺形成。在本实施例中,伪栅电极层45的宽度在从约30nm至约60nm的范围内。在一些实施例中,栅电极层的厚度在从约30nm至约50nm的范围内。
伪栅极结构40还包括设置在伪栅电极45的两个主侧面上方的侧壁绝缘层47。侧壁绝缘层47可以包括氧化硅、氮化硅、氮氧化硅或其它合适的材料的一层或多层。侧壁绝缘层47可以包括单层或多层结构。侧壁绝缘材料的毯状层可以通过CVD、PVD、ALD或其它合适的技术形成。之后,对侧壁绝缘材料实施各向异性蚀刻以在栅极结构的两个主侧面上形成一对侧壁绝缘层47。在一些实施例中,侧壁绝缘层47的厚度在从约5nm至约30nm的范围内,以及在其它实施例中,侧壁绝缘层47的厚度在从约10nm至约20nm的范围内。
在图1的S103中,如图5所示,形成源极/漏极结构。图5是根据一个实施例的处于制造工艺的各个阶段的一个阶段的FinFET器件的示例性立体图。
向下蚀刻未由伪栅极结构40覆盖的部分上层20A以形成凹进部分。在一些实施例中,鳍结构的上层20A蚀刻至基层20B的水平。
之后,在凹进部分中形成适当的应变层60。在一些实施例中,应变层包括多层(包括Si或SiGe)。在这个实施例中,在凹进部分中外延形成Si。
在图5中,应变层60形成在隔离绝缘层50之上并且与邻近的应变层合并。然而,应变层60可以不合并并且可以从相应的凹进部分单独形成。应变层60成为FinFET器件的源极或漏极。
在图1的S104中,如图6所示,去除伪栅电极45。图6是根据一个实施例的处于制造工艺的各个阶段的一个阶段的沿着Y方向的示例性截面图。
可以通过湿蚀刻和/或干蚀刻去除伪栅电极45的多晶硅。在伪栅电极45的蚀刻期间,应变层60可以由诸如光刻胶、氮化硅或氧化硅的覆盖层覆盖。
在图1的S105中,使鳍结构20的上层20A凹进。图7和图8是根据一个实施例的处于制造工艺的各个阶段的沿着Y方向的示例性截面图。
如图7所示,通过使用例如各向异性干蚀刻去除覆盖上层20A的顶面的伪栅极介电层30的顶部。
如图8所示,将鳍结构20的部分上层20A去除(向下凹进)至隔离绝缘层50的上表面下面。在一些实施例中,可以在约1毫托至10毫托的压力下通过使用含氟气体(例如,NF3)蚀刻伪栅极介电层30,以及可以在约200毫托至600毫托的压力下通过使用含氟气体(例如,NF3)、H2和惰性气体(例如,Ar)蚀刻上层20A。
在一些实施例中,从隔离绝缘层50的上表面测量的凹槽的深度在从5nm至50nm的范围内,以及在其它实施例中,凹槽的深度在从10nm至30nm的范围内。
在图1的S106中,如图9和图10所示,形成沟道层70。图9和图10是根据一个实施例的处于制造工艺的各个阶段的沿着Y方向的示例性截面图。
如图9所示,在通过去除鳍结构20的部分上层20A形成的凹槽中形成沟道层70。在一个实施例中,沟道层70包括外延生长的SiGe。SiGe层的外延生长可以通过在从约500℃至约700℃范围内的温度下以及在从约10托至约100托(约133Pa至约1333Pa)的范围内的压力下使用SiH4和/或SiH2Cl2和GeH4作为源气体来实施。SiGe沟道层70表示为Si1-xGex,其中,在一些实施例中,X在从约0.1至约0.9的范围内,以及在其它实施例中,X在从约0.3至约0.5的范围内。沟道层可以包括诸如SiC、SiP、SiCP、GaAs、InGaAs、InP或GaN的化合物半导体的一层或多层。
在一些实施例中,SiGe沟道层70可以形成在与伪栅极介电层30相同的高度处,以及在其它实施例中,SiGe沟道层70可以形成在略低于伪栅极介电层30的高度。
因为SiGe沟道层70形成在由上层20A填充的间隔(凹槽)中,所以SiGe沟道层70的宽度基本与剩余的上层20A的宽度相同。在SiGe沟道层70和剩余的上层20A的界面处的侧表面上,基本没有梯级或不连续(以及,即使有,只有几埃)。在一些实施例中,剩余的上层20A的厚度在从约1nm至约50nm的范围内,以及可以在从约20nm至约40nm的范围内。
如图10所示,通过例如湿蚀刻去除伪栅极介电层30,从而使得暴露SiGe沟道层70。如图10所示,SiGe沟道层70的底部嵌入在隔离绝缘层50内。相应地,形成包括SiGe沟道层70、Si应变层20A、SiGe层25和Si层20B的半导体鳍结构。
在图1的S107中,如图11所示,形成覆盖层80。图11是根据一个实施例的处于制造工艺的各个阶段的一个阶段的沿着Y方向的示例性截面图。在一些实施例中,可以不形成覆盖层80。
在本发明的一个实施例中,覆盖层80包括外延生长的Si或硅化合物(例如,SiC、SiP或SiCP)。当由SiGe形成沟道层70时,覆盖层80可以抑制锗在随后的热操作中的扩散以及可以改进沟道和栅极电介质之间的界面结构。Si覆盖层80的外延生长可以通过在从约500℃至约700℃的范围内的温度下以及在从约10托至约100托(约133Pa至约1333Pa)的范围内的压力下使用SiH4和/或SiH2Cl2作为源气体来实施。在一些实施例中,Si覆盖层80的厚度在从0.1nm至50nm的范围内,以及在其它实施例中,Si覆盖层80的厚度在从约0.5nm至约2nm的范围内。Si覆盖层80可以通过原子层沉积(ALD)方法形成。在某些实施例中,未形成覆盖层80。
在图1的S108中,如图12所示,形成金属栅极结构。图12是根据一个实施例的处于制造工艺的各个阶段的一个阶段的沿着Y方向的示例性截面图。
在设置在沟道层70上方的界面层(未示出)上方形成栅极介电层90。在一些实施例中,界面层可以包括厚度在从0.2nm至1.5nm的氧化硅。氧化硅界面层可以通过氧化Si覆盖层80形成。在其它实施例中,界面层的厚度在从约0.5nm至约1.0nm的范围内。栅极介电层90包括诸如氧化硅、氮化硅或高k介电材料的介电材料、其它合适的介电材料和/或它们的组合的一层或多层。高k介电材料的实例包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆、氧化铝、氧化钛、二氧化铪-氧化铝(HfO2-Al2O3)合金、其它合适的高k介电材料和/或它们的组合。栅极介电层90通过例如化学汽相沉积(CVD)、物理汽相沉积(PVD)、原子层沉积(ALD)、高密度等离子体CVD(HDPCVD)、其它合适的方法和/或它们的组合形成。在一些实施例中,栅极介电层90的厚度在从约1nm至约10nm的范围内,以及在其它实施例中,栅极介电层90的厚度可以在从约2nm至约7nm的范围内。在一些实施例中,栅极介电层90可以包括由二氧化硅制成的界面层。
如图12所示,在栅极介电层90上方形成栅电极100。栅电极100包括诸如多晶硅、铝、铜、钛、钽、钨、钴、钼、氮化钽、硅化镍、硅化钴、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金属合金、其它合适的材料和/或它们的组合的任何合适的材料的一层或多层。
在本发明的某些实施例中,一个或多个功函调整层(未示出)可以介入在栅极介电层90和栅电极100之间。功函调整层由诸如TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC的单层或这些材料的两层或更多的多层的导电材料制成。对于p-FinFET,TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC和Co的一种或多种可以用作功函调整层。
应该理解,FinFET器件可以经受进一步的CMOS工艺以形成诸如接触件/通孔、互连金属层、介电层、钝化层等的各个部件。
图13至图16示出了根据本发明的另一个实施例的用于制造FinFET器件的示例性工艺。
如图13所示,在如图6所示地去除伪栅电极45之后,在伪栅极介电层30上方形成硬掩模层110。图13是根据一个实施例的处于制造工艺的各个阶段的一个阶段的沿着Y方向的示例性截面图。
在本发明的一个实施例中,硬掩模层110包括金属氮化物、金属氮氧化物或金属碳氮氧化物的一层或多层,诸如氮化钛(TiN)、氮化硅(SiN)、SiCN、SiOCN、SiON或氮化钽(TaN)。在这个实施例中,使用TiN。在一些实施例中,硬掩模层110的厚度在从约1nm至约5nm的范围内,以及在其它实施例中,硬掩模层110的厚度在从约1nm至约3nm的范围内。硬掩模层110通过例如CVD、包括溅射的PVD、ALD、HDPCVD、其它合适的方法和/或它们的组合形成。
图14是根据一个实施例的处于制造工艺的各个阶段的一个阶段的沿着Y方向的示例性截面图。如图14所示,通过使用例如干蚀刻去除覆盖上层20A的顶面的伪栅极介电层30和硬掩模层110的顶部。因为鳍顶部的蚀刻速率快于鳍侧面的蚀刻速率,因此基本仅去除鳍的顶部。
图15是根据一个实施例的处于制造工艺的各个阶段的一个阶段的沿着Y方向的示例性截面图。如图15所示,类似于图8,通过使用含氟气体(例如,NF3)、H2和惰性气体(例如,Ar)将鳍结构20的部分上层20A去除(向下凹进)至隔离绝缘层50的上表面的下面。
图16是根据一个实施例的处于制造工艺的各个阶段的一个阶段的沿着Y方向的示例性截面图。如图16所示,去除硬掩模层110。在本发明的一个实施例中,湿蚀刻用于去除TiN硬掩模层110。
在去除硬掩模层110之后,实施参照图8至图12描述的操作。
图17和图18示出了根据本发明另一个实施例的用于制造FinFET器件的示例性工艺。
图17是根据一个实施例的处于制造工艺的各个阶段的一个阶段的沿着Y方向的示例性截面图。在如图10所示地形成沟道层70之后,修整沟道层70以使沟道层70的宽度减小。当沟道层70是SiGe时,使用例如NH4OH、H2O2和H2O的混合物实施湿蚀刻以修整沟道层70。在一些实施例中,通过这个湿蚀刻,SiGe沟道层70的宽度的减小量为约0.5nm至约5nm。在其它实施例中,减小量在从约1nm至约3nm的范围内。
如图17所示,在减小沟道层70的宽度之后,类似于图11,形成覆盖层80。在这个实施例中,覆盖层80是硅。
图18是根据一个实施例的处于制造工艺的各个阶段的一个阶段的沿着Y方向的示例性截面图。类似于图12,形成金属栅极结构。
在这个实施例中,调整SiGe沟道层70的减小量和Si覆盖层80的厚度,从而使得SiGe沟道层70的总宽度变成期望的宽度。
在此处描述的各个实施例或实例提供了超越现有技术的若干优势。例如,在本发明中,由于在形成源极/漏极之后形成SiGe沟道层,因此SiGe层不会经受许多热操作(例如,用于源极/漏极的外延生长等)。如果首先形成SiGe沟道层并且之后形成源极/漏极,则SiGe沟道层中的锗可能扩散至伪栅电极(例如,多晶硅伪栅电极)内。如果锗扩散至多晶硅伪栅电极内,则在去除伪栅电极之后,多晶硅残留物趋于保留在鳍结构之间,这将降低FET的性能。此外,由于许多热操作,SiGe沟道层的表面粗糙度趋于增加。SiGe沟道层的表面粗糙度(RMS)可以大于0.2nm。
然而,在本发明中,避免锗通过伪栅极介电层扩散至伪多晶硅栅电极内是可能的。此外,由于SiGe沟道层经受较少的热操作,保持SiGe沟道层的平滑表面是可能的。在一些实施例中,本发明中的SiGe沟道层的表面粗糙度(RMS)小于0.2nm,以及在其它实施例中,SiGe沟道层的表面粗糙度(RMS)可以小于0.15nm。此外,更精确地控制SiGe沟道层的宽度是可能的。
应该理解,不是所有的优势都必需在这里讨论,没有特殊的优势对于所有实施例或实例都是需要的,并且其它实施例或实例可以提供不同的优势。
根据本发明的一个方面,制造包括FinFET的半导体器件的方法包括在衬底上方形成鳍结构。鳍结构在第一方向上延伸并且包括上层。部分上层从隔离绝缘层暴露。在部分鳍结构上方形成伪栅极结构。伪栅极结构包括伪栅电极层和伪栅极介电层。伪栅极结构在垂直于第一方向的第二方向上延伸。形成源极和漏极。在伪栅极结构、鳍结构和隔离绝缘层上方形成界面绝缘层。去除伪栅电极以使由伪栅极介电层覆盖的上层暴露。使上层凹进以产生由伪栅极介电层形成的凹槽。部分上层保留在凹槽的底部处。在凹槽中形成沟道层。去除伪栅极介电层。在沟道层上方形成栅极结构。
在上述方法中,其中,所述沟道层包括化合物半导体。
在上述方法中,其中,所述沟道层包括Si1-xGex,其中,x为0.1至0.9。
在上述方法中,其中,所述沟道层包括化合物半导体,其中:所述鳍结构的所述上层包括Si,以及所述沟道层设置在剩余的上层上。
在上述方法中,其中,所述沟道层包括化合物半导体,还包括形成覆盖层以覆盖所述沟道层,其中,在覆盖所述沟道层的所述覆盖层上方形成所述栅极结构。
在上述方法中,其中,所述沟道层包括化合物半导体,还包括形成覆盖层以覆盖所述沟道层,其中,在覆盖所述沟道层的所述覆盖层上方形成所述栅极结构,其中,所述覆盖层包括Si或硅化合物。
在上述方法中,其中,所述沟道层包括Si1-xGex,其中,x为0.1至0.9,其中,所述鳍结构还包括:设置在所述上层下方的中间层;以及设置在所述中间层下方的基层。
在上述方法中,其中,所述沟道层包括Si1-xGex,其中,x为0.1至0.9,其中,所述鳍结构还包括:设置在所述上层下方的中间层;以及设置在所述中间层下方的基层,所述中间层包括Si1-xGex或包含Si和Ge的化合物,其中,x为0.1至0.9。
在上述方法中,还包括:修整所述沟道层以减小所述沟道层的宽度;以及形成覆盖层以覆盖修整的沟道层,其中,所述栅极结构形成在覆盖所述修整的沟道层的所述覆盖层上方。
根据本发明的另一个方面,制造包括FinFET的半导体器件的方法包括在衬底上方形成鳍结构。鳍结构在第一方向上延伸并且包括上层。部分上层从隔离绝缘层暴露,在部分鳍结构上方形成伪栅极结构。伪栅极结构包括伪栅电极层和伪栅极介电层。伪栅极结构在垂直于第一方向的第二方向上延伸。形成源极和漏极。在伪栅极结构、鳍结构和隔离绝缘层上方形成界面绝缘层。去除伪栅电极以使由伪栅极介电层覆盖的上层暴露。在暴露的伪栅极介电层上方形成硬掩模层。图案化硬掩模层和伪栅极介电层以使上层的上表面暴露。使上层凹进以产生由伪栅极介电层形成的凹槽。部分上层保留在凹槽的底部处。在凹槽中形成沟道层。去除硬掩模层和伪栅极介电层。在沟道层上方形成栅极结构。
在上述方法中,其中,所述沟道层包括Si1-xGex或包含Si和Ge的化合物,其中,x为0.1至0.9。
在上述方法中,其中,所述沟道层包括Si1-xGex或包含Si和Ge的化合物,其中,x为0.1至0.9,其中:所述鳍结构的所述上层包括Si或硅化合物,以及所述沟道层设置在剩余的上层上。
在上述方法中,其中,所述伪栅电极层包括多晶硅。
在上述方法中,其中,所述沟道层包括Si1-xGex或包含Si和Ge的化合物,其中,x为0.1至0.9,所述方法还包括形成覆盖层以覆盖所述沟道层,其中,在覆盖所述沟道层的所述覆盖层上方形成所述栅极结构。
在上述方法中,其中,所述沟道层包括Si1-xGex或包含Si和Ge的化合物,其中,x为0.1至0.9,其中:所述鳍结构的所述上层包括Si或硅化合物,以及所述沟道层设置在剩余的上层上,其中,所述鳍结构还包括:设置在所述上层下方的中间层;以及设置在所述中间层下方的基层。
在上述方法中,还包括:修整所述沟道层以减小所述沟道层的宽度;以及形成覆盖层以覆盖修整的沟道层,其中,在覆盖所述修整的沟道层的所述覆盖层上方形成所述栅极结构。
在上述方法中,其中,所述硬掩模层包括选自由金属氮化物、金属氮氧化物和金属碳氮氧化物组成的组的至少一种。
根据本发明的另一个方面。包括FinFET的半导体器件包括设置在衬底上方的鳍结构、栅极结构以及源极和漏极。鳍结构在第一方向上延伸并且包括应力源层和设置在应力源层上方的沟道层。栅极结构包括栅电极层和栅极介电层,栅极结构覆盖部分鳍结构,并且在垂直于第一方向的第二方向上延伸。每个源极和漏极都包括应力源材料。在应力源层和沟道层之间的界面处的鳍结构的侧表面上未形成梯级。
在上述半导体器件中,其中:所述应力源层包括Si或硅化合物,以及所述沟道层包括Si1-xGex或包含Si和Ge的化合物,其中,x为0.1至0.9。
在上述半导体器件中,还包括覆盖所述沟道层的覆盖层。
上面概述了若干实施例的特征,使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,本文中他们可以做出多种变化、替换以及改变。
Claims (10)
1.一种制造包括FinFET的半导体器件的方法,所述方法包括:
在衬底上方形成鳍结构,所述鳍结构在第一方向上延伸并且包括上层,部分所述上层从隔离绝缘层暴露;
在部分所述鳍结构上方形成伪栅极结构,所述伪栅极结构包括伪栅电极层和伪栅极介电层,所述伪栅极结构在垂直于所述第一方向的第二方向上延伸;
形成源极和漏极;
在所述伪栅极结构、所述鳍结构和所述隔离绝缘层上方形成界面绝缘层;
去除所述伪栅电极层以使由所述伪栅极介电层覆盖的所述上层暴露;
使所述上层凹进以产生由所述伪栅极介电层形成的凹槽,部分所述上层保留在所述凹槽的底部处;
在所述凹槽中形成沟道层;
去除所述伪栅极介电层;以及
在所述沟道层上方形成栅极结构。
2.根据权利要求1所述的方法,其中,所述沟道层包括化合物半导体。
3.根据权利要求1所述的方法,其中,所述沟道层包括Si1-xGex,其中,x为0.1至0.9。
4.根据权利要求2所述的方法,其中:
所述鳍结构的所述上层包括Si,以及
所述沟道层设置在剩余的上层上。
5.根据权利要求2所述的方法,还包括形成覆盖层以覆盖所述沟道层,其中,在覆盖所述沟道层的所述覆盖层上方形成所述栅极结构。
6.根据权利要求5所述的方法,其中,所述覆盖层包括Si或硅化合物。
7.根据权利要求3所述的方法,其中,所述鳍结构还包括:
设置在所述上层下方的中间层;以及
设置在所述中间层下方的基层。
8.根据权利要求7所述的方法,其中,所述中间层包括Si1-xGex或包含Si和Ge的化合物,其中,x为0.1至0.9。
9.一种制造包括FinFET的半导体器件的方法,所述方法包括:
在衬底上方形成鳍结构,所述鳍结构在第一方向上延伸并且包括上层,部分所述上层从隔离绝缘层暴露;
在部分所述鳍结构上方形成伪栅极结构,所述伪栅极结构包括伪栅电极层和伪栅极介电层,所述伪栅极结构在垂直于所述第一方向的第二方向上延伸;
形成源极和漏极;
在所述伪栅极结构、所述鳍结构和所述隔离绝缘层上方形成界面绝缘层;
去除所述伪栅电极层以使由所述伪栅极介电层覆盖的所述上层暴露;
在暴露的伪栅极介电层上方形成硬掩模层;
图案化所述硬掩模层和所述伪栅极介电层以使所述上层的上表面暴露;
使所述上层凹进以产生由所述伪栅极介电层形成的凹槽,部分所述上层保留在所述凹槽的底部处;
在所述凹槽中形成沟道层;
去除所述硬掩模层和所述伪栅极介电层;以及
在所述沟道层上方形成栅极结构。
10.一种包括FinFET的半导体器件,包括:
鳍结构,设置在衬底上方,所述鳍结构在第一方向上延伸并且包括应力源层以及设置在所述应力源层上方的沟道层;
栅极结构,包括栅电极层和栅极介电层,覆盖部分所述鳍结构并且在垂直于所述第一方向的第二方向上延伸;
源极和漏极,均包括应力源材料,
其中,在所述应力源层和所述沟道层之间的界面处的所述鳍结构的侧表面上未形成梯级。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/730,210 US10269968B2 (en) | 2015-06-03 | 2015-06-03 | Semiconductor device including fin structures and manufacturing method thereof |
US14/730,210 | 2015-06-03 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN106252231A true CN106252231A (zh) | 2016-12-21 |
CN106252231B CN106252231B (zh) | 2020-04-17 |
Family
ID=57451245
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201610004626.9A Active CN106252231B (zh) | 2015-06-03 | 2016-01-05 | 包括鳍结构的半导体器件及其制造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US10269968B2 (zh) |
KR (1) | KR101799646B1 (zh) |
CN (1) | CN106252231B (zh) |
TW (1) | TWI588907B (zh) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110517990A (zh) * | 2018-05-21 | 2019-11-29 | 中芯国际集成电路制造(北京)有限公司 | 半导体结构及其形成方法 |
CN110957224A (zh) * | 2018-09-27 | 2020-04-03 | 台湾积体电路制造股份有限公司 | 半导体器件及其形成方法 |
CN110970505A (zh) * | 2018-09-28 | 2020-04-07 | 台湾积体电路制造股份有限公司 | 半导体器件及其制造方法 |
CN111128734A (zh) * | 2018-10-31 | 2020-05-08 | 台湾积体电路制造股份有限公司 | 制造半导体器件的方法和半导体器件 |
CN113555317A (zh) * | 2020-07-10 | 2021-10-26 | 台湾积体电路制造股份有限公司 | 制造半导体器件的方法和半导体器件 |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102374108B1 (ko) * | 2015-06-02 | 2022-03-14 | 삼성전자주식회사 | 스트레서를 갖는 반도체 장치 및 그 제조 방법 |
CN108028268B (zh) * | 2015-08-07 | 2021-01-01 | 东京毅力科创株式会社 | 没有伪栅极的图案化方法 |
US9837538B2 (en) * | 2016-03-25 | 2017-12-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US10332986B2 (en) * | 2016-08-22 | 2019-06-25 | International Business Machines Corporation | Formation of inner spacer on nanosheet MOSFET |
US9837408B1 (en) * | 2016-09-28 | 2017-12-05 | International Business Machines Corporation | Forming strained and unstrained features on a substrate |
TWI604569B (zh) * | 2016-11-15 | 2017-11-01 | 新唐科技股份有限公司 | 半導體裝置及其形成方法 |
US10522643B2 (en) | 2017-04-26 | 2019-12-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Device and method for tuning threshold voltage by implementing different work function metals in different segments of a gate |
WO2018236357A1 (en) * | 2017-06-20 | 2018-12-27 | Intel Corporation | THIN-FILM TRANSISTORS HAVING A RELATIVELY INCREASED WIDTH |
US10381479B2 (en) * | 2017-07-28 | 2019-08-13 | International Business Machines Corporation | Interface charge reduction for SiGe surface |
KR102388463B1 (ko) * | 2017-08-21 | 2022-04-20 | 삼성전자주식회사 | 채널 패턴을 포함하는 반도체 소자 및 그 제조 방법 |
US10361280B2 (en) * | 2017-08-30 | 2019-07-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Gate structure for semiconductor device |
US11222977B2 (en) | 2017-09-26 | 2022-01-11 | Intel Corporation | Source/drain diffusion barrier for germanium NMOS transistors |
DE112017008124T5 (de) * | 2017-09-29 | 2020-08-20 | Intel Corporation | Bauelement, verfahren und system zum bereitstellen eines gestressten kanals eines transistors |
US10388756B2 (en) * | 2018-01-12 | 2019-08-20 | United Microelectronics Corp. | Semiconductor device and method for fabricating the same |
US10692773B2 (en) * | 2018-06-29 | 2020-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Forming nitrogen-containing low-K gate spacer |
US11245023B1 (en) * | 2020-07-31 | 2022-02-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
EP3989273A1 (en) * | 2020-10-20 | 2022-04-27 | Imec VZW | A method for forming a semiconductor device and a semiconductor device |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201421693A (zh) * | 2012-11-29 | 2014-06-01 | Taiwan Semiconductor Mfg | FinFET元件與其形成方法 |
CN103855010A (zh) * | 2012-11-30 | 2014-06-11 | 中国科学院微电子研究所 | FinFET及其制造方法 |
CN103915504A (zh) * | 2014-04-04 | 2014-07-09 | 唐棕 | 一种鳍型半导体结构及其成型方法 |
JP2014220532A (ja) * | 2014-08-22 | 2014-11-20 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | 半導体装置の製造方法、及び、半導体装置 |
CN104576735A (zh) * | 2013-10-16 | 2015-04-29 | 台湾积体电路制造股份有限公司 | 具有掩埋绝缘层的FinFET及其形成方法 |
CN104835844A (zh) * | 2013-11-26 | 2015-08-12 | 三星电子株式会社 | 鳍式场效应晶体管半导体装置及其制造方法 |
Family Cites Families (79)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100625175B1 (ko) * | 2004-05-25 | 2006-09-20 | 삼성전자주식회사 | 채널층을 갖는 반도체 장치 및 이를 제조하는 방법 |
US20060030093A1 (en) * | 2004-08-06 | 2006-02-09 | Da Zhang | Strained semiconductor devices and method for forming at least a portion thereof |
US7393733B2 (en) | 2004-12-01 | 2008-07-01 | Amberwave Systems Corporation | Methods of forming hybrid fin field-effect transistor structures |
US7425740B2 (en) | 2005-10-07 | 2008-09-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and structure for a 1T-RAM bit cell and macro |
US7923337B2 (en) * | 2007-06-20 | 2011-04-12 | International Business Machines Corporation | Fin field effect transistor devices with self-aligned source and drain regions |
US7939889B2 (en) * | 2007-10-16 | 2011-05-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reducing resistance in source and drain regions of FinFETs |
US8048723B2 (en) | 2008-12-05 | 2011-11-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Germanium FinFETs having dielectric punch-through stoppers |
US8776734B1 (en) | 2008-05-19 | 2014-07-15 | Innovative Environmental Solutions, Llc | Remedial system: a pollution control device for utilizing and abating volatile organic compounds |
US7838373B2 (en) * | 2008-07-30 | 2010-11-23 | Intel Corporation | Replacement spacers for MOSFET fringe capacitance reduction and processes of making same |
US8053299B2 (en) | 2009-04-17 | 2011-11-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabrication of a FinFET element |
US8415718B2 (en) | 2009-10-30 | 2013-04-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming epi film in substrate trench |
US8395195B2 (en) | 2010-02-09 | 2013-03-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bottom-notched SiGe FinFET formation using condensation |
US8492235B2 (en) * | 2010-12-29 | 2013-07-23 | Globalfoundries Singapore Pte. Ltd. | FinFET with stressors |
US8691650B2 (en) * | 2011-04-14 | 2014-04-08 | International Business Machines Corporation | MOSFET with recessed channel film and abrupt junctions |
US8637359B2 (en) * | 2011-06-10 | 2014-01-28 | International Business Machines Corporation | Fin-last replacement metal gate FinFET process |
US9761666B2 (en) * | 2011-06-16 | 2017-09-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained channel field effect transistor |
US8618556B2 (en) | 2011-06-30 | 2013-12-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET design and method of fabricating same |
US8609518B2 (en) | 2011-07-22 | 2013-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Re-growing source/drain regions from un-relaxed silicon layer |
US8841701B2 (en) * | 2011-08-30 | 2014-09-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device having a channel defined in a diamond-like shape semiconductor structure |
US8723272B2 (en) * | 2011-10-04 | 2014-05-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device and method of manufacturing same |
US8735232B2 (en) * | 2011-11-29 | 2014-05-27 | GlobalFoundries, Inc. | Methods for forming semiconductor devices |
US8815712B2 (en) | 2011-12-28 | 2014-08-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for epitaxial re-growth of semiconductor region |
US8698199B2 (en) * | 2012-01-11 | 2014-04-15 | United Microelectronics Corp. | FinFET structure |
US9171925B2 (en) * | 2012-01-24 | 2015-10-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-gate devices with replaced-channels and methods for forming the same |
US9466696B2 (en) * | 2012-01-24 | 2016-10-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs and methods for forming the same |
US9281378B2 (en) * | 2012-01-24 | 2016-03-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin recess last process for FinFET fabrication |
US8697523B2 (en) * | 2012-02-06 | 2014-04-15 | International Business Machines Corporation | Integration of SMT in replacement gate FINFET process flow |
US8742509B2 (en) | 2012-03-01 | 2014-06-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Apparatus and method for FinFETs |
US8785285B2 (en) | 2012-03-08 | 2014-07-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and methods of manufacture thereof |
KR101894221B1 (ko) * | 2012-03-21 | 2018-10-04 | 삼성전자주식회사 | 전계 효과 트랜지스터 및 이를 포함하는 반도체 장치 |
US8828813B2 (en) * | 2012-04-13 | 2014-09-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Replacement channels |
US8652932B2 (en) * | 2012-04-17 | 2014-02-18 | International Business Machines Corporation | Semiconductor devices having fin structures, and methods of forming semiconductor devices having fin structures |
US8912606B2 (en) * | 2012-04-24 | 2014-12-16 | Globalfoundries Inc. | Integrated circuits having protruding source and drain regions and methods for forming integrated circuits |
US9171929B2 (en) | 2012-04-25 | 2015-10-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained structure of semiconductor device and method of making the strained structure |
US8729634B2 (en) | 2012-06-15 | 2014-05-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET with high mobility and strain channel |
US8647937B2 (en) * | 2012-06-26 | 2014-02-11 | Globalfoundries Singapore Pte. Ltd. | Deep depleted channel MOSFET with minimized dopant fluctuation and diffusion levels |
US8617957B1 (en) * | 2012-09-10 | 2013-12-31 | International Business Machines Corporation | Fin bipolar transistors having self-aligned collector and emitter regions |
US20140070328A1 (en) * | 2012-09-12 | 2014-03-13 | Toshiba America Electronic Components, Inc. | Semiconductor device and method of fabricating the same |
US8946035B2 (en) * | 2012-09-27 | 2015-02-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Replacement channels for semiconductor devices and methods for forming the same using dopant concentration boost |
US8633516B1 (en) | 2012-09-28 | 2014-01-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Source/drain stack stressor for semiconductor device |
US8497177B1 (en) | 2012-10-04 | 2013-07-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of making a FinFET device |
US9443962B2 (en) * | 2012-11-09 | 2016-09-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Recessing STI to increase fin height in fin-first process |
US9349837B2 (en) * | 2012-11-09 | 2016-05-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Recessing STI to increase Fin height in Fin-first process |
US9190486B2 (en) * | 2012-11-20 | 2015-11-17 | Globalfoundries Inc. | Integrated circuits and methods for fabricating integrated circuits with reduced parasitic capacitance |
US9299809B2 (en) * | 2012-12-17 | 2016-03-29 | Globalfoundries Inc. | Methods of forming fins for a FinFET device wherein the fins have a high germanium content |
US8815691B2 (en) * | 2012-12-21 | 2014-08-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating a gate all around device |
US9391181B2 (en) * | 2012-12-21 | 2016-07-12 | Intel Corporation | Lattice mismatched hetero-epitaxial film |
US9093530B2 (en) | 2012-12-28 | 2015-07-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin structure of FinFET |
US9224849B2 (en) * | 2012-12-28 | 2015-12-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Transistors with wrapped-around gates and methods for forming the same |
KR102017616B1 (ko) * | 2013-01-02 | 2019-09-03 | 삼성전자주식회사 | 전계 효과 트랜지스터 |
US9006786B2 (en) * | 2013-07-03 | 2015-04-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin structure of semiconductor device |
US8901607B2 (en) * | 2013-01-14 | 2014-12-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and fabricating the same |
US9559181B2 (en) * | 2013-11-26 | 2017-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for FinFET device with buried sige oxide |
US8815693B2 (en) * | 2013-01-23 | 2014-08-26 | International Business Machines Corporation | FinFET device formation |
US8716156B1 (en) * | 2013-02-01 | 2014-05-06 | Globalfoundries Inc. | Methods of forming fins for a FinFET semiconductor device using a mandrel oxidation process |
KR102018101B1 (ko) * | 2013-02-04 | 2019-11-14 | 삼성전자 주식회사 | 반도체 소자 및 이의 제조 방법 |
JP6309299B2 (ja) * | 2013-02-27 | 2018-04-11 | ルネサスエレクトロニクス株式会社 | 圧縮歪みチャネル領域を有する半導体装置及びその製造方法 |
US9362386B2 (en) * | 2013-02-27 | 2016-06-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | FETs and methods for forming the same |
US9159824B2 (en) * | 2013-02-27 | 2015-10-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs with strained well regions |
US9214555B2 (en) | 2013-03-12 | 2015-12-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Barrier layer for FinFET channels |
US8963258B2 (en) | 2013-03-13 | 2015-02-24 | Taiwan Semiconductor Manufacturing Company | FinFET with bottom SiGe layer in source/drain |
KR102038486B1 (ko) * | 2013-04-09 | 2019-10-30 | 삼성전자 주식회사 | 반도체 장치 및 그 제조 방법 |
US8796666B1 (en) | 2013-04-26 | 2014-08-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | MOS devices with strain buffer layer and methods of forming the same |
US9276087B2 (en) * | 2013-05-10 | 2016-03-01 | Samsung Electronics Co., Ltd. | Methods of manufacturing FINFET semiconductor devices using sacrificial gate patterns and selective oxidization of a fin |
US9006842B2 (en) * | 2013-05-30 | 2015-04-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Tuning strain in semiconductor devices |
US9093531B2 (en) * | 2013-06-11 | 2015-07-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin structure of semiconductor device |
US9601381B2 (en) * | 2013-12-05 | 2017-03-21 | Stmicroelectronics (Crolles 2) Sas | Method for the formation of a finFET device with epitaxially grown source-drain regions having a reduced leakage path |
US9431523B2 (en) * | 2014-01-16 | 2016-08-30 | Globalfoundries Inc. | Local thinning of semiconductor fins |
KR102167519B1 (ko) * | 2014-03-21 | 2020-10-19 | 인텔 코포레이션 | Ge-풍부 p-mos 소스/드레인 컨택트들의 집적을 위한 기술들 |
WO2015147784A1 (en) * | 2014-03-24 | 2015-10-01 | Intel Corporation | Fin sculpting and cladding during replacement gate process for transistor channel applications |
CN106030818B (zh) * | 2014-03-27 | 2020-09-01 | 英特尔公司 | 用于基于鳍状物的nmos晶体管的高移动性应变沟道 |
US9443769B2 (en) * | 2014-04-21 | 2016-09-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wrap-around contact |
US9178067B1 (en) * | 2014-04-25 | 2015-11-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for FinFET device |
US9472628B2 (en) * | 2014-07-14 | 2016-10-18 | International Business Machines Corporation | Heterogeneous source drain region and extension region |
US9391201B2 (en) * | 2014-11-25 | 2016-07-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Source/drain structure and manufacturing the same |
US9362405B1 (en) * | 2014-12-04 | 2016-06-07 | Globalfoundries Inc. | Channel cladding last process flow for forming a channel region on a FinFET device |
US9431485B2 (en) * | 2014-12-23 | 2016-08-30 | GlobalFoundries, Inc. | Formation of finFET junction |
US9502567B2 (en) * | 2015-02-13 | 2016-11-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor fin structure with extending gate structure |
US9496338B2 (en) * | 2015-03-17 | 2016-11-15 | International Business Machines Corporation | Wire-last gate-all-around nanowire FET |
-
2015
- 2015-06-03 US US14/730,210 patent/US10269968B2/en active Active
- 2015-11-19 KR KR1020150162378A patent/KR101799646B1/ko active IP Right Grant
- 2015-11-26 TW TW104139362A patent/TWI588907B/zh active
-
2016
- 2016-01-05 CN CN201610004626.9A patent/CN106252231B/zh active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201421693A (zh) * | 2012-11-29 | 2014-06-01 | Taiwan Semiconductor Mfg | FinFET元件與其形成方法 |
CN103855010A (zh) * | 2012-11-30 | 2014-06-11 | 中国科学院微电子研究所 | FinFET及其制造方法 |
CN104576735A (zh) * | 2013-10-16 | 2015-04-29 | 台湾积体电路制造股份有限公司 | 具有掩埋绝缘层的FinFET及其形成方法 |
CN104835844A (zh) * | 2013-11-26 | 2015-08-12 | 三星电子株式会社 | 鳍式场效应晶体管半导体装置及其制造方法 |
CN103915504A (zh) * | 2014-04-04 | 2014-07-09 | 唐棕 | 一种鳍型半导体结构及其成型方法 |
JP2014220532A (ja) * | 2014-08-22 | 2014-11-20 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | 半導体装置の製造方法、及び、半導体装置 |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110517990A (zh) * | 2018-05-21 | 2019-11-29 | 中芯国际集成电路制造(北京)有限公司 | 半导体结构及其形成方法 |
CN110517990B (zh) * | 2018-05-21 | 2021-10-15 | 中芯国际集成电路制造(北京)有限公司 | 半导体结构及其形成方法 |
CN110957224A (zh) * | 2018-09-27 | 2020-04-03 | 台湾积体电路制造股份有限公司 | 半导体器件及其形成方法 |
US11615965B2 (en) | 2018-09-27 | 2023-03-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor FinFET device and method |
CN110957224B (zh) * | 2018-09-27 | 2023-12-19 | 台湾积体电路制造股份有限公司 | 半导体器件及其形成方法 |
CN110970505A (zh) * | 2018-09-28 | 2020-04-07 | 台湾积体电路制造股份有限公司 | 半导体器件及其制造方法 |
CN110970505B (zh) * | 2018-09-28 | 2023-09-12 | 台湾积体电路制造股份有限公司 | 半导体器件及其制造方法 |
CN111128734A (zh) * | 2018-10-31 | 2020-05-08 | 台湾积体电路制造股份有限公司 | 制造半导体器件的方法和半导体器件 |
US11764289B2 (en) | 2018-10-31 | 2023-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing a semiconductor device and a semiconductor device |
CN111128734B (zh) * | 2018-10-31 | 2023-12-19 | 台湾积体电路制造股份有限公司 | 制造半导体器件的方法和半导体器件 |
CN113555317A (zh) * | 2020-07-10 | 2021-10-26 | 台湾积体电路制造股份有限公司 | 制造半导体器件的方法和半导体器件 |
US12015085B2 (en) | 2020-07-10 | 2024-06-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing a semiconductor device including etching polysilicon |
Also Published As
Publication number | Publication date |
---|---|
US10269968B2 (en) | 2019-04-23 |
US20160359043A1 (en) | 2016-12-08 |
TWI588907B (zh) | 2017-06-21 |
CN106252231B (zh) | 2020-04-17 |
TW201643967A (zh) | 2016-12-16 |
KR101799646B1 (ko) | 2017-11-20 |
KR20160142750A (ko) | 2016-12-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN106252231A (zh) | 包括鳍结构的半导体器件及其制造方法 | |
US20200127117A1 (en) | Semiconductor device and manufacturing method thereof | |
US10141307B2 (en) | Semiconductor device and manufacturing method thereof | |
US9882029B2 (en) | Semiconductor device including Fin-FET and manufacturing method thereof | |
US10158007B2 (en) | Semiconductor device and manufacturing method thereof | |
US11239084B2 (en) | Semiconductor device and manufacturing method thereof | |
US11121217B2 (en) | Semiconductor device and manufacturing method thereof | |
US10157998B2 (en) | Semiconductor device and manufacturing method thereof | |
CN105845578A (zh) | 半导体器件及其制造方法 | |
US11075269B2 (en) | Semiconductor device and manufacturing method thereof | |
CN106158617A (zh) | 半导体器件及其制造方法 | |
CN106992154B (zh) | 半导体器件及其制造方法 | |
CN106847813A (zh) | 半导体器件及其制造方法 | |
CN106158967A (zh) | 半导体器件及其制造方法 | |
CN107665825A (zh) | 半导体器件以及PMOS FET的源极/漏极结构和PMOS FinFET的制造方法 | |
KR20210148804A (ko) | 반도체 디바이스를 제조하는 방법 및 반도체 디바이스 | |
CN111129147B (zh) | 制造半导体器件的方法和半导体器件 | |
US9991362B2 (en) | Semiconductor device including tungsten gate and manufacturing method thereof | |
US12020947B2 (en) | Method of manufacturing semiconductor devices and semiconductor devices | |
US20210272951A1 (en) | Semiconductor device and manufacturing method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |