CN108695388A - 半导体元件及其制造方法 - Google Patents
半导体元件及其制造方法 Download PDFInfo
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- CN108695388A CN108695388A CN201710710460.7A CN201710710460A CN108695388A CN 108695388 A CN108695388 A CN 108695388A CN 201710710460 A CN201710710460 A CN 201710710460A CN 108695388 A CN108695388 A CN 108695388A
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Classifications
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- H01L29/772—Field effect transistors
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
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Abstract
一种半导体元件及其制造方法。在一种使用取代栅极技术制造半导体元件的方法中,形成一由多个介电材料部分所构成的栅极空间,一半导体鳍片通道层是暴露于此栅极空间中。这些介电材料部分的多个表面会被形成为疏水的。一第一介电层是形成于此半导体鳍片通道层上,并保持这些介电材料部分的这些表面疏水。此形成的第一介电层的一表面亲水。一第一导电层是形成于此第一介电层上方,并保持这些介电材料部分的这些表面疏水。一第二导电层是形成于此第一导电层上方与这些介电材料部分的这些疏水表面上,以填充此栅极空间。
Description
技术领域
本揭露关于半导体集成电路,且特别是关于一种具有金属栅极结构的半导体元件及其制造方法。
背景技术
当半导体工业追求更高的元件密度、更高的效能以及更低的成本,而进展至纳米科技制程的节点,制造与设计的挑战也随之而来,这样的挑战促使例如鳍式场效晶体管(fin field effect transistor;FinFET)的3D设计的发展。鳍式场效晶体管元件一般包括具有高深宽比(aspect ratio)的半导体鳍片。通道和源极/漏极区是形成在半导体鳍片中。栅极是形成于鳍结构的侧边上并沿着侧边形成(例如,包覆鳍结构)。这样的设计可增加通道与源极/漏极区的表面积,以制造更快速、可靠度更高且控制性更佳的半导体晶体管元件。金属栅极结构连同具有高介电常数的高k栅极介电质,是时常使用在鳍式场效晶体管元件中且是由取代栅极技术制造。
发明内容
根据本揭露的一态样,一种半导体元件包含一鳍式场效晶体管。此鳍式场效晶体管包含一鳍结构、一栅极结构以及多个侧壁间隔物。此鳍结构沿一第一方向延伸,此栅极结构包含一栅极介电层与一栅极电极层。此栅极介电层是设置于此鳍结构上方。此栅极电极层是设置于此栅极介电层上方。此栅极结构沿与此第一方向交叉的一第二方向延伸。这些侧壁间隔物是设置于此栅极结构的相对侧面上,这些侧壁间隔物是由一绝缘材料形成。此栅极电极层接触这些侧壁间隔物,且此栅极电极层与这些侧壁间隔物之间沿此第一方向上无设置此栅极介电层。
根据本揭露的其他态样,一半导体元件包含一第一鳍式场效晶体管与一第二鳍式场效晶体管。此第一鳍式场效晶体管包含一第一鳍结构与一第一栅极结构。此第一鳍结构沿一第一方向延伸。此第一栅极结构包含一第一栅极介电层与一第一栅极电极层。此第一栅极介电层是形成于此第一鳍结构上方。此第一栅极电极层是形成于此第一栅极介电层上方并沿与此第一方向垂直的一第二方向延伸。此第二鳍式场效晶体管包含一第二鳍结构以及一第二栅极结构,此第二鳍结构沿此第一方向延伸,此第二栅极结构包含一第二栅极介电层与一第二栅极电极层,此第二栅极介电层是形成于此第二鳍结构上方,此第二栅极电极层是形成于此第二栅极介电层上方并沿此第二方向延伸,此第一栅极结构与此第二栅极结构是沿此第二方向对齐。此第一栅极结构与此第二栅极结构是由一分离插塞所分隔,此分离插塞是由一绝缘材料形成,此第一栅极电极层接触此分离插塞的一侧壁,此第一栅极电极层与此分离插塞之间不设置此第一栅极介电层,且多个硫原子是设置于此第一栅极电极层与此分离插塞的此侧壁之间的一界面上。
根据本揭露的另一态样,在一种使用取代栅极技术制造半导体元件的方法中,形成一由多个介电材料部分所构成的栅极空间,一半导体鳍片通道层是暴露于此栅极空间中。使这些介电材料部分的多个表面疏水,在此半导体鳍片通道层上形成一第一介电层,并保持这些介电材料部分的这些表面疏水,并保持此形成的第一介电层的一表面亲水,于此第一介电层上方形成一第一导电层,并保持这些介电材料部分的这些表面疏水,以及于此第一导电层上方与这些介电材料部分的这些疏水表面上形成一第二导电层,以填充此栅极空间。
附图说明
阅读以下详细叙述并搭配对应的附图,可了解本揭露的多个样态。需留意的是,附图中的多个特征并未依照该业界领域的标准作法绘制实际比例。事实上,所述的特征的尺寸可以任意的增加或减少以利于讨论的清晰性。
图1A至图1D为根据本揭露的部分实施例的半导体元件的示例图,图1A为示例俯视图,图1B为示例立体图,而图1C与图1D为示例剖面图;
图2为根据本揭露的部分实施例的循序的半导体元件制造过程中,某一阶段的示例剖面图;
图3为根据本揭露的部分实施例的循序的半导体元件制造过程中,某一阶段的示例剖面图;
图4为根据本揭露的部分实施例的循序的半导体元件制造过程中,某一阶段的示例剖面图;
图5A至图5C为根据本揭露的部分实施例的循序的半导体元件制造过程中某一阶段的示例图,图5A为示例剖面图,图5B为示例俯视图,而图5C为示例立体图;
图6A与图6B为根据本揭露的部分实施例的循序的半导体元件制造过程中某一阶段的示例图,图6A为示例剖面图且图6B为示例俯视图;
图7A与图7B为根据本揭露的部分实施例的循序的半导体元件制造过程中某一阶段的示例剖面图,图7A为示例剖面图且图7B为示例俯视图;
图8A与图8B为根据本揭露的部分实施例的循序的半导体元件制造过程中某一阶段的示例剖面图,图8A与图8C为示例剖面图,而图8B为示例俯视图;
图9A与图9B为根据本揭露的部分实施例的循序的半导体元件制造过程中,某一阶段的示例剖面图;
图10A与图10B为根据本揭露的部分实施例的循序的半导体元件制造过程中,某一阶段的示例剖面图;
图11A为自主装单层的示例图;
图11B与图11C显示亲水性界面和疏水界面之间的差异;
图12显示用于自聚集单分子层的化合物的范例;
图13A与图13B为根据本揭露的部分实施例的循序的半导体元件制造过程中,某一阶段的示例剖面图;
图14A与图14B为根据本揭露的部分实施例的循序的半导体元件制造过程中,某一阶段的示例剖面图;以及
图15A与图15B为根据本揭露的部分实施例的循序的半导体元件制造过程中,某一阶段的示例剖面图。
具体实施方式
以下将以附图及详细说明清楚说明本揭露的精神,任何所属技术领域中具有通常知识者在了解本揭露的实施例后,当可由本揭露所教示的技术,加以改变及修饰,其并不脱离本揭露的精神与范围。举例而言,叙述“第一特征形成于第二特征上方或上”,于实施例中将包含第一特征及第二特征具有直接接触;且也将包含第一特征和第二特征为非直接接触,具有额外的特征形成于第一特征和第二特征之间。此外,本揭露在多个范例中将重复使用元件标号以和/或文字。重复的目的在于简化与厘清,而其本身并不会决定多个实施例以和/或所讨论的配置之间的关系。
此外,方位相对词汇,如“在…之下”、“下面”、“下”、“上方”或“上”或类似词汇,在本文中为用来便于描述绘示于附图中的一个元件或特征至另外的元件或特征的关系。方位相对词汇除了用来描述装置在附图中的方位外,其包含装置于使用或操作下的不同的方位。当装置被另外设置(旋转90度或者其他面向的方位),本文所用的方位相对词汇同样可以相应地进行解释。
图1A至图1D显示根据本揭露的部分实施例的半导体元件的示例图。图1A为示例俯视图,图1B为示例立体图,图1C为沿着图1A的X1-X1剖线的示例剖面图且图1D为沿着图1A的Y1-Y1剖线的示例剖面图,图1B相当于图1A中的圈起部分A。
如图1A至图1D所示,例如鳍式场效晶体管的半导体元件包含第一元件区1A与第二元件区1B。第一元件区1A包含一或多个第一鳍式场效晶体管,而第二元件区1B包含一或多个第二鳍式场效晶体管。第一鳍式场效晶体管的通道类型相同或相异于第二鳍式场效晶体管的通道类型。
在部分实施例中,第一元件区1A包含p型金属氧化物半导体场效晶体管,而第二元件区1B包含n型金属氧化物半导体场效晶体管。在其他实施例中,第一与第二元件区包含p型金属氧化物半导体场效晶体管、第一与第二元件区包含n型金属氧化物半导体场效晶体管、或第一与第二元件区皆包含p型与n型金属氧化物半导体场效晶体管两者。
鳍式场效晶体管还包含基材10、鳍结构20、栅极介电层30以及栅极电极40。在部分实施例中,基材10可为硅基材。或者,基材10可包含另一元素半导体(例如锗)、化合物半导体(包括第四族化合物半导体(例如碳化硅(SiC)、硅锗(SiGe))、第三五族化合物半导体(例如砷化镓(GaAs)、磷化镓(GaP)、氮化镓(GaN)、磷化铟(InP)、砷化铟(InAs)、锑化铟(InSb)、磷砷化镓(GaAsP)、氮化铝镓(AlGaN)、砷化铝铟(AlInAs)、砷化铝镓(AlGaAs)、砷化镓铟(GaInAs)、磷化镓铟(GaInP)及/或砷磷化镓铟(GaInAsP)))、或以上的组合。非晶基材(例如非晶硅或非晶碳化硅)或绝缘材料(例如氧化硅)亦可做为基材10使用。基材10可包含已适当地掺有杂质(例如p型或n型电性)的各种区域。
鳍结构20是设置于基材10上方,鳍结构20可由与基材10相同的材料形成且可由基材10连续地延伸。在部分实施例中,鳍结构20是由硅形成。鳍结构20中的硅层可为本征的(intrinsic)或适当地掺有n型杂质或p型杂质。
在图1A至图1C中,两个鳍结构20是分别设置于第一元件区1A中与第二元件区1B中。然而,鳍结构20的数目不限定为二(或四)个而可为一、二、三、五个或更多个。此外,一或多个虚设(dummy)鳍结构可设置在邻近于鳍结构20的两侧,以助于提升图案化制程中的图案保真度(pattern fidelity)。在部分实施例中,鳍结构20的宽度W1为约5纳米至约40纳米,而在某些实施例中则为约7纳米至约15纳米。在部分实施例中,鳍结构20的高度为约100纳米至约300纳米,而在另一些实施例中则为约50纳米至约100纳米。
进一步地,多个鳍结构20之间的空间及/或于基材10上方所形成的一鳍结构与另一元件之间的空间是以包含绝缘材料的隔离绝缘层50(或称之为浅沟槽隔离(shallowtrench isolation;STI)层)填充,且层间介电层70是设置于隔离绝缘层50上方。隔离绝缘层50与层间介电层70的绝缘材料可包含氧化硅、氮化硅、氮氧化硅(SiON)、氮碳氧化硅(SiOCN)、掺杂氟的硅酸盐玻璃(fluorosilicate glass;FSG)或是低k介电材料。隔离绝缘层50与层间介电层70的绝缘材料可相同或相异。
在栅极电极40下方的鳍结构20的底部是称为井层,且鳍结构20的顶部是称为通道层或通道区。在栅极电极40下方,井层是嵌设于隔离绝缘层50,且通道层从隔离绝缘层50突出。通道层的底部亦可嵌设于隔离绝缘层50至约1纳米至5纳米的深度。
在部分实施例中,井层的高度为约60纳米至约100纳米,而通道层的高度为约为40纳米至约60纳米。
从隔离绝缘层50突出的鳍结构20中的通道层是被栅极介电层30覆盖,且栅极介电层30是进一步被栅极电极40覆盖。未被栅极电极40覆盖的部分通道层当作金属氧化物半导体场效晶体管的源极及/或漏极(如图1B)使用。鳍结构20沿第一方向延伸而栅极电极40沿与第一方向垂直的第二方向延伸。
在某些实施例中,栅极介电层30包含界面层230与高k介电层235。举例而言,界面层230是由氧化硅形成。高k介电层235为由一或多层的二氧化铪(HfO2)、氧化硅铪(HfSiO)、氮氧化硅铪(HfSiON)、氧化铪钽(HfTaO)、氧化镧(La2O3)、氧化铪钛(HfTiO)、氧化铪锆(HfZrO)、氧化锆、氧化铝、氧化钛、二氧化铪-氧化铝合金(HfO2-Al2O3)或其他适合的高k介电材料所形成。
栅极电极40包含主要电极层250与一或多个导电底层240。主要电极层250包含以下元素一或多层的铝、铜、钛、钽、钨、钴、钼、镍、以上组合的合金或其他适合的导电材料。
一或多层导电底层240包含一或多个功函数调整层、一或多个阻障层、一或多个粘着层及/或一或多个衬垫层。功函数调整层由一或多层的钛(Ti)、银(Ag)、铝(Al)、氮化钛铝(TiAlN)、碳化钽(TaC)、氮碳化钽(TaCN)、氮化钽硅(TaSiN)、锰(Mn)、锆(Zr)、氮化钛(TiN)、氮化钽(TaN)、铷(Ru)、钼(Mo)、铝(Al)、氮化钨(WN)、铜(Cu)、钨(W)、铼(Re)、铱(Ir)、钴(Co)、镍(Ni)或其他适合的导电材料所形成。在部分实施例中,功函数调整层可包含适于p型通道鳍式场效晶体管(例如于第一元件区1A中)的第一金属材料与适于n型通道鳍式场效晶体管(例如于第二元件区1B中)的第二金属材料。功函数调整层可由原子层沉积(atomiclayer deposition;ALD)、物理气相沉积(physical vapor deposition;PVD)、化学气相沉积(chemical vapor deposition;CVD)、电子束蒸镀(e-beam evaporation)或是其他适合的制程所形成。进一步地,n型通道鳍式场效晶体管中的功函数调整层与p型通道鳍式场效晶体管中的功函数调整层可使用不同的金属层且可分开形成。
一或多个阻障层、粘着层及/或衬垫层包含钛、氮化钛、钽及/或氮化钽。
源极与漏极区亦是形成于未被栅极电极40覆盖的鳍结构中,源极与漏极区可经由于源极与漏极区中适当地掺入杂质及/或经由形成一或多个磊晶层而形成。由硅或锗与金属(例如钴、镍、钨、钛或钽)组成的合金可形成于源极与漏极区上。
进一步地,多个侧壁绝缘层80是设置于栅极电极40的相对侧面上。栅极电极40与源极/漏极区被层间介电层70覆盖,且必要的线路及/或导通孔/接触孔是设置于半导体元件中以完成半导体元件。
在部分实施例中,栅极电极40的宽度W2为约20纳米至约40纳米。在部分实施例中,当多个栅极电极40沿宽度方向排列(如图1B),多个栅极电极40之间距为约60纳米至约100纳米。
如图1A至图1C所示,相邻多个栅极电极40是以由绝缘材料所形成的分离插塞200彼此分隔。在部分实施例中,分离插塞200具有顶部尺寸(宽度)小于底部尺寸(宽度)的锥形形状。在其他实施例中,分离插塞200具有顶部尺寸(宽度)大于底部尺寸(宽度)的倒锥形形状。
在某些实施例中,分离插塞200顶部的宽度W3小于约20纳米且在部分实施例中可为约5纳米至约15纳米。在某些实施例中,分离插塞200底部的宽度W4小于约35纳米且在部分实施例中可为约10纳米至约30纳米。在部分实施例中,分离插塞200的顶部对应栅极电极40的顶面,而分离插塞200的底部对应栅极介电层30的底部或是隔离绝缘层50与层间介电层70之间的界面,分离插塞200的绝缘材料可包含氧化硅、氮化硅、氮氧化硅(SiON)、氮碳氧化硅(SiOCN)、掺杂氟的硅酸盐玻璃(FSG)或低k介电材料,且分离插塞200的绝缘材料与隔离绝缘层50及/或层间介电层70的绝缘材料的材料可相同或相异。在部分实施例中,分离插塞200是由以氮化硅为基础的材料形成,例如氮化硅、氮氧化硅、氮碳化硅或氮碳氧化硅。
如图1C与图1D所示,硫、氮-氢键(N-H)、碳-氢键(C-H)以及硅原子(非构成分离插塞200的硅原子)的至少一者是设置于主要电极层250与分离插塞200之间的界面(如图1C)及/或主要电极层250与侧壁间隔物80之间的界面(如图1D),以做为自聚集单分子层(self-assembled monolayer;SAM)残余物225。
图2至图10B与图13A至图15B为根据本揭露的部分实施例来显示制造鳍式场效晶体管的示例循序过程。可理解的是,在本方法的其他实施例中,于图2至图10B与图13A至图15B所绘示的制程之前、之中、之后可有其他的步骤,而一些下述的步骤则可被取代或移除。步骤/制程的顺序可能可以互换。
遮罩层是形成于基材10(例如半导体晶圆)上方,以制造鳍结构。举例而言,遮罩层是以热氧化(thermal oxidation)制程及/或化学气相沉积制程形成。举例而言,基材为杂质浓度在约1x1015cm-3至约5x1015cm-3的p型硅基材。在其他实施例中,基材10为杂质浓度在约1x1015cm-3至约5x1015cm-3的n型硅基材。基材10可包含已适当地掺有杂质(例如p型或n型电性)的各种区域。
在部分实施例中,举例而言,遮罩层包含氧化物(例如氧化硅)垫层与氮化硅遮罩层。氧化物垫层可通过使用热氧化或化学气相沉积制程形成。氮化硅遮罩层可通过物理气相沉积(例如溅镀法(sputtering method))、化学气相沉积、等离子辅助化学气相沉积(plasma-enhanced chemical vapor deposition;PECVD)、大气压力化学气相沉积(atmospheric pressure chemical vapor deposition;APCVD)、低压化学气相沉积(low-pressure chemical vapor deposition;LPCVD)、高密度等离子化学气相沉积(highdensity plasma chemical vapor deposition;HDPCVD)、原子层沉积、及/或其他制程所形成。
在部分实施例中,氧化物垫层的厚度为约2纳米至约15纳米,而氮化硅遮罩层的厚度为约2纳米至约50纳米。遮罩图案进一步地形成于遮罩层上方。举例而言,遮罩图案为通过光微影形成的光阻图案。
如图2所示,氧化物垫层106与氮化硅遮罩层107两者所形成的硬遮罩图案100是通过使用遮罩图案做为蚀刻遮罩而形成。
通过使用硬遮罩图案做为蚀刻遮罩,基材10是通过使用干式蚀刻(dryetching)法及/或湿式蚀刻(wet etching)法的沟渠蚀刻(trench etching)而被图案化成鳍结构20。
在部分实施例中,基材10上方设置的鳍结构20可由与基材10相同的材料所形成且连续地从基材10延伸。鳍结构20可为本征半导体或适当地掺有n型杂质或p型杂质。
在图2中,四个鳍结构20被设置并用于p型鳍式场效晶体管及/或n型鳍式场效晶体管。鳍结构的数目不限定为四个而可为至少一个或多于四个。除此之外,一或多个虚设鳍结构可设置于邻近于鳍结构20的两侧,以在图案化制程中提升图案保真度。在部分实施例中,鳍结构20的宽度W1为约5纳米至约40纳米,且在某些实施例中为约7纳米至约20纳米。在部分实施例中,鳍结构20的高度H1为约100纳米至约300纳米,且在另一些实施例中为约50纳米至约100纳米。当鳍结构20的高度不均匀时,可由鳍结构20的平均高度所对应的平面而测得从基材10起的高度。
如图3所示,形成隔离绝缘层的绝缘材料层50是形成于基材10上方,以完全覆盖鳍结构20。
举例而言,隔离绝缘层50的绝缘材料是以通过低压化学气相沉积、等离子化学气相沉积或可流动式化学气相沉积(flowable chemical vapor deposition)所形成的二氧化硅所形成。于可流动式化学气相沉积中,可流动介电材料会被沉积,而非氧化硅。正如其名,可流动介电材料在沉积过程中可“流动”,以填满具有高深宽比的空隙或空间。一般而言,各种化学物质可添加在含硅先驱物中,以使沉积的薄膜流动。在部分实施例中,氮-氢键可被添加。可流动介电先驱物,特别是可流动氧化硅先驱物的例子包含硅酸盐、硅氧烷、甲基倍半硅氧烷(methyl silsesquioxane;MSQ)、氢倍半硅氧烷(hydrogen silsesquioxane;HSQ)、甲基倍半硅氧烷与氢倍半硅氧烷的混合物(MSQ/HSQ)、全氢硅氮烷(perhydrosilazane;TCPS)、全氢化聚硅氮烷(perhydro-polysilazane;PSZ)、四乙氧基硅烷(tetraethyl orthosilicate;TEOS)或如三硅烷基胺(trisilylamine;TSA)的硅烷基胺(silyl-amine)。这些可流动氧化硅材料是形成于多重操作制程中。在可流动薄膜沉积后,先进行固化再进行退火将不想要的元素移除,以形成氧化硅。当不想要的元素被移除,可流动薄膜致密化并收缩。在部分实施例中,执行多重退火制程。可流动薄膜是经过大于一次的固化及退火。隔离绝缘层50可为旋转涂布玻璃(spin on glass;SOG)、氧化硅(SiO)、氮氧化硅(SiON)、氮碳氧化硅(SiOCN)或掺杂氟的硅酸盐玻璃(FSG)。隔离绝缘层50可掺有硼及/或磷。
在隔离绝缘层50形成后,进行平坦化步骤以移除隔离绝缘层50顶部与包含氧化物垫层106与氮化硅遮罩层107的遮罩层100。然后,如图4所示,将隔离绝缘层50进一步地移除,因此,鳍结构20顶部是暴露且成为通道区。
将隔离绝缘层50形成后,可选择性地进行例如退火制程的热制程,以提升隔离绝缘层50的品质。在某些实施例中,热制程是通过使用快速热退火(rapid thermalannealing;RTA)进行,此快速热退火为在惰性气体环境中于温度范围介于约900℃至约1050℃之间进行约1.5秒至约10秒,举例而言,惰性气体可为氮气(N2)、氩气(Ar)或氦气(He)气体。
在鳍结构20的顶部从隔离绝缘层50暴露后,虚设栅极绝缘层105于与多晶硅层形成于隔离绝缘层50上方与暴露出的鳍结构20上方。接着,如图5A至图5C所示,进行图案化步骤,以得到由多晶硅所形成的虚设栅极层110。虚设栅极绝缘层105可为通过化学气相沉积、物理气相沉积、原子层沉积、电子束蒸镀或是其他适合的制程所形成的氧化硅。在部分实施例中,多晶硅层的厚度为约5纳米至约100纳米。在此实施例所描述的取代栅极技术中,虚设栅极绝缘层105与虚设栅极层110被实质移除。
将多晶硅层图案化后,侧壁绝缘层80(侧壁间隔物)亦形成于栅极层110的两侧面上。侧壁绝缘层80是由一或多层由氧化硅或氮化硅为基础的材料形成,例如氮化硅(SiN)、氮碳化硅(SiCN)、氮氧化硅(SiON)或氮碳氧化硅(SiOCN)。在部分实施例中,氮化硅是用于侧壁绝缘层80。
在部分实施例中,在侧壁绝缘层80形成后,做为接触蚀刻停止层(contact-etchstop layer;CESL)的绝缘层72是形成于多晶硅层110上方与侧壁绝缘层80上方。接触蚀刻停止层72可为一或多层由氧化硅或氮化硅为基础的材料例如氮化硅(SiN)、氮碳化硅(SiCN)、氮氧化硅(SiON)或氮碳氧化硅(SiOCN)所形成。在部分实施例中,氮化硅是用于接触蚀刻停止层。
进一步地,层间介电层70(interlayer dielectric layer;ILD)是形成于具有侧壁绝缘层80的多个栅极层110之间的空间中的接触蚀刻停止层72上与栅极层110上方。层间介电层70可包含氧化硅、氮化硅、氮氧化硅(SiON)、氮碳氧化硅(SiOCN)、掺杂氟的硅酸盐玻璃(FSG)或是低k介电材料且可通过化学气相沉积或其他适合的制程所形成。隔离绝缘层50的绝缘材料可相同或相异于层间介电层70的绝缘材料。
进行平坦化步骤例如回蚀刻制程及/或化学机械研磨(chemical mechanicalpolishing;CMP)制程,以得到图5A至图5C中的结构。
图5B与图5C分别为在虚设栅极层110与层间介电层70形成之后的鳍式场效晶体管元件的俯视图(上视图)与立体图。图2至图4与图5A相当于图5B中沿剖线X1-X1的横截面。图5C相当于图5B中的圈起部分B。
如图5B及图5C所示,多个虚设栅极层110是以固定之间距间隔性地排列,并沿一方向(X方向)延伸。多个虚设栅极层110可沿不同方向间隔性的排列,并沿与X方向垂直的另一方向(Y方向)延伸。
虚设栅极层110覆盖与具有鳍结构20的鳍式场效晶体管的通道区。也就是说,虚设栅极层110是形成于通道区上方。未被栅极层覆盖的鳍结构20将通过适当的源极/漏极制造步骤而成为源极/漏极区。
接着,如图6A与图6B所示,在以平坦化步骤使栅极层110的顶面暴露后,虚设栅极层110与虚设栅极绝缘层105(例如虚设层)是通过图案化处理例如微影处理与蚀刻处理而分割,因此形成分割的虚设栅极层110A与分割的虚设栅极层110B。在部分实施例中,硬遮罩是用在虚设栅极电极层的蚀刻处理中,且硬遮罩可留在第一与第二分割的虚设栅极电极层的顶部。如图6A与图6B所示,开口115是形成于第一与第二分割的虚设栅极层110A与110B之间。
接着,如图7A与图7B所示,分离插塞200是形成于开口115中。分离插塞200的形成是通过化学气相沉积或原子层沉积以将绝缘材料的毯覆层(blanket layer)形成于开口115中、虚设栅极电极层110A、110B上方与层间介电层70上方,然后进行平坦化步骤例如化学机械研磨。如图7A与图7B所示,化学机械研磨可被执行以使虚设栅极电极层110A、110B的顶面暴露,分离插塞200是通过此平坦化步骤而形成。举例而言,分离插塞200是由氧化硅或氮化硅为基础的材料例如氮化硅(SiN)、氮氧化硅(SiON)、氮碳化硅(SiCN)、氮碳氧化硅(SiOCN)或任何其他适合的介电材料所形成。
接着,如图8A至图8C所示,虚设栅极电极层110A、110B与虚设栅极绝缘层105是通过使用干式蚀刻及/或湿式蚀刻而被移除,因此使栅极空间210形成。通道层20(鳍结构的顶部)是通过将虚设栅极绝缘层105移除而暴露于栅极空间210中。
栅极空间210是由包含分离插塞200、侧壁间隔物80与隔离绝缘层50的介电材料部分所构成或围绕。
在其他实施例中,在虚设栅极电极110形成之后,虚设栅极电极层110是被分割为第一与第二虚设栅极电极层110A、110B,然后,侧壁间隔物80与层间介电层70是形成。在这样的实施例中,分离插塞是由部分侧壁间隔物与层间介电层所形成。进一步地,栅极空间210是由包含侧壁间隔物80与隔离绝缘层50的介电材料部分所构成或围绕。
图9A至图10B与图13A至图15B中,符号“A”相当于图8C的区域D,且符号“B”相当于图8A的区域C。
图9A与图9B显示将虚设栅极绝缘层105移除后的示例剖面图。在部分实施例中,虚设栅极绝缘层105是通过使用稀释氢氟酸(HF)或缓冲氢氟酸而被移除。氢氟酸蚀刻使得通道(鳍)表面带有氢键端而疏水,而介电部分(例如二氧化硅(SiO2)、氮化硅(SiN))的表面维持带有氢氧键(OH-)端而亲水。
如图11B所示,亲水性表面或亲水性的意思是指水珠在表面上的接触角(contactangle)θ1小于90度。而如图11C所示,疏水性表面或疏水性的意思是指水珠在表面上的接触角θ2等于或大于90度(且小于180度)。
接着,如图10A与图10B所示,自聚集单分子层220形成于包含分离插塞200、侧壁间隔物80以及隔离绝缘层50的介电材料部分的表面上,因此将亲水性表面转变成疏水性表面。
自聚集单分子层220是由以下所形成:以硅烷为基础的化合物(例如:苯基乙基三氯硅烷(phenylethyltrichlorosilane;PETS)、硫醇基丙基三甲氧基硅烷(mercaptopropyltrimethoxysilane;MPTMS)、全氟十二烷基三氯硅烷(perfluorodecyltrichlorosilane;FDTS)、氨基丙基三甲氧基硅烷(aminopropyltrimethoxysilane;AMPTS)、十一烷基三氯硅烷(undecyltrichlorosilane;UTS)、氨丙基三乙氧基硅烷(aminopropyltriethoxysilane;APTES)、氨基乙基氨基丙基三甲氧基硅烷(aminoethylaminopropyltrimethoxysilane;EDA)或(氨基乙基氨基甲基)苯乙基三甲氧基甲硅烷(aminoethylaminomethylphenethyltrimethoxysilane;PEDA))、以硫醇为基础的化合物(例如:2-甲基-1-丙硫醇(methylpropanethiol;MPT)、十八硫醇(octadecanethiol;ODT)、1-十六烷硫醇(hexadecanethiol;HDT)、1-十一硫醇(undecanethiol;UDT)或十二硫醇(dodecanethiol;DDT))、以酸为基础的化合物(例如:16-巯基十六烷基酸(mercaptohexadecanoic acid;MHDA)或11-巯基十一烷酸(mercaptoundecanoic acid;MUDA)、以胺为基础的化合物(例如:半胱胺(cysteamine;CYS)、二乙烯三胺基丙基三甲氧基硅烷(trimethoxysilylpropyldiethylenetriamine;DETA)或三甲基硅烷基二乙胺(tetramethylsilyldiethylamine;TMSDMA))以及其他化合物(例如11-巯基-1-十一醇(mercaptoundecanol;MUDO)或六甲基二硅氮烷(hexamethyldisilazane;HMDS)),这些材料的结构式显示于图12。
图11A显示以硫醇为基础的自聚集单分子层的示例结构。头基包含硫且附着于介电层的表面,而尾基具有甲基(CH3)端的烷链。
自聚集单分子层220可通过湿式制程或干式制程所形成。在湿式制程中,将待处理的基材浸入自聚集单分子层溶液,自聚集单分子层溶液中的自聚集单分子层化合物由水、醇类(例如:异丙醇(isopropyl alcohol;IPA)、乙醇(ethanol)或甲醇(methanol))或其他有机溶剂(例如:二甲基亚砜(dimethyl sulfoxide;DMSO)、二甲基甲酰胺(dimethylformamide)或碳酸丙烯酯(propylene carbonate;PC))所稀释。在部分实施例中,自聚集单分子层化合物和稀释溶液的重量比率为1:0(无稀释)至1:10000。在部分实施例中,溶液的温度为约室温(25℃)至约120℃。酸碱值(pH value)可通过添加酸类(例如:盐酸、氢氟酸或柠檬酸)及/或碱类(例如:氨水、四甲基氢氧化铵(tetramethylammonium;TMAH)来调整。在部分实施例中,自聚集单分子层溶液的酸碱值为约6.0至约8.0。在干式制程中,汽化的自聚集单分子层材料是于真空腔体中供应给在待处理的基材。在部分实施例中,制程温度介于约室温(25℃)至约400℃之间。携载气体可采用如氮气、氩气、氦气及/或氢气等气体。所形成的自聚集单分子层220的厚度介于约0.2纳米至约1纳米之间,此厚度可取决于自聚集单分子层的材料。
如图10A与图10B所示,自聚集单分子层220是选择性地形成于介电/绝缘材料层(分离插塞200、侧壁间隔物80以及隔离绝缘层50)的表面。
在形成自聚集单分子层220后,包含通道层20的栅极空间210的内表面会完全疏水。
接着,如图13A与图13B所示,界面层230是形成于通道层20的表面上。界面层230是通过湿式化学氧化所形成,湿式化学氧化使用包含硫酸(sulfuricacid;H2SO4)与过氧化氢(hydrogen peroxide;H2O2)(SPM)以及臭氧水的水性溶液、包含氨水与过氧化氢的水性溶液(SC1)或包含盐酸与过氧化氢的水性溶液(SC2)。表面亲水的薄二氧化硅界面层230是通过湿式化学氧化形成且具有厚度范围介于约0.2纳米至约2纳米。湿式化学氧化过程中,自聚集单分子层220是稳定地保留。
在其他实施例中,通道层20的表面可通过使用双氧水蒸汽而调整为具亲水性而毋须通过形成二氧化硅界面层230来调整为具亲水性。
一旦形成亲水性表面(二氧化硅界面层230),随后形成的层可通过使用原子层沉积而实质上选择性地形成于亲水性表面上。在部分实施例中,层是通过调整原子层沉积的制程温度而选择性地只设置于亲水性表面上。
如图14A与图14B所示,在界面层230形成后,具有厚度为约1纳米至约20纳米的高k介电层235是选择性地形成于界面层230上。高k介电层235实质上不形成于侧壁间隔物80的侧面上(除了高k介电层235的侧端面之外),也实质上不形成于分离插塞200的表面上。因此,高k介电层235具有实质上均匀的厚度(与平均厚度的误差在±0.5纳米之内)且不具有沿Y方向的U形横截面。
在此,U型横截面具有厚的端部与薄的中央部。如果侧壁间隔物80的表面具亲水性而非疏水性,高k介电层235会共形地形成不仅于界面层230上且于侧壁间隔物80上(层间介电层70的顶部)而形成U型。U型横截面会使栅极空间210更小。然而,在本实施例中,因高k介电层235是实质上不形成于侧壁间隔物80的侧面上,栅极空间210的尺寸的缩小可被最小化。同样地,因高k介电层235是实质上不形成于分离插塞200的表面上,栅极空间210沿X方向的尺寸的缩小可被最小化。进一步来说,分离插塞200与最靠近分离插塞200的通道20之间的距离的缩小可被最小化。
接着,一或多个导电底层240是通过原子层沉积形成于高k介电层235上。高k介电层235是由金属氧化物形成,所以高k介电层235的表面亦为亲水性。因此,一或多个导电底层240是可选择性地形成于高k介电层235上而不形成于疏水性的侧壁间隔物80上(除了一或多个导电底层240的侧端面)与分离插塞200的疏水性表面。
在部分实施例中,导电底层240包含第一导电层242、第二导电层244、第三导电层246以及第四导电层248。各个一或多个导电底层240具有实质上均匀的厚度(与平均厚度的误差在±0.5纳米之内)且不具有沿Y方向的U型横截面。在部分实施例中,第一导电层242是由氮化钛形成的阻障层,第二导电层244是由钛形成的粘着层,第三导电层246为功函数调整层,而第四导电层248为后续所形成的主要电极层250的粘着层,导电底层240的数目不限定于四个且最小可为一个或大于四个。
进一步地,如图14B所示,无任何高k介电层235与导电底层240是形成于分离插塞200的疏水性表面上。
接下来,如图15A与图15B所示,主要电极层250是形成于一或多个导电底层240上。主要电极层250可通过适合的薄膜形成法例如化学气相沉积、物理气相沉积、原子层沉积或电镀而形成。接着进行平坦化步骤例如化学机械研磨。
在部分实施例中,将主要电极层250形成前,将自聚集单分子层220移除。自聚集单分子层220可通过加热基材至约400℃至600℃或通过等离子处理而被移除。在部分实施例中,自聚集单分子层220是被全部移除。在其他实施例中,自聚集单分子层220的残余物225留下。在某些实施例中,自聚集单分子层220的头部留下成为自聚集单分子层的残余物225。自聚集单分子层的残余物225可包含以下至少一者:硫、氮氢键化合物、碳氢键化合物以及Si原子,且自聚集单分子层的残余物225是设置于主要电极层250与侧壁间隔物80之间的界面及/或主要电极层250与分离插塞200之间的界面。
如图15B所示,无任何高k介电层235与一或多个导电底层240是形成于分离插塞200的表面,因此,主要电极层250直接接触隔离绝缘层50的表面于分离插塞200与最靠近分离插塞200的通道20之间的区域中以及在两相邻通道20之间的区域中(如图1C)。
若侧壁间隔物80的表面具亲水性而非疏水性,一或多个导电底层240会共形地形成于不仅是高k介电层235(且与之前刚形成的导电层)上而且形成于侧壁间隔物80(且与层间介电层70的顶部)上而形成U型。U型横截面会使栅极空间210变小。然而,在本实施例中,因无任何一或多个导电底层240是形成于侧壁间隔物80的侧面上,栅极空间210的尺寸的缩小可被最小化。同样地,因无任何一或多个导电底层240是形成于分离插塞200的表面,栅极空间210沿X方向的尺寸的缩小可被最小化,进一步来说,分离插塞200与最靠近分离插塞200的通道20之间的距离的缩小可被最小化。
可理解的是,图15A与图15B所示的结构通过进一步进行互补式金属氧化物半导体(CMOS)制程以形成各种特征(例如:互连导通孔、互连金属层与钝化层等)。
此处所描述的各种实施例或例子提供数个相较于先前技术的优点。在上述实施例中,通过使用自聚集单分子层,形成于其上的后续层的表面的疏水性获得控制。可通过使介电部分的表面疏水,实质上使得后续层形成在疏水表面之上。通过这样的技术,栅极空间的尺寸的缩小可因而最小化。因此,体积更大的主要电极层可被填充于栅极空间中,使栅极电极的电阻降低。进一步地,分离插塞与邻近于分离插塞的通道层之间的距离可被降低。可理解的是,并非所有优点都必要在此讨论,并非全部的实施例或例子毋都需要特定的优点,其他实施例或例子可能提供不同优点。
于部分实施方式中,一种半导体元件包含一鳍式场效晶体管,此鳍式场效晶体管包含一鳍结构、一栅极结构以及多个侧壁间隔物。此鳍结构沿一第一方向延伸。此栅极结构包含一栅极介电层与一栅极电极层,此栅极介电层是设置于此鳍结构上方,此栅极电极层是设置于此栅极介电层上方,此栅极结构沿与此第一方向交叉的一第二方向延伸,
这些侧壁间隔物是设置于此栅极结构的相对侧面上,这些侧壁间隔物是由一绝缘材料形成,此栅极电极层接触这些侧壁间隔物,且此栅极电极层与这些侧壁间隔物之间沿此第一方向上无设置此栅极介电层。
于部分实施方式中,硫、氮-氢键、碳-氢键以及硅原子的至少一者是设置于此栅极电极层与这些侧壁间隔物之间的一界面。
于部分实施方式中,多个硫原子是设置于此栅极电极层与这些侧壁间隔物之间的此界面。
于部分实施方式中,此栅极电极层包含一或多个底层与一主要金属电极层,且此主要金属电极层接触这些侧壁间隔物,且此主要金属电极层与这些侧壁间隔物之间无设置此一或多个底层与此栅极介电层。
于部分实施方式中,此一或多个底层不具有一U型横截面,此U型横截面具有沿此第一方向的一中央部与比此中央部厚的多个端部。
于部分实施方式中,此一或多个底层具有一实质上均匀的厚度于此鳍结构上方。
于部分实施方式中,此主要金属电极层包含钨(W)、钴(Co)、镍(Ni)、铝(Al)及铜(Cu)的至少一层,且此一或多个底层包含钛(Ti)、氮化钛(TiN)、氮化钽(TaN)以及氮硅化钛(TiSiN)的至少一层。
于部分实施方式中,此栅极介电层包含一界面层与一高k介电层,此界面层是设置于此鳍结构上,此高k介电层是设置于此界面层上。
于部分实施方式中,此高k介电层包含二氧化铪(HfO2)、氧化锆(ZrO2)、氧化铝(Al2O3)以及氧化镧(La2O3)的至少一层。
于部分实施方式中,一种半导体元件包含一第一鳍式场效晶体管以及一第二鳍式场效晶体管,此第一鳍式场效晶体管包含一第一鳍结构以及一第一栅极结构,此第一鳍结构沿一第一方向延伸,此第一栅极结构包含一第一栅极介电层与一第一栅极电极层,此第一栅极介电层是形成于此第一鳍结构上方,此第一栅极电极层是形成于此第一栅极介电层上方并沿与此第一方向垂直的一第二方向延伸。此第二鳍式场效晶体管包含一第二鳍结构以及一第二栅极结构,此第二鳍结构沿此第一方向延伸,此第二栅极结构包含一第二栅极介电层与一第二栅极电极层,此第二栅极介电层是形成于此第二鳍结构上方,此第二栅极电极层是形成于此第二栅极介电层上方并沿此第二方向延伸,其中此第一栅极结构与此第二栅极结构是沿此第二方向对齐。此第一栅极结构与此第二栅极结构是由一分离插塞所分隔,此分离插塞是由一绝缘材料形成。此第一栅极电极层接触此分离插塞的一侧壁,此第一栅极电极层与此分离插塞之间不设置此第一栅极介电层,且多个硫原子是设置于此第一栅极电极层与此分离插塞的此侧壁之间的一界面上。
于部分实施方式中,此第一栅极电极层包含一或多个底层与一主要金属电极层,此主要金属电极层接触此分离插塞的此侧壁,且无任何此一或多个底层接触此分离插塞的此侧壁。
于部分实施方式中,半导体元件还包含一隔离绝缘层,此第一及此第二鳍结构的多个底部嵌设于此隔离绝缘层,其中在此第一鳍结构与此分离插塞之间,此第一栅极电极层直接接触此隔离绝缘层的一表面。
于部分实施方式中,此第一栅极介电层与此第二栅极介电层不设置于此分离插塞的此侧壁上。
于部分实施方式中,此第一栅极介电层包含一界面层与一高k介电层,此界面层是设置于此第一鳍结构上,此高k介电层是设置于此界面层上,且此高k介电层不设置于此分离插塞的此侧壁上。
于部分实施方式中,此分离插塞是由以一氮化硅为基础的材料所形成。
于部分实施方式中,一种使用取代栅极技术制造半导体元件的方法,此方法包含形成一由多个介电材料部分所构成的栅极空间,其中一半导体鳍片通道层是暴露于此栅极空间中,使这些介电材料部分的多个表面疏水,在此半导体鳍片通道层上形成一第一介电层,并保持这些介电材料部分的这些表面疏水,并保持此形成的第一介电层的一表面亲水,于此第一介电层上方形成一第一导电层,并保持这些介电材料部分的这些表面疏水,以及于此第一导电层上方与这些介电材料部分的这些疏水表面上形成一第二导电层,以填充此栅极空间。
于部分实施方式中,这些介电材料部分的这些表面通过于这些介电材料部分的这些表面上方形成一自聚集单分子层而具疏水性。
于部分实施方式中,此自组装介电单层包含以下的一或多者:苯基乙基三氯硅烷、(3-巯基丙基)三甲氧基硅烷、全氟十二烷基三氯硅烷、(3-氨基丙基)三乙氧基硅烷、十一烷基三氯硅烷、甲基丙硫醇、十八硫醇、十六烷硫醇、16-巯基十六烷基酸、11-巯基十一烷酸、十一硫醇、11-巯基十一醇、半胱胺、十二烷基硫醇、三甲氧基硅烷、氨乙基氨丙基三甲氧基硅烷、二乙烯三胺基丙基三甲氧基硅烷、(氨基乙基氨基甲基)苯乙基三甲氧基甲硅烷、三甲基硅烷基二乙胺、以及六甲基二硅氮烷。
于部分实施方式中,此自聚集单分子层的多个残留原子或分子存在于此第二导电层与这些介电材料部分的这些表面的至少一部分之间。
于部分实施方式中,此方法还包含将此第一导电层形成之前,于此第一介电层上形成一第二介电层,其中此第一导电层包含一或多个导电底层,且此第二介电层、此一或多个导电底层以及此第二导电层的至少一层是通过一原子层沉积法形成,以在一亲水表面上选择性地形成此至少一层。
以上概述数个实施例或例子的特征,使所属领域中具有通常知识者可以从各个方面更加了解本揭露。本技术领域中具有通常知识者应可理解,且可轻易地以本揭露为基础来设计或修饰其他制程及结构,并以此达到相同的目的及/或达到在此介绍的实施例或例子相同的优点。本技术领域中具有通常知识者也应了解这些相等的结构并未悖离本揭露的揭露精神与范围。在不悖离本揭露的精神与范围的前提下,可对本揭露进行各种改变、置换或修改。
Claims (10)
1.一种半导体元件,其特征在于,包含一鳍式场效晶体管,该鳍式场效晶体管包含:
一鳍结构,沿一第一方向延伸;
一栅极结构,包含一栅极介电层与一栅极电极层,该栅极介电层是设置于该鳍结构上方,该栅极电极层是设置于该栅极介电层上方,该栅极结构沿与该第一方向交叉的一第二方向延伸;以及
多个侧壁间隔物,设置于该栅极结构的相对侧面上,所述多个侧壁间隔物是由一绝缘材料形成,该栅极电极层接触所述多个侧壁间隔物,且该栅极电极层与所述多个侧壁间隔物之间沿该第一方向上无设置该栅极介电层。
2.根据权利要求1所述的半导体元件,其特征在于,硫、氮-氢键、碳-氢键以及硅原子的至少一者是设置于该栅极电极层与所述多个侧壁间隔物之间的一界面。
3.根据权利要求1所述的半导体元件,其特征在于,多个硫原子是设置于该栅极电极层与所述多个侧壁间隔物之间的该界面。
4.一种半导体元件,其特征在于,包含:
一第一鳍式场效晶体管,包含一第一鳍结构以及一第一栅极结构,该第一鳍结构沿一第一方向延伸,该第一栅极结构包含一第一栅极介电层与一第一栅极电极层,该第一栅极介电层是形成于该第一鳍结构上方,该第一栅极电极层是形成于该第一栅极介电层上方并沿与该第一方向垂直的一第二方向延伸;以及
一第二鳍式场效晶体管,包含一第二鳍结构以及一第二栅极结构,该第二鳍结构沿该第一方向延伸,该第二栅极结构包含一第二栅极介电层与一第二栅极电极层,该第二栅极介电层是形成于该第二鳍结构上方,该第二栅极电极层是形成于该第二栅极介电层上方并沿该第二方向延伸,其中:
该第一栅极结构与该第二栅极结构是沿该第二方向对齐,
该第一栅极结构与该第二栅极结构是由一分离插塞所分隔,该分离插塞是由一绝缘材料形成,
该第一栅极电极层接触该分离插塞的一侧壁,该第一栅极电极层与该分离插塞之间不设置该第一栅极介电层,且多个硫原子是设置于该第一栅极电极层与该分离插塞的该侧壁之间的一界面上。
5.根据权利要求4所述的半导体元件,其特征在于,该第一栅极电极层包含一或多个底层与一主要金属电极层,该主要金属电极层接触该分离插塞的该侧壁,且无任何该一或多个底层接触该分离插塞的该侧壁。
6.根据权利要求5所述的半导体元件,其特征在于,还包含:
一隔离绝缘层,该第一鳍结构及该第二鳍结构的多个底部嵌设于该隔离绝缘层,其中在该第一鳍结构与该分离插塞之间,该第一栅极电极层直接接触该隔离绝缘层的一表面。
7.一种使用取代栅极技术制造半导体元件的方法,其特征在于,该方法包含:
形成一由多个介电材料部分所构成的栅极空间,其中一半导体鳍片通道层是暴露于该栅极空间中;
使所述多个介电材料部分的多个表面疏水;
在该半导体鳍片通道层上形成一第一介电层,并保持所述多个介电材料部分的所述多个表面疏水,并保持形成的该第一介电层的一表面亲水;
于该第一介电层上方形成一第一导电层,并保持所述多个介电材料部分的所述多个表面疏水;以及
于该第一导电层上方与所述多个介电材料部分的所述多个疏水表面上形成一第二导电层,以填充该栅极空间。
8.根据权利要求7所述的方法,其特征在于,所述多个介电材料部分的所述多个表面通过于所述多个介电材料部分的所述多个表面上方形成一自聚集单分子层而具疏水性。
9.根据权利要求8所述的方法,其特征在于,该自聚集单分子层的多个残留原子或分子存在于该第二导电层与所述多个介电材料部分的所述多个表面的至少一部分之间。
10.根据权利要求8所述的方法,其特征在于,还包含:
将该第一导电层形成之前,于该第一介电层上形成一第二介电层,其中该第一导电层包含一或多个导电底层,且该第二介电层、该一或多个导电底层以及该第二导电层的至少一层是通过一原子层沉积法形成,以在一亲水表面上选择性地形成该至少一层。
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