CN110660855A - 集成电路装置 - Google Patents

集成电路装置 Download PDF

Info

Publication number
CN110660855A
CN110660855A CN201910208312.4A CN201910208312A CN110660855A CN 110660855 A CN110660855 A CN 110660855A CN 201910208312 A CN201910208312 A CN 201910208312A CN 110660855 A CN110660855 A CN 110660855A
Authority
CN
China
Prior art keywords
layer
gate
liner
semiconductor
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201910208312.4A
Other languages
English (en)
Inventor
吴旭升
刘昌淼
尚慧玲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN110660855A publication Critical patent/CN110660855A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

本公开实施例提供一种集成电路装置，包含：一基板；一鳍片，延伸自所述基板；一栅极，设置于所述鳍片上且具有朝向所述鳍片设置的一底部分和设置于所述底部分上的一顶部分；以及一衬层，设置于所述栅极的底部分的一侧表面上，使得所述栅极的顶部分没有衬层。

Description

集成电路装置
技术领域
本公开实施例涉及半导体制造技术，且特别涉及具有能产生通道应变的衬层的集成电路装置。
背景技术
半导体集成电路(integrated circuit；IC)产业已经历快速成长。在集成电路演进的历程中，当几何尺寸(亦即工艺中所能创造出最小的元件或线路)缩减时，功能密度(亦即单位芯片面积的内连接装置数量)通常也增加。这种尺寸微缩的工艺通常通过提高生产效率及降低相关成本而提供一些效益。然而，这样的尺寸微缩也增加了包含这些集成电路的装置在加工和制造上的复杂度。制造上的平行进步使得越来越复杂的设计能够以精确和可靠的方式制造。
举例来说，制造上的进步使得三维设计成为可能，例如鳍式场效晶体管(fin-likefield effect transistor；FinFET)。可以将鳍式场效晶体管设想为从基板突出(extrudedout)并进入栅极的典型平面装置。示例性鳍式场效晶体管具有从基板向上延伸的薄“鳍片”(或鳍片结构)。场效晶体管(FET)的通道区域形成于此垂直鳍片中，且栅极设置于鳍片的通道区域之上(例如包覆(wrapping around))。以鳍片包覆住栅极增加了通道区域和栅极之间的接触面积，并允许栅极从多个侧面控制通道。这可以通过多种方式实现，并且在一些应用中，鳍式场效晶体管提供降低的短通道效应、减少的漏电(leakage)和更高的电流。换句话说，它们可以比平面装置更快、更小、更有效率。
鳍式场效晶体管和平面装置都可受益于生产最适化，例如应变工程(strainengineering)，其形成应变产生(strain-generating)层以对装置的一部分施加应力，借此改善电荷载子通过装置的通道区域的流动。
发明内容
根据本公开的一实施例，提供一种集成电路装置，包含：基板；鳍片，延伸自所述基板；栅极，设置于所述鳍片上且具有朝向所述鳍片设置的底部分和设置于所述底部分上的顶部分；以及衬层，设置于所述栅极的底部分的侧表面上，使得所述栅极的顶部分没有衬层。
根据本公开的另一实施例，提供一种集成电路装置，包含：基板；一对源极/漏极部件，设置于所述基板上；栅极，设置于该对源极/漏极部件之间；以及衬层，设置于每一对源极/漏极部件上且沿着所述栅极的第一部分延伸，使得所述栅极的第二部分没有衬层。
又根据本公开的另一实施例，提供一种集成电路装置的制造方法，包含：接收基板，所述基板具有设置于其上的占位栅极；形成衬层，沿着所述占位栅极的侧表面的第一部分延伸，使得所述侧表面的第二部分没有衬层，其中所述衬层被配置以产生通道应变；以及以功能性栅极取代所述占位栅极。
附图说明
通过以下的详细描述配合说明书附图，可以更加理解本公开实施例的内容。需强调的是，根据产业上的标准惯例，许多部件(feature)并未按照比例绘制。事实上，为了能清楚地讨论，各种部件的尺寸可能被任意地增加或减少。
图1是根据本公开实施例的各个面向示出制造具有应变产生衬层的工件的方法流程图。
图2A、图3A、图4A、图5A、图6A、图7A、图8A、图9A、图10A和图11A是根据本公开实施例的各个面向示出在制造方法中的各个点用于形成非平面装置的工件的第一区域的剖面图。
图2B、图3B、图4B、图5B、图6B、图7B、图8B、图9B、图10B和图11B是根据本公开实施例的各个面向示出在制造方法中的各个点用于形成非平面装置的工件的第二区域的剖面图。
图12A、图13A和图14A是根据本公开实施例的各个面向示出在制造方法中的各个点用于形成平面装置的工件的第一区域的剖面图。
图12B、图13B和图14B是根据本公开实施例的各个面向示出在制造方法中的各个点用于形成平面装置的工件的第二区域的剖面图。
附图标记说明如下：
100～方法
102、104、106、108、110、112、114、116、118～方框
200、1200～工件
204、1202～基板
206、1204～第一区域
207、1206～第二区域
208～鳍片
210、1208～隔离部件
212、1210～占位栅极
214～占位栅极材料
216～硬掩模层
218、1216～侧壁间隔物
220、1218～源极/漏极部件
222、1220～接触蚀刻停止层
302、1222～衬层
402～倒角部件
404、406、502、1116、1118、1302、1416、1418～高度
702、1306～层间介电层
1002～凹槽
1102、1402～功能性栅极
1104、1404～界面层
1106、1406～栅极介电质
1108、1408～盖层
1110、1410～功函数层
1112、1412～电极填充物
1114、1414～栅极盖
具体实施方式
以下内容提供了许多不同的实施例或范例，用于实施所提供的标的的不同部件。组件和配置的具体范例描述如下，以简化本公开实施例。当然，这些仅仅是范例，并非用以限定本公开实施例。举例来说，叙述中若提及第一部件形成于第二部件上方，可能包含形成第一和第二部件直接接触的实施例，也可能包含额外的部件形成于第一和第二部件之间，使得第一和第二部件不直接接触的实施例。此外，在本公开实施例中，形成一个部件连接至及/或耦合至另一部件，可能包含形成两个部件直接接触的实施例，也可能包含两者之间有其他部件形成介入，使得两个部件不直接接触的实施例。
此外，其中可能用到与空间相对用语，例如：“较低的”、“较高的”、“水平的”、“垂直的”、“上方”、“之上”、“下方”、“下方”、“上”、“下”、“顶部”、“底部”等及其类似的用词(例如“水平地”、“向下地”、“向上地”等)为了便于描述如图所示的一个部件与另一个部件之间的关系。这些空间相对用语是用以涵盖包含这些部件的装置的不同方位。另外，本公开实施例可能在不同实施例中重复使用参考符号及/或标记。这些重复为了简化与清晰的目的，并非用以限定不同实施例及/或结构之间具有超出所述范围的特定的关系。
示例性集成电路包含数个电性互连的平面装置(例如场效晶体管)及/或非平面装置(例如鳍式场效晶体管)。可以在一些装置上形成一或多个应变产生层。在一个这样的示例中，应变产生层形成于平面及/或非平面装置的源极/漏极部件上。应变产生层也可以沿着装置的栅极垂直延伸。当应变产生层被氧化时，会膨胀并在相邻的通道区域上产生应变。
然而，已经确定的是，沿着栅极延伸的应变产生层的最上部分可能对通道应变不具有意义的贡献，因为它们与基板和通道仍相隔一段距离。相反地，应变产生层的这些部分向栅极本身和周围结构施加力量。在移除占位栅极的栅极置换工艺(gate replacementprocess)期间，应变产生层的顶部可以在占位栅极留下的凹槽上向内挤压(press)，并且可使凹槽的顶部变窄或塌陷。即使凹槽没有塌陷，当在凹槽中形成功能性栅极时，变窄也可能导致填充问题。此外，当功能性栅极形成于凹槽中时，栅极可能具有较窄的顶部和缩小的临界尺寸。窄顶(narrow-top)栅极可能产生接触对准问题且可能具有较高的栅极电阻。因此，本技术的一些示例选择性地从装置栅极旁(alongside)移除应变产生层的最上部分。
经由这些方式和其他方式，经修饰的应变产生层提供改善的电性(例如导通模式(on-mode)中降低的电阻、更大的电流、更快地切换(switching)等)，而没有栅极变形、降低临界尺寸或与某些技术相关的填充缺陷的风险。然而，除非另有说明，否则实施例不需要提供任何特定的优点。
本公开实施例提供了集成电路装置及用于制造所述装置的技术的示例。一些示例形成非平面晶体管，例如参照图1和图2A至图11B所描述的那些装置。其他的示例形成平面晶体管，例如参照图1和图12A至图14B所描述的那些装置。
图1是根据本公开实施例的各个面向示出制造具有应变产生衬层(liner)的工件的方法100的流程图。可以在方法100的前、期间和的后提供额外的步骤，并且可以在方法100的其他实施例中取代或消除所述的一些步骤。
图2A、图3A、图4A、图5A、图6A、图7A、图8A、图9A、图10A和图11A是根据本公开实施例的各个面向示出在制造方法中的各个点用于形成非平面装置的工件200的第一区域的剖面图。图2B、图3B、图4B、图5B、图6B、图7B、图8B、图9B、图10B和图11B是根据本公开实施例的各个面向示出在制造方法中的各个点用于形成非平面装置的工件200的第二区域的剖面图。为清楚起见且为了优选地说明本公开实施例的概念，已经简化了图2A至图11B。可以将额外的部件合并到工件200中，且在工件200的其他实施例中，可以取代或消除以下所述的一些部件。
参照图1的方框102并参照图2A和图2B，接收工件200。工件200包含基板204，装置将形成于基板204上。在各个示例中，基板204包含元素(单一元素)半导体，例如晶体结构的硅或锗；化合物半导体，例如碳化硅、砷化镓、磷化镓、磷化铟、砷化铟及/或锑化铟；合金半导体，例如SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；非半导体材料，例如钠钙玻璃(soda-lime glass)、熔融硅、熔融石英及/或氟化钙(CaF2)；及/或前述的组合。
基板204的组成可以是均匀的，或者可以包含各种膜层，可选择性蚀刻其中一些膜层以形成鳍片(fin)。这些膜层可具有相似或不同的组成，并且在各个实施例中，一些基板层具有不均匀的组合物以引发装置应变并借此调节装置的效能。分层基板的示例也包含绝缘体上覆硅(silicon-on-insulator；SOI)基板204。在一些这样的示例中，绝缘体上覆硅基板204的绝缘层包含半导体氧化物、半导体氮化物、半导体氮氧化物、半导体碳化物及/或其他合适的绝缘材料。
可形成掺杂区域(例如阱)于基板204上，且基板204的一些区域可掺杂有p-型掺杂物，例如硼、BF2或铟，而基板204的其他区域可掺杂有n-型掺杂物，例如磷或砷；及/或包含前述的组合的其他合适掺杂物。基板204的特定区域的掺杂可取决于将要形成在所述区域上的装置。在一示例中，基板204包含用于形成图2A、图3A、图4A、图5A、图6A、图7A、图8A、图9A、图10A和图11A所示的p-通道装置的第一区域206以及用于形成图2B、图3B、图4B、图5B、图6B、图7B、图8B、图9B、图10B和图11B所示的n-通道装置的第二区域207。
在一些示例中，将要形成于基板204上的装置自基板204延伸出来。举例来说，鳍式场效晶体管及/或其他非平面装置可形成于设置在基板204上的装置鳍片208上。鳍片208代表任何凸起的(raised)部件且包含鳍式场效晶体管装置鳍片208和用于在基板204上形成其他凸起的主动和被动装置的鳍片208。可以通过蚀刻基板204的一部分、沉积各种层于基板204上并蚀刻这些层及/或通过其他合适的技术来形成鳍片208。举例来说，可以使用一或多个光刻工艺来图案化鳍片208，包含双重图案化(double-patterning)或多重图案化(multi-patterning)工艺。通常而言，双重图案化或多重图案化工艺结合光刻和自对准(self-aligned)工艺，使得将被创造的图案的例如节距(pitches)小于利用例如单一、直接的光刻工艺所获得的节距。举例而言，在一实施例中，形成牺牲层于基板之上并利用光刻工艺将牺牲层图案化。利用自对准工艺在经图案化的牺牲层旁(alongside)形成间隔物。然后移除牺牲层，剩余之间隔物可接着用于将鳍片图案化。
鳍片208在组成上可类似于基板204，或者可以与基板204不同。举例来说，在一些实施例中，基板204主要包含硅，而鳍片208包含一或多层主要为锗或硅锗的半导体。在一些实施例中，基板204包含硅锗半导体，且鳍片208包含一或多层具有不同硅与锗比例的硅锗半导体。
鳍片208可以通过隔离部件210，例如浅沟槽隔离部件(shallow trenchisolation features；STI)，与彼此物理地和电性分离。在这方面，鳍片208从基板204延伸穿过隔离部件210并延伸至隔离部件210上方，使得栅极结构(例如占位栅极(placeholdergate)212)可以包覆鳍片208。在各个示例中，隔离部件210包含介电材料，例如半导体氧化物、半导体氮化物、半导体碳化物、氟硅酸盐玻璃(FluoroSilicate Glass；FSG)、低介电常数(low-k)介电材料及/或其他合适的介电材料。
占位栅极212或虚设栅极形成于鳍片208的通道区域之上。通过施加至相邻并覆盖(overwrapping)通道区域的栅极结构的电压，控制源极/漏极部件之间通过通道区域的载子(用于n-通道鳍式场效晶体管的电子和用于p-通道鳍式场效晶体管的空穴)的流动。当栅极结构的材料对某些制造过程(例如源极/漏极活化退火)敏感或者难以图案化时，可以在一些制造过程期间使用占位栅极212，随后将其移除并以栅极后制(gate-last)工艺中的功能性栅极(例如栅极电极、栅极介电层、界面层等)的元件进行替换。
在一示例中，形成占位栅极212包含沉积一层占位栅极材料214，例如多晶硅、介电材料(例如半导体氧化物、半导体氮化物、半导体氮氧化物、半导体碳化物、半导体碳氮氧化物等)及/或其他合适的材料。
可以将硬掩模层216沉积于占位栅极材料214层上。硬掩模层216的组成可以与占位栅极材料214的组成不同，且在各个示例中，硬掩模层216包含介电材料(例如半导体氧化物、半导体氮化物、半导体氮氧化物、半导体碳化物、半导体碳氮氧化物等)及/或其他合适的材料。在一些实施例中，硬掩模层216包含多个构成层(constituent layer)，每一个构成层具有不同的介电材料，在一个这样的实施例中，硬掩模层216包含设置于占位栅极材料214上的第一层半导体氧化物和设置于所述氧化物层上的第二层半导体氮化物。
占位栅极材料214和硬掩模层216可以形成为均匀的膜层并且使用蚀刻工艺将其图案化以定义占位栅极212，所述蚀刻工艺例如湿蚀刻、干蚀刻、反应离子蚀刻(ReactiveIon Etching；RIE)、灰化及/或其他蚀刻方法。
侧壁间隔物218形成于占位栅极212的侧表面上。在各个示例中，侧壁间隔物218包含一或多层合适的材料，例如介电材料(例如半导体氧化物、半导体氮化物、半导体氮氧化物、半导体碳化物、半导体碳氮氧化物等)、旋涂玻璃(Spin On Glass；SOG)、四乙氧基硅烷(tetraethylorthosilicate；TEOS)、等离子体增强化学气相沉积氧化物(Plasma EnhancedCVD oxide；PE-oxide)、高深宽比工艺(High-Aspect-Ratio-Process；HARP)形成的氧化物及/或其他合适的材料。在一些示例中，侧壁间隔物218包含一或多层低介电常数介电材料，例如磷硅酸盐玻璃(PhosphoSilicate Glass；PSG)、硼磷硅酸盐玻璃(BoroPhosphoSilicate Glass；BPSG)、氟化硅玻璃(Fluorinated Silica Glass；FSG)、碳掺杂氧化硅、黑钻石(Black
Figure BDA0001999705830000081
)、干凝胶(Xerogel)、气凝胶(Aerogel)、非晶氟化碳(amorphous fluorinated carbon)、聚对二甲苯(Parylene)、双-苯并环丁烯(bis-benzocyclobutenes；BCB)、
Figure BDA0001999705830000082
(密西根州米特兰陶氏化学的注册商标)、聚酰亚胺、其他合适的材料。在一实施例中，侧壁间隔物218各自包含第一层半导体氧化物、设置于第一层上的第二层半导体氮化物、设置于第二层上的第三层半导体氧化物。在此实施例中，每一层侧壁间隔物218的厚度介于约1nm至约50nm。
源极/漏极部件220形成于占位栅极212相对两侧上的鳍片208上。在各个示例中，通过化学气相沉积(Chemical Vapor Deposition；CVD)沉积技术(例如气相外延(Vapor-Phase Epitaxy；VPE)及/或超高真空化学气相沉积(Ultra-High Vacuum CVD；UHV-CVD))、分子束外延(molecular beam epitaxy)及/或其他合适的工艺来形成源极/漏极部件220。外延工艺可以使用气体及/或液体前驱物，其与基板204的成分(例如硅或硅-锗)相互作用以形成源极/漏极部件220。源极/漏极部件220的半导体成分可以类似于或不同于鳍片208的剩余部分。举例来说，含硅的源极/漏极部件220可形成于含硅锗的鳍片208上，反之亦然。当源极/漏极部件220和鳍片208包含多于一个半导体时，其比例可实质上(substantially)类似或不同。
源极/漏极部件220可经由原位(in-situ)掺杂以包含p-型掺杂物，例如硼、BF2或铟；n-型掺杂物，例如磷或砷；及/或包含前述的组合的其他合适掺杂物。额外地或替代地，可以在形成源极/漏极部件220之后，使用布植工艺(亦即接合布植工艺(junction implantprocess))来掺杂源极/漏极部件220。关于特定掺杂物类型，源极/漏极部件220被掺杂为与鳍片208的剩余部分相反的类型。对于p-通道装置，鳍片208掺杂有n-型掺杂物且源极/漏极部件220掺杂有p-型掺杂物，而同样的道理也适用于n-通道装置。一旦将掺杂物引进源极/漏极部件220中，就可以进行掺杂物活化工艺以活化掺杂物，所述掺杂物活化工艺例如快速热退火(Rapid Thermal Annealing；RTA)及/或激光退火工艺。
接触蚀刻停止层(contact-etch stop layer；CESL)222可以在源极/漏极部件220上且沿着占位栅极212的顶部和侧面形成。接触蚀刻停止层222可以包含介电质(例如半导体氧化物、半导体氮化物、半导体氮氧化物、半导体碳化物等)及/或其他合适的材料，在各个实施例中，接触蚀刻停止层222包含SiN、SiO、SiON及/或SiC。可以通过任何合适的技术来沉积接触蚀刻停止层222，所述技术包含原子层沉积(Atomic Layer Deposition；ALD)、化学气相沉积(CVD)、高密度等离子体化学气相沉积(High Density Plasma CVD；HDP-CVD)及/或其他合适的技术，且接触蚀刻停止层222可以具有任何合适的厚度。在一些示例中，接触蚀刻停止层222的厚度介于约1nm至约50nm。
参照图1的方框104并参照图3A和图3B，衬层302形成于接触蚀刻停止层222上，使得衬层302设置于源极/漏极部件220上方并沿着占位栅极212的侧表面垂直延伸。衬层302也可设置于占位栅极212的顶表面之上。衬层302可包含半导体(例如硅、锗、硅锗等)、介电质(例如半导体氧化物、半导体氮化物、半导体氮氧化物、半导体碳化物等)及/或其他合适的材料。包含半导体的衬层302也可包含一或多种掺杂物(例如B、BF2、In、P及/或As)。可以通过任何合适的技术来沉积衬层302，所述技术包含原子层沉积(ALD)、化学气相沉积(CVD)、高密度等离子体化学气相沉积(HDP-CVD)及/或其他合适的技术，且衬层302可以具有任何合适的厚度。可以选择特定的厚度，使得衬层302足够厚以在衬层被氧化时产生通道应力(channel stress)，同时足够薄以在给定的退火预算(annealing budget)内完全氧化。在一些示例中，衬层302的厚度介于约1nm至约10nm。
衬层302可用来施加应变至将要形成于鳍片208上的装置的通道区域上。在许多应用中，通道应变改善载子迁移率，借此提高晶体管的电性(例如降低Ron、提高效率、增加切换速度等)。不同的应变方向对不同类型的装置产生不同的影响。通常而言，通道区域上的压缩应变整体改善p-通道装置的载子迁移率，而拉伸应变改善n-通道装置的载子迁移率。因此，在一些实施例中，衬层302被配置以改善p-通道装置的载子迁移率并且相应地设置于第一区域206上以形成p-通道装置而不设置在用于形成n-通道装置的第二区域207上。
在一些实施例中，这通过先在基板204的两个区域上形成衬层302来实现。然后，将光刻胶层涂布于工件并将光刻胶层图案化以覆盖并保护第一区域206中的衬层302并露出第二区域207中的衬层302。示例性光刻胶层包含光敏材料，光敏材料使得所述层在暴露于光时经历性质变化。这种性质变化可用来在称为光刻图案化的工艺中选择性移除光刻胶层的曝光或未曝光部分。
举例来说，在一个这样的实施例中，光刻系统使得光刻胶层在由掩模定义的特定图案中暴露于辐射。穿过掩模或从掩模反射的光照射光刻胶层，借此将形成于掩模上的图案转移至光刻胶。在其他这样的实施例中，使用直写(direct write)或无掩模光刻技术来图案化光刻胶层，例如激光图案化、电子束图案化及/或离子束图案化。一旦曝光，光刻胶层经过显影仅留下光刻胶的曝光部分，或者在替代实施例中，仅留下光刻胶的未曝光部分。示例性图案化工艺包含光刻胶层的软烘烤、掩模对准、曝光、曝光后烘烤(post-exposurebaking)、显影光刻胶层、清洗和干燥(例如硬烘烤)。
图案化工艺移除光刻胶层位于第二区域207中的那些部分。因此，在图案化光刻胶层之后，可以在工件200上进行一或多个蚀刻工艺以从第二区域207移除衬层302，此时光刻胶层保护了第一区域206中的衬层302。所述蚀刻工艺可包含任何合适的蚀刻技术，例如干蚀刻、湿蚀刻及/或其他蚀刻方法(例如反应离子蚀刻)。包含蚀刻剂化学物质的蚀刻技术可被配置以避免光刻胶层及/或接触蚀刻停止层222的显著蚀刻。在蚀刻衬层302之后，可以移除任何剩余的光刻胶。
参照图1的方框106，从占位栅极212旁(alongside)部分地移除衬层302。具体而言，沿着占位栅极212的侧表面移除衬层302的顶部分，而保留衬层302的底部分于占位栅极212侧面和源极/漏极部件220上。可以使用任何合适的倒角工艺(chamfering process)来移除衬层302的顶部分。
在一些示例中，一组倒角部件402形成于工件200上，如图4A和图4B所示。倒角部件402设置于占位栅极212之间，并在随后的蚀刻工艺期间保护衬层302下方的部分。倒角部件402包含任何合适的材料，其可以被选择为与衬层302及/或接触蚀刻停止层222具有不同的蚀刻选择性。在各个示例中，倒角部件402包含介电质(例如半导体氧化物、半导体氮化物、半导体氮氧化物、半导体碳化物、半导体碳氮化物等)、多晶硅、旋涂玻璃(SOG)、四乙氧基硅烷(TEOS)、等离子体增强化学气相沉积氧化物(PE-oxide)、高深宽比工艺(HARP)形成的氧化物、底部抗反射涂层(Bottom Anti-Reflective Coating；BARC)及/或其他合适的材料。可以使用任何合适的工艺来沉积倒角部件402，所述工艺包含原子层沉积(ALD)、化学气相沉积(CVD)、高密度等离子体化学气相沉积(HDP-CVD)、物理气相沉积(PVD)、旋涂式(spin-on)沉积及/或其他合适的沉积工艺。
可以通过将所选择的材料沉积在源极/漏极部件220的顶部上和占位栅极212的顶部上，并从占位栅极212的顶部回蚀刻衬层来形成倒角部件402。经回蚀刻的倒角部件402露出设置于占位栅极212旁的衬层302的一部分。在各个示例中，使用湿蚀刻、干蚀刻、反应离子蚀刻及/或化学机械平坦化/研磨(Chemical Mechanical Planarization/Polishing；CMP)以回蚀刻倒角部件402。倒角部件402的剩余部分可具有任何合适的高度及/或深宽比(aspect ratio)。在各个示例中，倒角部件402的高度介于相邻占位栅极212的高度的约1/100至约4/5，如标记404和406所示。
此后，蚀刻衬层302的露出部分，如图5A和图5B所示。在占位栅极212之间，所述蚀刻移除至少一部分设置于侧壁间隔物218旁且沿着接触蚀刻停止层222的垂直表面延伸的衬层302。衬层302的剩余部分可以包含沿着源极/漏极部件220延伸的水平部分，以及沿着接触蚀刻停止层222的垂直表面延伸的垂直部分，其延伸至水平部分上方的一高度。在这方面，垂直部分可以具有任何合适的高度502。在各个示例中，占位栅极212的高度404介于约10nm至约500nm，且衬层302的垂直部分的高度502介于占位栅极212的高度404的约1/100至约4/5。因此，大部分的占位栅极212(以及大部分的侧壁间隔物218和接触蚀刻停止层222的垂直表面)可以没有衬层302。
在各个示例中，衬层302的蚀刻包含湿蚀刻、干蚀刻、反应离子蚀刻及/或其他合适的蚀刻工艺。可以选择蚀刻工艺和蚀刻化学物质以大致上避免蚀刻接触蚀刻停止层222、倒角部件402、以及衬层302位于倒角部件402下方和旁边的部分。举例来说，当使用湿蚀刻时，可以选择蚀刻剂的黏度以防止显著蚀刻衬层302设置于倒角部件402旁的部分，否则将露出倒角部件402。
参见图6A和图6B，从占位栅极212之间移除倒角部件402。可以使用任何合适的蚀刻工艺移除倒角部件402，所述蚀刻工艺例如湿蚀刻、干蚀刻、反应离子蚀刻及/或其他合适的蚀刻工艺，且可以选择特定的蚀刻工艺和蚀刻剂化学物质以避免显著蚀刻衬层302、接触蚀刻停止层222及/或工件200的其他元件。在一些这样的示例中，通过具有氧反应物的灰化来移除倒角部件402。
参照图1并参照图7A和图7B，在工件200上形成层间介电(Inter-LevelDielectric；ILD)层702。层间介电层702用来做为支撑和隔离电性多层内连线结构(electrical multi-level interconnect structure)的导电迹线(traces)的绝缘体。相反地，多层内连线结构与工件200的元件电性互连，所述元件例如源极/漏极部件220和后续形成的功能性栅极。层间介电层702可包含介电材料(例如半导体氧化物、半导体氮化物、半导体氮氧化物、半导体碳化物等)、旋涂玻璃(SOG)、氟掺杂硅酸盐玻璃(fluoride-dopedsilicate glass；FSG)、磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、黑钻石(
Figure BDA0001999705830000132
加利福尼亚州圣克拉拉的应用材料)、干凝胶(Xerogel)、气凝胶(Aerogel)、非晶氟化碳、聚对二甲苯、双-苯并环丁烯(BCB)、
Figure BDA0001999705830000131
(密西根州米特兰陶氏化学)及/或前述的组合。可以通过任何合适的工艺来形成层间介电层702，所述工艺包含化学气相沉积(CVD)、物理气相沉积(PVD)、旋涂沉积及/或其他合适的工艺。
参见图1的方框110并参照图8A和图8B，对工件200进行退火工艺。退火工艺可以是层间介电层702的固化或致密化工艺的一部分。举例来说，层间介电层702可以以液体形式涂布，且退火可以固化任何剩余的液体前驱物。在另一个示例中，使用可流动式化学气相沉积(flowable CVD)工艺来沉积层间介电层702，且刚沉积的(as-deposited)形式包含元素(例如H、N等)及/或键(例如Si-H、Si-N等)，这些是不想要出现在完成的层间介电层702中的。退火可以赶走不需要的组成并重新构筑键结以增加密度、调节介电常数及/或调整层间介电层702的任何其他合适的性质。
退火工艺也可以使刚沉积的层间介电层702中的氧迁移至衬层302。氧可以与包含半导体的衬层302(例如经掺杂或未掺杂的Si衬层)键结以形成包含介电质的衬层302(例如经掺杂或未掺杂的SiOx衬层)。由于氧化硅的结构比结晶硅具有更大的体积，因此氧化可能会导致衬层302的体积膨胀。然而，所述膨胀可能受限于层间介电层702，借此导致压力累积。相反地，所述压力可能在所得装置中产生所需的通道应变。
如前所述，通道区上的压缩应变整体改善了p-通道装置的载子迁移率，而拉伸应变改善了n-通道装置的载子迁移率。因此，在一些实施例中，衬层302被配置以改善p-通道装置的载子迁移率且相应地设置于第一区域206上以形成p-通道装置而不设置在用于形成n-通道装置的第二区域207上。
退火工艺可包含将工件200加热到任何合适的温度，在各个示例中包含将工件200加热到介于约300℃至约1000℃的温度约10分钟至约24小时。退火工艺氧化一些或全部的衬层302，且在一些示例中，退火被配置以进行直到大致上所有衬层302都转变为氧化硅为止。因此，退火的持续时间可部分地取决于衬层302的厚度。在退火之后，衬层302和层间介电层702可具有一些共同的材料(例如半导体、氧等)，尽管这些材料的比例和其他材料特性(例如密度)可能不同。举例来说，衬层302中的氧与硅的比例可能低于层间介电层702中的比例。同样地，衬层302的密度可能高于层间介电层702的密度。
如前所述，因为衬层302被限制在占位栅极212和侧壁间隔物218的底部，所以衬层302在栅极置换工艺期间可施加较小的压力于侧壁间隔物218上(特别是接近栅极结构的顶部)。这可以减少填充问题、避免意外的栅极变窄、降低栅极电阻及/或避免接触对准的问题。
参照图1的方框112并参照图9A和图9B，在工件200上进行化学机械研磨/平坦化工艺以从占位栅极212的顶部移除层间介电层702及/或接触蚀刻停止层222。化学机械研磨/平坦化工艺之后，可进行回蚀刻工艺以从占位栅极212移除任何剩余的层间介电层702材料或接触蚀刻停止层222材料。
参照图1的方框114并参照图10A和图10B，做为栅极置换工艺的一部分，移除占位栅极212以在侧壁间隔物218之间提供凹槽1002。在一些示例中，先通过化学机械研磨/平坦化及/或蚀刻来移除硬掩模层216以露出占位栅极材料214。然后，可以通过一或多个蚀刻工艺(例如湿蚀刻、干蚀刻、反应离子蚀刻)，其使用蚀刻化学物质来移除占位栅极材料214，所述蚀刻化学物质被配置以选择性蚀刻占位栅极材料214和任何剩余的硬掩模层216而大致上不蚀刻周围的材料，例如鳍片208、侧壁间隔物218、接触蚀刻停止层222、层间介电层702等。
参照图1的方框116并参照图11A和图11B，功能性栅极1102形成于通过移除占位栅极212而定义的凹槽1002中。在一些示例中，形成功能性栅极包含在通道区域处的鳍片208的顶表面和侧表面上形成界面层1104。界面层1104可以包含界面材料，例如半导体氧化物、半导体氮化物、半导体氮氧化物、其他半导体介电质、其他合适的界面材料及/或前述的组合。可以使用任何合适的工艺形成具有任何合适厚度的界面层1104，所述工艺包含热生长、原子层沉积(ALD)、化学气相沉积(CVD)、高密度等离子体化学气相沉积(HDP-CVD)、物理气相沉积(PVD)、旋涂沉积及/或其他合适的沉积工艺。在一些示例中，通过热氧化工艺来形成界面层1104，且界面层1104包含存在于鳍片208中的半导体热氧化物(例如用于含硅鳍片208的氧化硅、用于含硅锗鳍片208的硅锗氧化物等)。
在一些示例中，形成功能性栅极1102包含形成设置于界面层1104上的栅极介电质1106。栅极介电质1106也可以沿着侧壁间隔物218的垂直表面设置。栅极介电质1106可以包含一或多个介电材料，其特征通常在于它们相对于二氧化硅的介电常数。在一些实施例中，栅极介电质1106包含高介电常数(high-k)介电材料，例如HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆、氧化铝、二氧化铪-氧化铝(HfO2-Al2O3)合金、其他合适的高介电常数介电材料及/或前述的组合。额外地或替代地，栅极介电质1106可以包含其他介电质，例如半导体氧化物、半导体氮化物、半导体氮氧化物、半导体碳化物、非晶碳(amorphouscarbon)、四乙氧基硅烷(TEOS)、其他合适的介电材料及/或前述的组合。可以使用任何合适的工艺来形成栅极介电质1106，包含原子层沉积(ALD)、等离子体增强原子层沉积(PlasmaEnhanced ALD；PEALD)、化学气相沉积(CVD)、等离子体增强化学气相沉积(PlasmaEnhanced CVD；PECVD)、高密度等离子体化学气相沉积(HDP-CVD)、物理气相沉积(PVD)、旋涂沉积及/或其他合适的沉积工艺。栅极介电质1106可以具有任何合适的厚度，在一些示例中，栅极介电质1106的厚度介于约0.1nm至约3nm。
在一些示例中，形成功能性栅极1102包含在工件200上形成栅极电极。栅极电极可以包含数个不同的导电层，其中示出三个示例性膜层(盖层1108、功函数层1110和电极填充物1112)。关于第一层，在一些示例中，形成栅极电极包含在工件200上形成盖层(cappinglayer)1108。盖层1108可以包含任何合适的导电材料，包含金属(例如W、Al、Ta、Ti、Ni、Cu、Co等)、金属氮化物及/或金属硅氮化物，且可以通过化学气相沉积(CVD)、原子层沉积(ALD)、等离子体增强化学气相沉积(PECVD)、等离子体增强原子层沉积(PEALD)、物理气相沉积(PVD)及/或其他合适的沉积工艺来沉积盖层1108。在各个实施例中，盖层1108包含TaSiN、TaN及/或TiN。
在一些示例中，形成栅极电极包含在盖层1108上形成一或多个功函数层1110。基于装置的类型，合适的功函数层1110材料包含n-型及/或p-型功函数材料。示例性的p-型功函数金属包含TiN、TaN、Ru、Mo、Al、WN、ZrSi2、MoSi2、TaSi2、NiSi2、WN、其他合适的p-型功函数材料及/或前述的组合。示例性的n-型功函数金属包含Ti、Ag、TaAl、TaAlC、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、其他合适的n-型功函数材料及/或前述的组合。可以通过任何合适的技术来沉积功函数层1110，所述技术包含原子层沉积(ALD)、化学气相沉积(CVD)、等离子体增强化学气相沉积(PECVD)、等离子体增强原子层沉积(PEALD)、物理气相沉积(PVD)及/或前述的组合。因为p-通道和n-通道装置可以具有不同的功函数层1110，所以在一些示例中，p-型功函数层1110沉积于第一沉积工艺中，所述工艺使用介电硬掩模以防止沉积至n-通道装置的电极上，n-型功函数层1110于第二沉积工艺中，所述第二沉积工艺使用介电硬掩模以防止沉积在p-通道装置的电极上。
在一些示例中，形成栅极电极包含在功函数层1110上形成电极填充物1112。电极填充物1112可以包含任何合适的材料，包含金属(例如W、Al、Ta、Ti、Ni、Cu、Co等)、金属氧化物、金属氮化物及/或前述的组合，在一示例中，电极填充物包含钨。可以通过任何合适的技术来沉积电极填充物1112，所述技术包含原子层沉积(ALD)、化学气相沉积(CVD)、等离子体增强化学气相沉积(PECVD)、等离子体增强原子层沉积(PEALD)、物理气相沉积(PVD)及/或前述的组合。
可以进行化学机械研磨/平坦化工艺来移除功能性栅极1102外部多余的电极材料(例如盖层1108、功函数层1110、电极填充物1112等的材料)。
在一些示例中，形成栅极结构1102(又称为功能性栅极)包含部分地凹陷栅极结构1102(例如栅极介电质1106、盖层1108、功函数层1110、电极填充物1112等)和形成栅极盖(gate cap)1114于凹陷的栅极结构1102上。栅极盖1114可以包含任何合适的材料，例如介电材料(例如半导体氧化物、半导体氮化物、半导体氮氧化物、半导体碳化物，半导体碳氮氧化物等)、多晶硅、旋涂玻璃(SOG)、四乙氧基硅烷(TEOS)、等离子体增强化学气相沉积氧化物(PE-oxide)、高深宽比工艺(HARP)形成的氧化物及/或其他合适的材料。在一些示例中，栅极盖1114包含碳氮氧化硅。可以使用任何合适的沉积技术(例如化学气相沉积、高密度等离子体化学气相沉积、原子层沉积等)形成具有任何合适厚度的栅极盖1114。在一些示例中，通过化学气相沉积(CVD)及/或原子层沉积(ALD)工艺沉积栅极盖1114，且栅极盖1114的厚度介于约1nm至约50nm。
因此，方法100提供的衬层302沿着功能性栅极1102的侧面具有降低的高度。在各个示例中，衬层302的垂直部分的高度1116介于约1nm至约50nm，而且是功能性栅极1102的高度1118的约1/100至约4/5。
参照图1的方框118，提供工件200以用于进一步的制造。在各个示例中，这包含形成耦合到源极/漏极部件220和功能性栅极1102的接触件，形成电性互连结构的剩余部分、切割(dicing)、封装和其他制造过程。
虽然以上示例涉及非平面装置(例如鳍式场效晶体管)，但是方法100同样适用于在平面装置中形成应变产生衬层。参照图1和图12A至图14B描述利用方法100形成平面装置的示例。图12A、图13A和图14A是根据本公开实施例的各个面向示出在制造方法中的各个点用于形成平面装置的工件1200的第一区域的剖面图，图12B、图13B和图14B是根据本公开实施例的各个面向示出在制造方法中的各个点用于形成平面装置的工件1200的第二区域的剖面图。为清楚起见且为了优选地说明本公开实施例的概念，已经简化了图12A至图14B。可以将额外的部件合并到工件1200中，且在工件1200的其他实施例中，可以取代或消除以下所述的一些部件。
参照图1的方框102并参照图12A和图12B，接收工件1200。工件1200包含基板1202，基板1202可大致类似于上述的基板204，除了它可以不包含从其延伸的装置鳍片。不在鳍片上形成装置，而是在基板1202的顶表面上形成平面装置(例如场效晶体管)。在一示例中，基板1202包含用于形成图12A所示的p-通道装置的第一区域1204和用于形成图12B所示的n-通道装置的第二区域1206。
基板1202的主动区域可以通过隔离部件1208(例如浅沟槽隔离)与彼此物理地和电性隔离，大致上如前所述。
工件1200可包含设置于基板1202上的占位栅极1210。占位栅极1210可大致类似于前述那些，除了它们可设置于基板1202的顶表面上而不是包覆鳍片。占位栅极1210可以包含一层占位栅极材料1212、硬掩模层1214和侧壁间隔物1216，各自大致如前所述。
工件1200也可以包含设置于占位栅极1210相对两侧上的基板1202上的源极/漏极部件1218和设置于侧壁间隔物1216上和源极/漏极部件1218上的接触蚀刻停止层1220，各自大致类似于前述的那些。
参照图1的方框104，衬层1222形成于接触蚀刻停止层1220上，使得衬层1222设置于源极/漏极部件1218和占位栅极1210之上且垂直延伸于占位栅极1210旁。这可大致如前所述地进行。衬层1222可以足够厚以在衬层被氧化时产生通道应力(channel stress)，同时足够薄以在给定的退火预算内完全氧化。在一些示例中，衬层1222的厚度介于约1nm至约10nm。
参照图1的方框106并参照图13A和图13B，沿着占位栅极1210的侧表面移除衬层1222的顶部分，而保留衬层1222的底部分于占位栅极1210的侧表面和源极/漏极部件1218上。这可大致如前所述地进行，且在一些这样的示例中，形成倒角部件以保护衬层1222下方的部分，同时移除衬层1222的露出部分。沿着接触蚀刻停止层1220的垂直表面延伸的衬层的剩余部分可以具有任何合适的高度1302。在各个示例中，高度1302介于约1nm至约50nm，而且为占位栅极1210的高度1304的约1/100至约4/5。因此，大部分的占位栅极1210(且因此，大部分的侧壁间隔物1216和接触蚀刻停止层1220的垂直表面)可以没有衬层1222。
参照图1的方框108并参照图13A和图13B，在工件1200上形成大致与前述类似的层间介电(Inter-Level Dielectric；ILD)层1306。
参见图1的方框110，对工件1200进行退火工艺。退火工艺可以是层间介电层1306的固化或致密化工艺的一部分，而且也可以使刚沉积的(as-deposited)层间介电层1306中的氧迁移至衬层1222。氧可以与包含半导体的衬层1222(例如经掺杂或未掺杂的Si衬层)键结以形成包含介电质的衬层1222(例如经掺杂或未掺杂的SiOx衬层)。由于氧化硅的结构比结晶硅具有更大的体积，因此氧化可能会导致衬层1222的体积膨胀。然而，所述膨胀可能受限于层间介电层1306，借此累积压力。相反地，所述压力可能在所得装置中产生所需的通道应变。
在一些实施例中，衬层1222被配置以改善p-通道装置的载子迁移率且相应地设置于第一区域1204上以形成p-通道装置而不设置在用于形成n-通道装置的第二区域1206上。
退火工艺可以包含将工件1200加热到任何合适的温度，且在各个示例中包含将工件1200加热到介于约300℃至约1000℃的温度约10分钟至约24小时。在退火之后，衬层1222和层间介电层1306可以具有一些共同的材料(例如半导体、氧等)，尽管这些材料的比例和其他材料特性(例如密度)可能不同。举例来说，衬层1222中的氧与硅的比例可能低于层间介电层1306中的比例。同样地，衬层1222的密度可能高于层间介电层1306的密度。
如前所述，因为衬层1222被限制在占位栅极1210和侧壁间隔物1216的底部，所以衬层1222在栅极置换工艺期间可施加较小的压力于侧壁间隔物侧壁间隔物1216上(特别是在接近栅极结构的顶部)。这可以减少填充问题、避免意外的栅极变窄、降低栅极电阻及/或避免接触对准的问题。
参照图1的方框112，在工件1200上进行化学机械研磨/平坦化工艺以从占位栅极1210的顶部移除层间介电层1306及/或接触蚀刻停止层1220。
参见图1的方框114，做为栅极置换工艺的一部分，移除占位栅极1210以在侧壁间隔物1216之间提供凹槽。
参照图1的方框116并参照图14A和图14B，功能性栅极1402形成于通过移除占位栅极1210而定义的凹槽中。形成功能性栅极1402可以包含形成界面层1404、栅极介电质1406、盖层1408、功函数层1410、电极填充物1412及/或栅极盖1414，各自大致如上所述。
参照图1的方框118，提供工件1200以用于进一步的制造。在各个示例中，这包含形成耦合到源极/漏极部件1218和功能性栅极1402的接触件，形成电性互连结构的剩余部分、切割、封装和其他制造过程。
因此，方法100提供的衬层1222沿着功能性栅极1402的侧面具有降低的高度。在各个示例中，衬层1222的垂直部分的高度1416介于约1nm至约50nm，而且是功能性栅极1402的高度1418的约1/100至约4/5。
因此，本公开实施例提供一种具有应变产生衬层的集成电路的示例及其形成方法。在一些实施例中，集成电路包含：基板、延伸自所述基板的鳍片、设置于所述鳍片上的栅极，其具有朝向所述鳍片设置的底部分和设置于所述底部分上的顶部分。衬层设置于所述栅极的底部分的侧表面上，使得所述栅极的顶部分没有衬层。在一些这样的实施例中，所述衬层被配置以产生通道应变(channel strain)。在一些这样的实施例中，所述衬层的高度介于栅极的高度的约1/100至约4/5。在一些这样的实施例中，大部分的栅极没有衬层。在一些这样的实施例中，基板包含第一区域和第二区域，其中所述第一区域具有第一通道类型的第一装置且所述第二区域具有第二通道类型的第二装置。第一区域包含所述衬层，且第二区域没有所述衬层。在一些这样的实施例中，所述鳍片包含一源极/漏极部件且所述衬层设置于源极/漏极部件上。在一些这样的实施例中，所述集成电路装置还包含蚀刻停止层，设置于所述衬层和所述栅极的底部分的侧表面之间。在一些这样的实施例中，所述蚀刻停止层更设置于所述衬层和所述鳍片之间。在一些这样的实施例中，所述装置还包含层间介电层，设置于所述衬层上。所述衬层物理接触蚀刻停止层的底部分，且所述层间介电层物理接触蚀刻停止层的顶部分。在一些这样的实施例中，所述衬层和所述层间介电层各自包含半导体和氧。在一些这样的实施例中，所述衬层中半导体与氧的比例不同于所述层间介电层中半导体与氧的比例。在一些这样的实施例中，所述衬层的密度不同于所述层间介电层的密度在一些这样的实施例中，衬层包含中心部分和朝向所述栅极设置的侧部分，其中所述侧部分延伸至中心部分上方。在一些这样的实施例中，所述侧部分延伸至一高度，所述高度小于栅极的高度。
在进一步的实施例中，装置包含基板、设置于所述基板上的一对源极/漏极部件、设置于该对源极/漏极部件之间的栅极、以及设置于每一对源极/漏极部件上且沿着所述栅极的第一部分延伸的一衬层，使得所述栅极的第二部分没有衬层。在一些这样的实施例中，所述衬层包含：沿着该对源极/漏极部件延伸且具有第一高度的水平部分，以及沿着所述栅极延伸且具有大于第一高度的第二高度的垂直部分。在一些这样的实施例中，第二高度介于栅极的高度的约1/100至约4/5。在一些这样的实施例中，所述衬层被配置以产生通道应变。在一些这样的实施例中，大部分的栅极没有所述衬层。在一些这样的实施例中，所述装置还包含设置于所述衬层和一对源极/漏极部件的个别(respective)源极/漏极部件之间且设置于每一对源极/漏极部件上的接触蚀刻停止层。在一些这样的实施例中，接触蚀刻停止层更设置于所述衬层和所述栅极之间。
在更进一步的实施例中，集成电路装置的制造方法包含：接收基板，所述基板具有设置于其上的占位栅极，以及形成沿着所述占位栅极的侧表面的第一部分延伸的衬层，使得所述侧表面的第二部分没有衬层。所述衬层被配置以产生通道应变。由功能性栅极取代所述占位栅极。在一些这样的实施例中，形成所述衬层包含：形成所述衬层于占位栅极的侧表面的第一部分和第二部分上，以及进行倒角工艺以从所述占位栅极的侧表面的第二部分移除所述衬层。在一些这样的实施例中，形成所述衬层包含：沉积层间介电层于衬层上，以及退火所述基板以氧化衬层。在一些这样的实施例中，所述退火被配置以使得氧从所述层间介电层迁移至所述衬层。在一些这样的实施例中，形成所述衬层被配置以使得占位栅极大部分的侧表面没有衬层。
以上概述数个实施例的部件，使得在本公开所属技术领域中技术人员可以更加理解本公开实施例的面向。在本公开所属技术领域中技术人员应该理解，他们能以本公开实施例为基础，设计或修改其他工艺和结构，以达到与在此介绍的实施例相同的目的及/或优势。本公开所属技术领域中技术人员也应该理解到，此类等效的结构并未悖离本公开的构思与范围，且他们能在不违背本公开的构思和范围下，做各式各样的改变、取代和替换。

Claims (1)

1.一种集成电路装置，包括：
一基板；
一鳍片，延伸自该基板；
一栅极，设置于该鳍片上且具有朝向该鳍片设置的一底部分和设置于该底部分上的一顶部分；以及
一衬层，设置于该栅极的该底部分的一侧表面上，使得该栅极的该顶部分没有该衬层。
CN201910208312.4A 2018-06-29 2019-03-19 集成电路装置 Pending CN110660855A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201862691668P 2018-06-29 2018-06-29
US62/691,668 2018-06-29
US16/192,856 2018-11-16
US16/192,856 US10840375B2 (en) 2018-06-29 2018-11-16 Integrated circuits with channel-strain liner

Publications (1)

Publication Number Publication Date
CN110660855A true CN110660855A (zh) 2020-01-07

Family

ID=69008370

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910208312.4A Pending CN110660855A (zh) 2018-06-29 2019-03-19 集成电路装置

Country Status (3)

Country Link
US (2) US10840375B2 (zh)
CN (1) CN110660855A (zh)
TW (1) TW202002292A (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10840375B2 (en) 2018-06-29 2020-11-17 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuits with channel-strain liner
US11063065B2 (en) * 2018-07-06 2021-07-13 Samsung Electronics Co., Ltd. Semiconductor device having a negative capacitance using ferroelectrical material
CN112582270A (zh) * 2019-09-28 2021-03-30 台湾积体电路制造股份有限公司 半导体结构的制造方法
US11757020B2 (en) 2020-01-31 2023-09-12 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method
US11610982B2 (en) 2020-09-15 2023-03-21 Taiwan Semiconductor Manufacturing Co., Ltd. Void elimination for gap-filling in high-aspect ratio trenches
US20220246747A1 (en) * 2021-02-04 2022-08-04 Tokyo Electron Limited Contact Etch Stop Layer with Improved Etch Stop Capability

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9245805B2 (en) 2009-09-24 2016-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Germanium FinFETs with metal gates and stressors
US8962400B2 (en) 2011-07-07 2015-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. In-situ doping of arsenic for source and drain epitaxy
US8841701B2 (en) 2011-08-30 2014-09-23 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device having a channel defined in a diamond-like shape semiconductor structure
US9236267B2 (en) 2012-02-09 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Cut-mask patterning process for fin-like field effect transistor (FinFET) device
US8847293B2 (en) 2012-03-02 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Gate structure for semiconductor device
US8836016B2 (en) 2012-03-08 2014-09-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structures and methods with high mobility and high energy bandgap materials
US8853025B2 (en) 2013-02-08 2014-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET/tri-gate channel doping for multiple threshold voltage tuning
US9093514B2 (en) 2013-03-06 2015-07-28 Taiwan Semiconductor Manufacturing Co., Ltd. Strained and uniform doping technique for FINFETs
US9136106B2 (en) 2013-12-19 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for integrated circuit patterning
US9520482B1 (en) 2015-11-13 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of cutting metal gate
US10879180B2 (en) * 2017-11-28 2020-12-29 Globalfoundries Inc. FinFET with etch-selective spacer and self-aligned contact capping layer
US10840375B2 (en) 2018-06-29 2020-11-17 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuits with channel-strain liner

Also Published As

Publication number Publication date
US20210083113A1 (en) 2021-03-18
US11430890B2 (en) 2022-08-30
TW202002292A (zh) 2020-01-01
US20200006558A1 (en) 2020-01-02
US10840375B2 (en) 2020-11-17

Similar Documents

Publication Publication Date Title
CN111128882B (zh) 集成电路器件及其形成方法
CN110729233B (zh) 具有气隙的半导体结构、其制造方法和气隙的密封方法
KR102237258B1 (ko) 핀 폭 균일성을 달성하기 위한 핀형 전계 효과 트랜지스터 패터닝 방법
US10854726B2 (en) Integrated circuit with doped low-k sidewall spacers for gate stacks
US11430890B2 (en) Integrated circuits with channel-strain liner
US11848326B2 (en) Integrated circuits with gate cut features
TW202018821A (zh) 積體電路的製造方法
US11830930B2 (en) Circuit devices with gate seals
US20190355729A1 (en) Integrated Circuits with Contacting Gate Structures
US11088022B2 (en) Different isolation liners for different type FinFETs and associated isolation feature fabrication
US11855082B2 (en) Integrated circuits with FinFET gate structures
US20230207320A1 (en) Integrated Circuits with Capacitors
TW201926429A (zh) 半導體元件
US20230387256A1 (en) Circuit devices with gate seals

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20200107

WD01 Invention patent application deemed withdrawn after publication