TWI686880B - 半導體裝置和其製造方法 - Google Patents

半導體裝置和其製造方法 Download PDF

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TWI686880B
TWI686880B TW106135966A TW106135966A TWI686880B TW I686880 B TWI686880 B TW I686880B TW 106135966 A TW106135966 A TW 106135966A TW 106135966 A TW106135966 A TW 106135966A TW I686880 B TWI686880 B TW I686880B
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Taiwan
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dielectric layer
layer
conductive
dielectric
forming
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TW106135966A
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TW201913837A (zh
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游佳達
李凱璿
陳燕銘
徐志安
楊世海
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台灣積體電路製造股份有限公司
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Abstract

本揭露提供一種半導體裝置及其製造方法。在上述裝置中，第一介電層設於基材上，且與導電線共平面。第二介電層設於導電線上方且第三介電層設於第一介電層上方。介層窗延伸穿過第二介電層並耦合至導電線。第二介電層和第三介電層共平面，且第二介電層和第三介電層具有不同組成。

Description

半導體裝置和其製造方法
本揭露是有關於一種半導體裝置和其製造方法，且特別是有關於一種增加製造介層窗時的製程窗的內連結構及其製造方法。
半導體積體電路工業歷經指數型的成長。在積體電路材料和設計的技術進步，已造就多個世代的積體電路，其每一代都比前一代具有更小且更複雜的電路。在積體電路的演進過程中，功能密度(即每晶片面積的內連裝置的數量)逐漸增加，而幾何尺寸(即可使用製程製造的最小元件(或線))逐漸變小。上述縮減尺寸的過程大致上提供了增加生產效能和減少相關成本的優點。上述的尺寸縮減也增加加工和製造積體電路的複雜度，且為了實現這些進步，則需要相似程度的積體電路加工和製造的發展。
例如：使用多層內連接來連接各種裝置(電晶體、電阻器、電容等)，以形成積體電路。在典型的多層內連結構中，多個導電線(如銅線)位在堆疊的介電層中，並透過介層窗從一層連接至另一層。此製程需要將多個導電特徵 對準其上方之層和其下方之層。此對準可藉著由微影(或光刻)製程製造的圖案來定義。有時候，微影製程間的重疊(overlay)失誤可能造成與目標導電特徵相關的介層窗未對準。未對準的導電特徵可能造成和鄰近導電特徵之非預期的橋接(短路)，導致積體電路缺陷；造成下方層的過度蝕刻，導致積體電路信賴度的問題；或造成導電特徵之間預定的內連接未對準，從而導致開路的風險。此導電特徵(例如介層窗-線)的未對準問題隨積體電路的持續縮減而變得更嚴重。
本揭露的一個層面提出一種半導體裝置。此裝置包含設於基材上方的導電線；設於基材上方並與導電線共平面的第一介電層；設於導電線上方的第二介電層；設於第一介電層上方的第三介電層；以及，延伸穿過第二介電層並與導電線耦合的介層窗。第二介電層和第三介電層共平面，且第二介電層和第三介電層具有不同組成。
本揭露的一個層面提出一種半導體裝置的製造方法，其包括形成導電特徵於第一介電層中，第一介電層設於基材上方，以及形成第二介電層於導電特徵上，並形成第三介電層於第一介電層上。第二介電層和第三介電層具有不同組成。蝕刻介層窗開口於第二介電層中，以從圖案化的第二介電層中暴露出導電特徵。以導電材料填入介層窗開口中。
本揭露的一個層面提出一種半導體裝置的製造 方法。上述方法包括形成多層內連結構的第一層。第一層包括第一金屬線和第一介電層。第二介電層形成於第一金屬線上方，且第三介電層形成於第一介電層上方。選擇性地蝕刻開口於第二介電層中，以暴露出第一金屬線。導電介層窗形成於開口中。然後，形成多層內連結構的第二層(其包括第二金屬線)。導電介層窗內連第二金屬線和第一金屬線。
100:方法
102、104、106、108、110、112、114、116、118、120:方塊
202:基材
204、1114:多層內連結構
206、902A:導電線(金屬線)
208:絕緣層(介電層)
210:抑制膜
302:第一層
302A、602A:虛線
402、402A、904、1134A、1134B、1134C:絕緣層
602:開口
702、902:導電材料
702A:介層窗
1100:裝置
1104:主動裝置
1106:閘極結構
1108:源極/汲極結構
1110:隔離特徵
1112:接觸結構
1116:第一金屬化層
1118:第二金屬化層
1120:第三金屬化層
1122:第四金屬化層
1124、1126、1128:介層窗結構
1130、1132:層
H:高度
W、W1:寬度
A-A’、B-B’:剖線
藉由以下詳細說明並配合圖式閱讀，可更容易理解本揭露。在此強調的是，按照產業界的標準做法，各種特徵並未按比例繪製，僅為說明之用。事實上，為了清楚的討論，各種特徵的尺寸可任意放大或縮小。
[圖1]繪示根據本揭露的各種層面之具有內連接件的積體電路的製造方法的一個實施例的流程圖。
[圖2A]、[圖3A]、[圖4A]、[圖5A]、[圖6A]、[圖7A]、[圖8A]、[圖9A]和[圖10A]繪示根據一些實施例於圖1之方法的各個製程階段中的裝置的一實施例的立體圖。
[圖2B]、[圖3B]、[圖4B]、[圖5B]、[圖6B]、[圖7B]、[圖8B]、[圖9B]、[圖10B]和[圖10C]繪示根據一些實施例於圖1之方法的各個製程階段中的裝置的一實施例的相對應剖面圖。
[圖11]繪示根據一些實施例的半導體裝置的一實施例的剖面圖。
下面的揭露提供了許多不同的實施例或例示，用於實現本揭露的不同特徵。部件和安排的具體實例描述如下，以簡化本揭露之揭露。當然，這些是僅僅是例示並且不意在進行限制。例如，在接著的說明中敘述在第二特徵上方或上形成第一特徵可以包括在第一和第二特徵形成直接接觸的實施例，並且還可以包括一附加特徵可以形成第一特徵的形成第一和第二特徵之間的實施例，從而使得第一和第二特徵可以不直接接觸。此外，本公開可以在各種例示重複元件符號和/或字母。這種重複是為了簡化和清楚的目的，並不在本身決定所討論的各種實施例和/或配置之間的關係。
此外，空間相對術語，如「之下」、「下方」、「低於」、「上方」、「高於」等，在本文中可以用於簡單說明如圖中所示元件或特徵對另一元件(多個)或特徵(多個特徵)的關係。除了在圖式中描述的位向，空間相對術語意欲包含元件使用或步驟時的不同位向。元件可以其他方式定位(旋轉90度或者在其它方位)，並且本文中所使用的相對的空間描述，同樣可以相應地進行解釋。
本揭露大致上是有關於半導體裝置，且特別是有關於積體電路的多層內連結構。然而，可以了解的是，欲使一(些)下層特徵對準另一(些)下層特徵的其他結構，也可從本揭露的多個層面中獲益。
圖1繪示根據本揭露的一或多個層面之半導體裝置的製造方法100的流程圖。方法100僅為例子，且方法100並非意欲限制本揭露超出申請專利範圍所明確記載 者。可於方法100前、中或後提供額外的操作，且上述方法的其他實施例可取代、刪除或移動所述的一些操作。
方法100從方塊102開始，其提供基材。示例的圖2A繪示半導體裝置200的立體圖，且圖2B繪示沿圖2A的剖線「A-A’」的半導體裝置200的剖面圖。請參考圖2A和圖2B的例子，半導體裝置200包括基材202。
在實施例中，基材202包括矽基材(例如晶圓)。選擇性地，基材202可包含如鍺的其他元素半導體；包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銦銻的化合物半導體；包含矽鍺(SiGe)、砷磷化鎵(GaAsP)、砷化鋁銦(AlInAs)、砷化鋁鎵(AlGaAs)、砷化鎵銦(GaInAs)、磷化鎵銦(GaInP)及/或砷磷化鎵銦(GaInAsP)的合金半導體；或上述的組合。在一些實施例中，基材202為絕緣層上覆矽(semiconductor on insulator；SOI)。基材202包括如p型場效電晶體(PFET)、n型場效電晶體(NFET)、金屬-氧化物半導體場效電晶體(MOSFET)、互補式金屬-氧化物半導體(CMOS)電晶體、二極式電晶體、高壓電晶體，和高頻率電晶體的主動裝置。電晶體可為平面電晶體或如鰭狀場效電晶體的多閘極電晶體。基材202可更包括如電阻器、電容和電感的被動裝置。後述將進一步說明的多層內連(multiple layer interconnect；MLI)結構204的一部分可用來內連接設置在基材202上的任何一或多個此些裝置。
然後，方法100可進行至方塊104，其形成導電線於基材上方。請參考圖2A和圖2B的例子，其繪示導電線206。導電線206為多層內連結構204的一部分。多層內連 結構為具有適合的絕緣材料部分環繞的導電線及/或介層窗或接觸結構的內連系列，多層內連結構提供設置於下方基材上的一或多個裝置的內連接。需說明的是，為了簡化，所示的多層內連結構204具有含導電線的單一層(及下述含導電線的第二層)。然而，在各種實施例中，多層內連結構204可包含任何數量(例如包含大於2)的導電層的層，例如在複雜的積體電路中有5、7或甚至更多層。每一個導電層可包括任何數量的導電線。此外，多層內連結構204可包括一或多層的導電線位於金屬化層下方，金屬化層包含所繪示的導電線206。再者，導電線206經由額外的導電線或介層窗，連接至設置在基材202上的一或多個元件或裝置。
導電線206可包括複數個層，如：阻障層、黏著層、及/或金屬層。在一些實施例中，阻障或黏著層包括鉭(Ta)、氮化鉭(TaN)、鈦(Ti)、氮化鈦(TiN)、鈷(Co)及/或其他適合的導電材料。在一些實施例中，銅層設置於阻障/黏著層上方。可做為導電線206的其他示例導電材料包括鋁(Al)、鎢(W)、鈷(Co)、多晶矽及/或其他適合的導體。在一個實施例中，導電線206包括阻障層(例如鉭或氮化鉭)和上方的銅導電材料。在實施例中，阻障層包括一或多層材料。
在實施例中，導電線206形成於絕緣層208中。在一些實施例中，絕緣層208包括低介電常數材料。絕緣層208的示例材料包括但不限於四乙氧基矽烷(tetraethyl orthosilicate；TEOS)氧化物、未摻雜的矽酸玻璃，或如硼磷矽酸鹽玻璃(BPSG)、熔融石英玻璃(FSG)、磷矽酸鹽 玻璃(PSG)、硼摻雜的矽玻璃(BSG)之摻雜的氧化矽，及/或其他適合的介電材料。
可藉由如低壓化學氣相沉積(LPCVD)、電漿加強型化學氣相沉積(PECVD)、流動式化學氣相沉積(FCVD)之化學氣相沉積技術或其他適合的沉積技術，將絕緣層208沉積於基材202上方。例如：流動式化學氣相沉積包括沉積流動的材料(如液態化合物)於基材202上方，以及藉由適合的技術將流動的材料轉變為固態材料，所述適合的技術如熱退火或紫外線。然後，藉由化學機械研磨製程平坦化或者凹陷絕緣層208，以使絕緣層208具有平坦的頂表面。在一些實施例中，隨後，以一或多個微影和蝕刻製程圖案化絕緣層208，以在絕緣層208中形成溝渠。微影製程可包括形成光阻(或阻劑)層於絕緣層208上、曝光所述光阻為一圖案、進行曝光後烘烤製程，以及顯影所述光阻以形成包含光阻的罩幕元件。然後，罩幕元件用來蝕刻溝渠於絕緣層208中。蝕刻製程可包括乾式蝕刻、濕式蝕刻及/或其他適合的製程。然後，導電線206可形成於蝕刻的溝渠中。例如：用來形成導電線206的阻障/黏著層及/或金屬層，可沉積於圖案化的絕緣層208中。在一些實施例中，可藉由如濺鍍、化學氣相沉積，及電鍍或無電電鍍的一或多個適合的技術，來沉積導電線206的導電材料。在沉積後，一或多個導電材料(例如阻障層和金屬導體層)可溢出絕緣層208中的溝渠，之後可進行化學機械研磨製程，以平坦化裝置200的頂表面，從而移除絕緣層208上方多餘的阻障和金屬材料。保留溝渠中的阻障和金屬材料，以形成導電線206。在一些實 施例中，因為化學機械研磨製程，絕緣層208的頂表面和導電線206的頂表面變成實質共平面。
方法100進行至方塊106，其沉積第一層材料於金屬線(或稱導電線)上。第一層材料可為選擇性地沉積，使得第一層材料實質覆蓋金屬線。在一些實施例中，圖案化第一層材料以形成特徵，所述特徵實質不延伸超過金屬線的末端。換言之，第一層材料形成一特徵，此特徵垂直對準金屬線並位於金屬線上。金屬線206上方的第一層之對準可落於製程的對準容忍度範圍內(例如落於10%內)。請參考圖3A和圖3B的例子，第一層302設置於基材202上方，特定地位於導電線206上方並與導電線206對準。第一層302和下方導電線206的垂直對準如圖3B的虛線302A所繪示。
在一實施例中，第一層302選擇性地成長於導電線206上。選擇性成長包括成長(或沉積)第一層302於導電線206上，然而不成長(或沉積)第一層302的材料於如介電層(或稱絕緣層)208之周圍的層上。在一些實施例中，可選擇性地成長氮化物材料，以形成第一層302。
在一實施例中，第一層302的選擇性成長包括預處理操作。在一實施例中，預處理操作包括導入化學物質至裝置的表面，包括導電線206的頂表面和介電層208的頂表面。化學物質的導入提供絕緣層208的頂表面上的懸浮鍵(dangling bond)之產生。預處理操作的示例化學物質包括酸水溶液，如稀釋氫氟酸(氫氟酸和去離子水)。預處理操作的示例化學物質也包括氣態化學物質的混合物，例如：氨(NH3)和三氟化氫(HF3)。
在一些實施例中，在選擇性成長的第一層302的預處理後包括一處理操作。此處理操作可終止(terminate)在預處理操作中產生的懸浮鍵。例如：此處理操作之進行可與介電層208(例如存在於介電層208的氧化物材料中的氧，包括前述的示例組成)中現存的懸浮鍵(例如氧原子)產生疏水鍵。此處理操作的製程氣體可例如包括雙(三甲基矽基)胺(bis(trimethylsilyl)amine)、六甲基二矽氮烷(hexamethyldisilazane；HMDS)、四甲基二矽氮烷(tetramethyldisilazane；TMDS)、三甲基氯矽烷(trimethylchlorosilane；TMCS)、二甲基二氯矽烷(dimethyldichlorosilane；DMDCS)、甲基三氯矽烷(methyltrichlorosilane；MTCS)或其類似物。
在一些實施例中，一或多個示例的製程氣體提供數個成分，此些成分適用於藉由矽化製程來接附至介電層208的懸浮鍵。接附至介電層208的氧原子者可包括C-H鍵，其可包括甲基(CH3)官能基。例如：根據一些實施例，接附的鍵結/材料可包括Si(CH3)3。
因為前述的鍵結，上述處理操作提供抑制膜(inhibitor film)210，抑制膜210形成於介電層208的頂表面上。所得的抑制膜210可非常薄，例如：抑制膜210可僅包括一些末端鍵結。需說明的是，在下述上方的層402之沉積中和沉積後，抑制膜210都保留在介電層208的頂表面上。
在上述分別說明的預處理操作和處理操作後，可進行形成第一層302的材料之選擇性成長。根據一些實施例，第一層302的材料可包括如氮化矽的介電材料。在一些 實施例中，選擇性成長是藉由導入製程氣體至導電線206的表面和抑制膜210來達成。製程氣體可包括如SiBr4的含矽前驅物。在一些實施例中，製程氣體可用來在約300℃至400℃的溫度下進行選擇性成長。
需說明的是，在一些實施例中，第一層302的選擇性成長提供包括第一層302對下層導電線206的自對準之優點。自對準緩和進行圖案化製程(包括如下述者)需要第一層302和下層導電線206之間的精確對準的需求。需說明的是，第一層302可選擇性地形成於金屬化層之每個暴露出的金屬線上方，所述金屬化層的金屬線包括示例的導電線206。
在一些實施例中，使用如低壓化學氣相沉積(LPCVD)、電漿加強型化學氣相沉積(PECVD)、流動式化學氣相沉積(FCVD)之化學氣相沉積技術或其他適合的沉積技術，將第一層302的材料沉積至基材202上。在一實施例中，所沉積的第一層302的材料為橫跨基材202之毯覆式沉積或共形沉積。在一些實施例中，接下來，以一或多個微影和蝕刻製程圖案化第一層302的材料，以形成特徵於導電線206的上方並與導電線206對準，如圖3A和圖3B所繪示的第一層302的特徵。圖案化第一層的材料為特徵的微影製程可包括形成光阻(或阻劑)層於第一層302的材料之毯覆式沉積上、將光阻曝光為一圖案、進行曝光後烘烤製程，以及顯影光阻以形成包括光阻的罩幕元件。罩幕元件可定義第一層302的特徵，使得第一層302的特徵位於導電線206上並與導電線206對準。在一些實施例中，然後，罩幕元件用 來蝕刻第一層302的材料，以將上述材料從絕緣層208上方移除。蝕刻製程可包括乾式蝕刻、濕式蝕刻、及/或其他適合的製程。需說明的是，第一層302可形成於金屬化層的每個金屬線上方。在一些實施例中，第一層包括位於每個金屬線上方的特徵，其中上方的介層窗將連接至金屬線。需說明的是，在使用如上述的微影圖案化的方法中，不形成抑制層(即抑制膜210)。
第一層302的材料為介電材料。在一實施例中，第一層302為氮化矽。第一層302之其他示例的介電材料包括碳氮化矽(SiCN)和碳氧氮化矽(SiCON)。可使用前述的選擇性沉積製程(例如預處理、處理和選擇性成長)來形成氮化矽、SiCN、SiCON的任一者及/或其他適合的組成。需說明的是，選擇第一層302的組成，以提供對下述的周圍絕緣層402的蝕刻選擇性。在一實施例中，相對於周圍的絕緣層402，第一層302的蝕刻選擇性為或大於約50%。
在導電線206上的第一層302具有高度H。在一些實施例中，高度H是藉由形成第一層302所沉積的材料之厚度來定義。在一些例子中，高度H為約5nm至50nm。高度H是藉由下述預定得到的介層窗結構長度(垂直延伸)而決定。在一些例子中，第一層302的特徵的寬度W為約等於導電線206的寬度。在一些例子中，寬度W為約5nm至25nm。
然後，方法100進行至方塊108，其形成絕緣層於基材上。絕緣層形成為與如上述方塊106的說明的第一層相鄰並相接。絕緣層可與第一層的特徵的側壁相接。請參考 圖4A和圖4B，絕緣層402形成在基材202上。絕緣層208和絕緣層402可包括相同或不同的介電材料。在一些實施例中，絕緣層402和絕緣層208的組成皆為氧化物。在一些實施例中，絕緣層402和絕緣層208為相同組成，例如：皆為相同的氧化物組成。在各種實施例中，絕緣層402包括如四乙氧基矽烷(tetraethyl orthosilicate；TEOS)氧化物、未摻雜的矽酸玻璃，或如硼磷矽酸鹽玻璃(BPSG)、熔融石英玻璃(FSG)、磷矽酸鹽玻璃(PSG)、硼摻雜的矽玻璃(BSG)之摻雜的氧化矽的低介電常數材料，及/或其他適合的介電材料。
絕緣層402可使用低壓化學氣相沉積、電漿加強型化學氣相沉積、流動式化學氣相沉積之化學氣相沉積技術來形成。
方法100進行至方塊110，其進行如化學機械研磨製程之平坦化製程。如圖4A和圖4B所繪示，在一些實施例中，形成絕緣層402使其設置在第一層302的上方。之後，如方塊110及圖5A和圖5B的例子所繪示，可回蝕絕緣層402以暴露出第一層302的頂表面，如絕緣層402A所繪示。在一些實施例，所述回蝕是藉由化學機械研磨製程進行。如圖5A和圖5B的例子所繪示，絕緣層402A的頂表面與第一層302的頂表面共平面。再者，如圖所繪示，絕緣層402A可與第一層302的側壁相接。
然後，方法100進行至方塊112，其蝕刻一開口於導電線的一部份上方的第一層中。開口可暴露出下方導電線的頂表面。可藉由預定的介層窗尺寸定義上述開口，如下 述，所述介層窗形成於開口中。請參考圖6A和圖6B的例子，將開口602蝕刻於第一層302中。開口602暴露出導電線206的頂表面。也可藉由絕緣層402A和第一層302的側壁來定義開口602。在一實施例中，上述蝕刻為濕式蝕刻、乾式蝕刻、電漿蝕刻的一種，或其他適合的蝕刻技術。在一些例子中，所述蝕刻為使用包括CH3F、O2及/或CH4的蝕刻劑之基於氟的電漿蝕刻。
如上述，絕緣層402A的組成使得絕緣層402A與第一層302不同。因此，在一些實施例中，第一層302的組成和周圍之絕緣層402A的組成之間具有蝕刻選擇性。因此，所述蝕刻可對第一層302有選擇性並局限於第一層302中，使得所得的開口602垂直對準導電線206，請參圖6B中所繪示的虛線602A的垂直對準。在一些實施例中，垂直對準為開口602和下層導電線206之間提供有利的自對準製程。在一些實施例中，第一層302的蝕刻率比周圍層的蝕刻率大至少50%。
開口602也可視為介層窗孔。開口602具有寬度W1，寬度W1實質與前述寬度W相同。在一些實施例中，開口602是藉由一或多個微影和蝕刻製程(如上述)來形成。微影製程可包括形成光阻層於絕緣層402A上、曝光光阻為一圖案以定義開口602，進行曝光後烘烤製程，以及顯影所述光阻以形成包括光阻的罩幕元件。然後，使用罩幕元件蝕刻開口至絕緣層402A中，直到導電線206暴露出來。如前述，蝕刻製程對第一層302的材料具有選擇性。需說明的是，在一些實施例中，由於第一層302所提供的蝕刻選擇性，疊設 罩幕元件以定義開口602的操作可具有較大的對準窗。例如：藉由罩幕元件所定義的開口可向左/右移動(如圖6B所示)，或者在光阻罩幕元件中提供較大寬度的開口，所述較大寬度是大於所得開口602之寬度W1，從而暴露出部分的絕緣層402A。這是因為雖然絕緣層402A可從罩幕元件中暴露出來，但由於絕緣層402A的組成和第一層302的組成之間的蝕刻選擇性，絕緣層402A暴露出的部分不會被蝕刻。因此，特定實施例可為定義開口的罩幕元件和導電線206之間的疊設提供較大的容忍度(margin)。
然後，方法100進行至方塊114，其以導電材料填入開口中，以形成介層窗。請參考圖7A和圖7B，以導電材料702填入開口602中。導電材料702可包括複數個層，例如包括：阻障層、黏著層和上方的導體層。在一些實施例中，導電材料702包括阻障層，例如：鉭或氮化鉭。在一些實施例中，導電材料702包括金屬導體，如銅、鋁、鎢、鈷或其他適合的金屬。阻障層可藉由化學氣相沉積、物理氣相沉積或原子層沉積之技術來形成。金屬導體可藉由濺鍍、化學氣相沉積或電鍍之技術來形成。可使用上述沉積方法，使導電材料702的層溢出開口602，如圖7A和圖7B所繪示。
然後，方法100進行至方塊116，其進行另一平坦化製程。在一些實施例中，平坦化製程包括化學機械研磨製程。圖8A和圖8B的例子繪示進行接續的平坦化製程後的裝置200。具體而言，進行平坦化(例如化學機械研磨)製程，以移除在方塊114中沉積並設置於絕緣層402A的頂表 面上方之過多的導電材料，留下剩下的導電層(例如阻障層和金屬導體)填於前述開口602中，從而提供介層窗702A。介層窗702A可包括一或多層(例如一個阻障層和一個金屬導體層)。
然後，方法100進行至方塊118，其形成另一導電線。可藉由實質相似於上述方塊104所說明者來形成另一導電線。請參考圖9A、圖9B、圖10A、圖10B和圖10C，沉積導電材料902以形成導電線902A於介層窗702A上方，且導電線902A與介層窗702A連接。絕緣層904設置於絕緣層402A上方，並與導電線902A相接。導電線902A可實質相似於導電線206。在一實施中，導電線902A和導電線206包括相同組成。在一些實施例中，導電線902A位於導電層或金屬化層中，所述導電層或金屬化層比導電線206所在的導電層或金屬化層高一階。例如：導電線902A可設置在金屬-2(Metal-2)，而導電線206設置在金屬-1(Metal-1)。絕緣層904可實質相似於上述說明的絕緣層402A及/或絕緣層208。在一實施例中，二個或更多的絕緣層904、絕緣層402A和絕緣層208包括相同組成。
導電材料902和，當然，導電線902A可包括複數個層，如阻障層、黏著層及/或金屬層。在一些實施例中，阻障層或黏著層包括鉭、氮化鉭、鈦、氮化鈦、鈷及/或其他適合的導電材料。在一些實施例中，銅層設置於阻障/黏著層上方。可做為導電線902A的其他示例導電材料包括鋁、鎢、鈷、多晶矽及/或其他適合的導體。在一實施例中， 導電線902A包括阻障層(例如鉭或氮化鉭)及上方的銅導電線。在實施例中，阻障層包括一或多層的材料。
在一實施例中，導電線902A形成於絕緣層904中。在一些實施例中，絕緣層904包括低介電常數材料。絕緣層904的示例材料可包括但不限於四乙氧基矽烷(tetraethyl orthosilicate；TEOS)氧化物、未摻雜的矽酸玻璃，或如硼磷矽酸鹽玻璃(BPSG)、熔融石英玻璃(FSG)、磷矽酸鹽玻璃(PSG)、硼摻雜的矽玻璃(BSG)之摻雜的氧化矽，及/或其他適合的介電材料。
可藉由如低壓化學氣相沉積(LPCVD)、電漿加強型化學氣相沉積(PECVD)、流動式化學氣相沉積(FCVD)之化學氣相沉積技術或其他適合的沉積技術，將絕緣層904沉積於基材202上方。然後，可藉由化學機械研磨製程，平坦化或者凹陷絕緣層904，以使絕緣層904具有平坦的頂表面。在一些實施例中，隨後，以一或多個微影和蝕刻製程圖案化絕緣層904，以在絕緣層904中形成溝渠。微影製程可包括形成光阻(或阻劑)層於絕緣層904上、曝光所述光阻為一圖案、進行曝光後烘烤製程，以及顯影所述光阻以形成包含光阻的罩幕元件。然後，罩幕元件用來蝕刻溝渠於絕緣層904中。蝕刻製程可包括乾式蝕刻、濕式蝕刻及/或其他適合的製程。然後，形成導電線902A的材料902可形成於蝕刻的溝渠中，如圖9A和圖9B所示。例如：用來形成導電線902A的阻障/黏著及/或金屬材料902，可沉積於圖案化的絕緣層904中。在一些實施例中，可藉由如濺鍍、化 學氣相沉積，及電鍍或無電電鍍的一或多個適合的技術，來沉積導電材料902。在沉積後，一或多個導電材料(例如阻障層和金屬導體層)可溢出絕緣層904中的溝渠(請參圖9A和圖9B)。之後，可進行化學機械研磨製程，以平坦化裝置200的頂表面，從而移除絕緣層904上方多餘的阻障和金屬材料，請參圖10A和圖10B。保留溝渠中的阻障和金屬材料，以形成導電線902A。在一些實施例中，因為化學機械研磨製程，絕緣層904的頂表面和導電線902A的頂表面變成實質共平面。
導電線206、介層窗702A和導電線902A提供多層內連結構204的示範導電特徵。多層內連結構204設置於基材202上方，並連接基材202中/上方的各種主動及/或被動裝置，以形成包括裝置200的積體電路。在所示的實施例中，導電線206可形成第一金屬化線(例如，視為金屬-1)，而導電線902A提供第二金屬化線(例如，視為金屬-2)，並以介層窗702A內連接上述金屬化線。然而，上述僅為示例，且在其他實施例中，導電線206和導電線902A可形成多層內連結構204的任何金屬層。雖然未繪示，導電線206/902A和介層窗702A，透過多層內連結構204的其他下層或透過主動及/或被動裝置的末端(例如源極、汲極和閘極接觸)，耦合至基材202中的主動及/或被動裝置。
需說明的是，圖10C繪示在剖線B-B’或者說從上方介層窗連接移開的導電線206。第一層302設置於導電線206上方並由絕緣層904、絕緣層402A和絕緣層208環 繞。在一些實施例中，絕緣層904、絕緣層402A和絕緣層208的組成為氧化物，第一層302的組成為氮化物。如此，第一層302的組成不同於一或多個絕緣層904、絕緣層402A和絕緣層208的組成。在一些實施例中，第一層302直接與導電線206的頂表面界面連接(interface)。
然後，方法100進行至方塊120，其可進行額外的製程。在一實施例中，進行額外的後段(back-end-of-the-line；BOEL)製程，如形成額外的金屬層和中介介電層，像是多層內連結構的額外特徵。
上述一或多個製程繪示使用鑲嵌製程形成介層窗702A和上方的金屬化層902A。包括雙鑲嵌製程的其他製程也可使用方法100來施行。
現在請參考圖11，其繪示可使用方法100的一或多個操作製造的裝置1100。裝置1100包括基材202，其實質相似於前述方法100的方塊102所說明的內容。主動裝置1104係建造於基材202上。在示範的實施例中，主動裝置1104為具有閘極結構1106和源極/汲極結構1108的電晶體。在一實施例中，主動裝置1104為鰭狀場效電晶體裝置，其設置於基材202延伸的主動區上。主動裝置1104設置在基材202的主動區上，而隔離特徵1110設置為與主動裝置1104相鄰。隔離特徵1110可為淺溝渠隔離特徵。
閘極結構1106可包括閘極介電層和閘極電極。可以了解的是，閘極結構1106可包含額外的層，如介面層、蓋層、擴散/阻障層、功函數層和其他適合的層。在 一些實施例中，閘極介電層為高介電常數閘極介電質。高介電常數材料的例子包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化鋯、氧化鋁、二氧化鉿-氧化鋁(HfO2-Al2O3)合金、其他適合的高介電常數材料或上述的組合。在一些實施例中，閘極結構包括多晶矽閘極電極。在一些實施例中，閘極結構包括金屬閘極電極。閘極電極層可包括任何適合的材料，如多晶矽、鋁、鈦、鉭、鎢、鉬、氮化鉭、矽化鎳、矽化鈷、氮化鈦(TiN)、氮化鎢(WN)、鈦鋁(TiAl)、氮化鈦鋁(TiAlN)、碳氮化鉭(TaCN)、碳化鉭(TaC)、矽氮化鉭(TaSiN)、金屬合金、其他適合的材料或上述的組合。在一些實施例中，閘極間隙壁包括在閘極結構中。閘極間隙壁可為多層介電質，其用來補償接下來形成的摻雜區，如源極/汲極區。閘極間隙壁可進一步用來設計或修飾源極/汲極區(接面)的形貌。
源極/汲極結構1108可包括適當摻雜以提供主動裝置1104的半導體材料。在一些實施例中，源極/汲極結構1108為具有n型摻質或p型摻質摻雜之磊晶成長的特徵。
接觸結構1112可從一或多個閘極結構1106和源極/汲極結構1108延伸。接觸結構1112可為鎢或其他適合的導電材料。
多層內連結構1114設置於主動裝置1104上方，並提供內連接至主動裝置1104。多層內連結構1114包括第一金屬化層(金屬-1)1116、第二金屬化層(金屬-2)1118、第三金屬化層(金屬-3)1120和第四金屬化層(金 屬-4)1122。然而，僅為說明的目的而繪示四個金屬化層，且多層內連結構1114可包括任何數量的金屬化層。
第一金屬化層1116、第二金屬化層1118、第三金屬化層1120和第四金屬化層1122的每一者可包括多層結構，如包括內襯或阻障層以及其上方之金屬化層。在一些實施例中，第一金屬化層1116、第二金屬化層1118、第三金屬化層1120及/或第四金屬化層1122包括鈦、鉭或其氮化物的阻障層，及阻障層上方如銅的導電材料。在一些實施例中，第一金屬化層1116、第二金屬化層1118、第三金屬化層1120及/或第四金屬化層1122包括如鈦、鉭、包括鈦、鉭、銅、鋁、鎢或鈷之金屬的氮化物或其他適合的金屬。第一金屬化層1116界面連接接觸結構1112。需說明的是，可插入複數個層於第一金屬化層1116和主動裝置1104之間，此些層包括層間介電層、接觸蝕刻停止層、矽化物特徵，以提供源極/汲極結構1108或閘極結構1106與上方接觸結構1112及/或其他本領域已知的特徵之間的接觸。
介層窗結構1124、介層窗結構1126和介層窗結構1128提供和個別的第一金屬化層1116、第二金屬化層1118、第三金屬化層1120及第四金屬化層1122之間的垂直內連接。介層窗結構1124、介層窗結構1126及/或介層窗結構1128可實質相似於上述方法100中說明的介層窗702A。在一些實施例中，介層窗結構1124、介層窗結構1126及/或介層窗結構1128的材料包括如鈦、鉭、包括鈦、鉭、銅、鋁、鎢或鈷之金屬的氮化物或其他適合的金屬。介層窗結構 1124、介層窗結構1126及/或介層窗結構1128也可為多層特徵。
多層內連結構1114也可包括複數個介電或絕緣層，包含相當於層間介電層的層。多層內連結構1114包括層1130，其可實質相似於前述圖1的方法100所說明的第一層302。在一實施例中，層1130為介電層。在一實施例中，層1130之組成不同於相鄰並共平面的多層內連結構1114的層間介電層(未繪示)之組成。層1130可設置於第一金屬化層1116上，使得層1130實質垂直對準於第一金屬化層1116。例如：層1130的端邊(terminus edge)可實質與第一金屬化層1116的端邊共平面(垂直地)。層1130可延伸為第一金屬化層1116的寬度。介層窗1124延伸穿過層1130的厚度(或高度)。
多層內連結構1114也包括層1132，其也可實質相似於前述圖1的方法100所說明的第一層302。在一實施例中，層1132為介電層。在一實施例中，層1132之組成不同於相鄰並共平面的多層內連結構1114的層間介電層(未繪示)之組成。層1132可設置於第三金屬化層1120上，使得層1132實質垂直對準於第三金屬化層1120。例如：層1132的端邊(terminus edge)可實質與第三金屬化層1120的端邊共平面(垂直地)。層1132可延伸為第三金屬化層1120的寬度。介層窗1128延伸穿過層1132的厚度(或高度)。
多層內連結構1114也包括絕緣層1134A、絕緣層1134B和絕緣層1134C。絕緣層1134A、絕緣層1134B 及/或絕緣層1134C可實質相似於前述圖1的方法100所說明的絕緣層208、絕緣層402A及/或絕緣層904。絕緣層1134A、絕緣層1134B及/或絕緣層1134C可包括四乙氧基矽烷(tetraethyl orthosilicate；TEOS)氧化物、未摻雜的矽酸玻璃，或如硼磷矽酸鹽玻璃(BPSG)、熔融石英玻璃(FSG)、磷矽酸鹽玻璃(PSG)、硼摻雜的矽玻璃(BSG)之摻雜的氧化矽的低介電常數材料，及/或其他適合的介電材料。絕緣層1134A、絕緣層1134B及/或絕緣層1134C的組成包括不同於層1130及/或層1132的組成。具體而言，相對於層1130及/或層1132，絕緣層1134A、絕緣層1134B及/或絕緣層1134C的組成具有蝕刻選擇性。在一些實施例中，一或多個絕緣層1134A、絕緣層1134B及/或絕緣層1134C為氧化物，且層1130及/或層1132為氮化物。需說明的是，絕緣層1134A、絕緣層1134B和絕緣層1134C僅為示例，多層內連結構1114的額外的層間介電層也存在於裝置1100中。具體而言，如上所述，與層1130和層1132的每一者共平面者為個別的層間介電層(即在金屬化層的此些區域中未位於如線1116之導電線上方者)。
需說明的是，裝置1100由多層內連結構1114中示範的點的剖面來表示。在裝置1100的其他剖面點中，實質相似於層1130及/或層1132的層橫向地(例如水平地)與介層窗1124和介層窗1128共平面。相似地，在裝置1100的其他剖面點中，實質相似於絕緣層1134A、絕緣層1134B及/或絕緣層1134C的層橫向地(例如水平地)與介層窗1126 共平面。
雖然並非意欲限制本揭露，本揭露的一或多個實施例對半導體裝置和其形成提供許多優點。例如：本揭露的實施例提供多層內連結構中的導電線上方的第一層。當定義介層窗開口因為重疊失誤(error)而未對準時，第一層限制周圍及/或下層介電層的逆向蝕刻。因此，特定實施例允許加大的介層窗臨界尺寸重疊窗。第一層材料的蝕刻選擇性(如與周圍的介電/絕緣層相比)可提供自對準製程，自對準製程可與後段金屬化製程整合，如前述方法100所說明。一或多個優點也可帶來改善的裝置效能，如因為金屬化特徵之間(如介層窗和下層金屬化層)較大的接觸面積，而造成低接觸阻抗。
在一示例層面中，本揭露指出一個裝置，此裝置包含設於基材上方的導電線；設於基材上方並與導電線共平面的第一介電層；設於導電線上方的第二介電層；設於第一介電層上方的第三介電層；以及，延伸穿過第二介電層並與導電線耦合的介層窗。第二介電層和第三介電層共平面，且第二介電層和第三介電層具有不同組成。
在一實施例中，介層窗的第一側壁與第二介電層界面連接，介層窗的第二側壁與第三介電層界面連接。在又一的實施例中，介層窗的底表面與導電線界面連接，且介層窗的頂表面和另一導電線界面連接。在一實施例中，第二介電層為氮化物，且第三介電層為氧化物。在一實施例中，第一介電層和第三介電層具有相同組成。在一實施例中，第 二介電層為氮化矽。
在此處所示之較廣的實施例的另一者中，方法包括形成導電特徵於第一介電層中，第一介電層設於基材上方，以及形成第二介電層於導電特徵上，並形成第三介電層於第一介電層上。第二介電層和第三介電層具有不同組成。蝕刻介層窗開口於第二介電層中，以從圖案化的第二介電層中暴露出導電特徵。以導電材料填入介層窗開口中。
上述方法的一些實施例中，形成第二介電層包括選擇性地成長材料於導電特徵上。在一些實施例中，形成第二介電層包括形成包括第一組成的第二介電層，第一組成包含矽和氮，以及形成第三介電層包含形成包括第二組成的第三介電層，第二組成包含矽和氧。在又一實施例中，選擇性地成長材料包括形成抑制層於第一介電層的頂表面。在一實施例中，在蝕刻介層窗開口前，平坦化第二介電層和第三介電層。在一實施例中，第二介電層的端邊垂直對準於導電特徵的端邊之上方。在一些實施例中，填入介層窗開口包括沉積阻障層和沉積導電材料於上述阻障層上方。在一實施例中，形成第二介電層包含選擇性地成長氮化矽於導電特徵上。在一實施例中，填入介層窗開口包括在填入導電材料後，進行平坦化製程。
在此處所示之較廣的實施例的另一者中，提供一種方法。上述方法包括形成多層內連結構的第一層。第一層包括第一金屬線和第一介電層。第二介電層形成於第一金屬線上方，且第三介電層形成於第一介電層上方。選擇性地 蝕刻開口於第二介電層中，以暴露出第一金屬線。導電介層窗形成於開口中。然後，形成多層內連結構的第二層(其包括第二金屬線)。導電介層窗內連第二金屬線和第一金屬線。
在另一實施例中，選擇性地蝕刻開口於第二介電層中包括進行蝕刻製程，其以大於第三介電層至少50%的蝕刻率蝕刻第二介電層。在一實施例中，第二介電層垂直對準第一金屬層。在一實施例中，形成第二介電層和第三介電層包括(1)處理第一介電層；(2)選擇性地成長第二介電層於第一金屬線上；(3)於選擇性地成長後，沉積第二材料以形成第三介電層於處理過的第一介電層。處理第一介電層的操作抑制第一介電層上方之第二介電層的成長。在另一實施例中，平坦化第二材料和第二介電層。
前述內容概述多個實施例之特徵，以使於本技術領域具有通常知識者可進一步了解本揭露之態樣。本技術領域具通常知識者應可輕易利用本揭露作為基礎，設計或潤飾其他製程及結構，藉以執行此處所描述之實施例的相同的目的及/或達到相同的優點。本技術領域具有通常知識者亦應可了解，上述相等的結構並未脫離本揭露之精神和範圍，且在不脫離本揭露之精神及範圍下，其可經潤飾、取代或替換。
100:方法
102、104、106、108、110、112、114、116、118、120:方塊

Claims (10)

  1. 一種半導體裝置，包含：一導電線，設於一基材上方；一第一介電層，設於該基材上方並與該導電線共平面；一抑制層，設於該第一介電層的一頂表面上；一第二介電層，設於該導電線上方；一第三介電層，設於該抑制層上方，其中該第二介電層和該第三介電層共平面，且該第二介電層和該第三介電層具有不同組成；以及一介層窗，延伸穿過該第二介電層並耦合至該導電線，其中該介層窗的二個相對側壁與該第二介電層連接，且該介層窗的另二個相對側壁與該第三介電層連接。
  2. 如申請專利範圍第1項所述之半導體裝置，其中該介層窗的一底表面界面連接該導電線，且該介層窗的一頂表面界面連接另一導電線。
  3. 如申請專利範圍第1項所述之半導體裝置，其中該第二介電層為氮化物，該第三介電層為氧化物，該第一介電層和該第三介電層具有相同組成，且該氮化物為氮化矽。
  4. 一種半導體裝置的製造方法，包含：形成一導電特徵於一第一介電層中，其中該第一介電層設於一基材上方； 形成一第二介電層於該導電特徵上和形成一第三介電層於該第一介電層上方，其中該第二介電層和該第三介電層具有不同組成；於該第二介電層中蝕刻一介層窗開口，以從圖案化的該第二介電層中暴露出該導電特徵；以及以一導電材料填入該介層窗開口中。
  5. 如申請專利範圍第4項所述之半導體裝置的製造方法，其中該形成該第二介電層之操作包括選擇性地成長一材料於該導電特徵上，該材料包括氮化矽，且該選擇性地成長該材料之操作包括形成一抑制層(inhibitor layer)於該第一介電層的一頂表面上。
  6. 如申請專利範圍第4項所述之半導體裝置的製造方法，其中該形成該第二介電層之操作包括形成包含一第一組成的該第二介電層，該第一組成包括矽和氮，其中該第二介電層具有一端邊(terminal edge)，且該第二介電層的該端邊垂直對準於該導電特徵的一端邊之上方，該形成該第三介電層之操作包括形成包含一第二組成的該第三介電層，該第二組成包括矽和氧，且該製造方法更包含：於蝕刻該介層窗開口前，平坦化該第二介電層和該第三介電層。
  7. 如申請專利範圍第4項所述之半導體裝置 的製造方法，其中該填入該介層窗開口之操作包含：沉積一阻障層和沉積該導電材料於該阻障層上方；以及在填入該導電材料後，進行一平坦化製程。
  8. 一種半導體裝置的製造方法，包含：形成一多層內連結構的一第一層，其中該第一層包括一第一金屬線和一第一介電層；形成一第二介電層於該第一金屬線上方和形成一第三介電層於該第一介電層上方；於該第二介電層中選擇性地蝕刻一開口，以暴露出該第一金屬線；形成一導電介層窗於該開口中；以及形成該多層內連結構的一第二層，其中該第二層包含一第二金屬線，且該導電介層窗內連接該第二金屬線和該第一金屬線。
  9. 如申請專利範圍第8項所述之半導體裝置的製造方法，其中該第二介電層垂直對準該第一金屬層，且於該第二介電層中選擇性地蝕刻該開口包含進行一蝕刻製程，該蝕刻製程以大於該第三介電層至少50%的一蝕刻率蝕刻該第二介電層。
  10. 如申請專利範圍第8項所述之半導體裝置的製造方法，其中該形成該第二介電層和該第三介電層 的操作包含：處理該第一介電層；選擇性地成長該第二介電層於該第一金屬線上，其中該處理該第一介電層的操作抑制該第一介電層上方之該第二介電層的成長；以及於該選擇性地成長後，沉積一第二材料以形成該第三介電層於處理過的該第一介電層上，且該製造方法更包含：平坦化該第二材料和該第二介電層。
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