TWI769611B - 半導體結構及其製造方法 - Google Patents
半導體結構及其製造方法 Download PDFInfo
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- TWI769611B TWI769611B TW109143259A TW109143259A TWI769611B TW I769611 B TWI769611 B TW I769611B TW 109143259 A TW109143259 A TW 109143259A TW 109143259 A TW109143259 A TW 109143259A TW I769611 B TWI769611 B TW I769611B
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Abstract
本揭露內容描述用於減少無線射頻操作的裝置中或會受益於RC延遲減少的裝置中之RC延遲的方法。此方法包含在基材上形成電晶體結構,電晶體結構具有源極/汲極區、及閘極結構;在基材上沉積第一介電層以埋置電晶體結構;在第一介電層之內,在電晶體結構的源極/汲極區上形成源極/汲極觸點;在第一介電層上沉積第二介電層;在第二介電層中形成金屬線路;在第二介電層中之金屬線路之間形成開口以暴露第一介電層;通過開口,蝕刻金屬線路之間之第二介電層及源極/汲極觸點之間之第一介電層;及沉積第三介電層以在第一介電層及第二介電層中及在電晶體結構之上形成氣隙。
Description
本揭露涉及一種減少RC延遲的半導體結構及其製造方法。
邏輯及記憶體晶片二者中之主動元件(例如,電晶體)皆是採用金屬接線電被連接至彼此及晶片的其他區域。金屬接線中之導線是採用非導電(即電絕緣)介電層彼此分開。在邏輯及記憶體晶片二者中,金屬接線用以將訊號從晶片的一個區域傳輸至另一區域。在提高訊號傳輸速度的同時最大程度降低訊號損耗,對裝置尺寸縮放至關重要。
依據本揭露之部分實施例,一種半導體結構包括:一基材,其具有形成在其上之一第一電晶體及一第二電晶體,其中該第一電晶體及該第二電晶體具有一相等高度,且每個該第一電晶體及該第二電晶體包括源極/汲極區及
一閘極結構;一局部互連接層,其包括分別連接至該第一電晶體及該第二電晶體的該等源極/汲極區及該閘極結構的源極/汲極觸點及閘極觸點,其中該等源極/汲極觸點比該第一電晶體及該第二電晶體的該等閘極結構高;一第一互連接層,在該局部互連接層上,該第一互連接層包括連接至該局部互連接層的該等源極/汲極觸點及該等閘極觸點之金屬線路;以及一氣隙,延伸進入該局部互連接層及該第一互連接層。
依據本揭露之部分實施例,一種半導體結構,包括:一基材,其具有形成在其上之一電晶體結構,其中該電晶體結構包括源極/汲極區及一閘極結構;一局部互連接層,包括連接至該電晶體結構的該等源極/汲極區的源極/汲極觸點;一第一互連接層,設置在該局部互連接層上,該第一互連接層包括連接至該局部互連接層的該等源極/汲極觸點的金屬線路;以及一氣隙,位於該第一互連接層中,其中該氣隙位於在該電晶體結構之上方,並在該第一互連接層的相鄰金屬線路之間延伸。
依據本揭露之部分實施例,一種半導體結構的製造方法,包括以下步驟:在一基材上形成一電晶體結構,其中該電晶體結構包括設置在該基材中之源極/汲極區及一閘極結構;在該基材上沉積一第一介電層以埋置該電晶體結構;在該第一介電層之內,在該電晶體結構的該等源極/汲極區上形成源極/汲極觸點;在該第一介電層上沉積一第二介電層;在該第二介電層中形成金屬線路以連接至該等
源極/汲極觸點;在該第二介電層中之該等金屬線路之間形成一開口以暴露該第一介電層;通過該開口,蝕刻該等金屬線路之間的該第二介電層及該等源極/汲極觸點之間的該第一介電層,以形成一延伸開口;以及沉積一第三介電層以密封該延伸開口並在該第一介電層及該第二介電層中及在該電晶體結構之上形成一氣隙。
θ:側壁角度
A,B:電晶體結構
A':第一晶片區域
A":第二晶片區域
H1~H3:高度
K/R:晶片區域
100:通道區
102:基材
102':介電層
105:源極/汲極區
110:閘極結構
110a:閘極電極
110b:介電堆疊
115a,115b:間隔件
120:矽化物層
125:源極/汲極觸點
130:閘極觸點
135:第一金屬化層
135a,155a,160a:金屬線路
140:氣隙
140a:內襯
140b:夾點/圓形頂表面
140bh:高度
145:層間介電質/ILD
150:金屬間介電質/IMD
155:第二金屬化層
155h:高度
155b,160b:通孔
160:第三金屬化層
165:蝕刻停止層
170:蝕刻停止層
400:方法
410~450:操作
600:開口
600t,800t:頂部開口
600b:底部開口
605:距離
800:延伸開口
當與附圖一起閱讀時,可由下文實施方式最佳地理解本揭露內容的態樣。注意到根據此行業中之通常實務,各種特徵並未按比例繪製。實際上,為了論述的清楚性,可任意增加或降低各種特徵的尺寸。
第1A至3圖為根據一些實施例,具有減少高度及形成在電晶體結構之上之氣隙之局部觸點的截面視圖。
第4至5圖為根據一些實施例,用於具有減少高度及在電晶體結構之上之氣隙之局部觸點的形成方法的流程圖。
第6圖為根據一些實施例,在電晶體結構之上之氣隙產製期間之中間結構的截面視圖。
第7圖為根據一些實施例,在電晶體結構之上之氣隙產製期間之中間結構的頂部視圖。
第8至10圖為根據一些實施例,在電晶體結構之上之氣隙產製期間之中間結構的截面視圖。
第11至16圖為根據一些實施例,具有減少高度及形成在電晶體結構之上之氣隙之局部觸點的截面視圖。
以下揭露內容提供用於實行所提供的標的的不同特徵的許多不同的實施例或範例。下文描述組件及佈置的特定範例以簡化本揭露內容。當然,此等僅為範例且未意圖具限制性。舉例而言,在下文的描述中,在第二特徵之上之第一特徵的形成可包含以直接接觸方式形成第一特徵及第二特徵的實施例,且亦可包含在第一特徵與第二特徵之間所形成的額外特徵的實施例,使得第一特徵及第二特徵並不直接接觸。此外,在各種範例中,本揭露內容可能重複元件符號及/或字母。此重複本身並不規範所論述的各種實施例及/或配置之間之關係。
再者,為了便於描述,本文中可使用諸如「在...之下」、「在...下方」、「較低」、「在...上方」、「較高」、及類似者的空間相對術語來描述圖示中所示意之一個元件或特徵與另一元件(等)或特徵(等)的關係。除了圖示中所描繪的方位之外,空間相對術語亦意圖涵蓋元件在使用或操作中之不同方位。設備能以其他方式定向(旋轉90度或以其他定向),且本文中使用的空間相對描述語可同樣以相應的方式解釋。
如本文所用,術語「象徵性」是指在產品或程序的設計階段針對組件或程序操作的特徵或參數所設定的符合
需求的值或目標值,以及高於、等於、及/或低於符合需求的值的範圍。值的範圍通常歸因於製造程序或公差的微小變化。
在一些實施例中,術語「約」及「大致上」可表示給定數量在5%範圍(例如,值之±1%、±2%、±3%、±4%、±5%)之內變化的值。此等僅為範例且未意圖具限制性。應當理解,術語「約」及「大致上」可指根據本文的教導,藉由熟習此項技藝者(等)所解釋之值的百分比。
如本文所用,術語「垂直」意指象徵性地垂直於基材的表面。
邏輯及記憶體導線中訊號傳播的速度取決於電阻及電容的乘積,通常稱作「RC延遲」。降低電阻及電容會是達成在晶片之內快速傳播訊號之理想選擇。在無線射頻(RF)下操作的裝置(諸如RF開關、及低噪聲放大器(LNA))特別容易受到RC延遲的影響,此現象會因裝置縮放而加劇。舉例而言,歸因於後端(BE)電阻及電容的作用,RF切換裝置可能展現不良的RC性能。此乃因BE中之寄生電容會致使操作過程中之不良隔離,而導線電阻會致使高插入損耗(例如,輸入/輸出訊號損耗)及不良的操作速度。
本文中所述之實施例是針對用於減少無線射頻操作的裝置中或會受益於RC延遲減少的其他裝置中之RC延遲的方法。在一些實施例中,此方法包含形成具有減少高度的局部互連接,並於局部互連接中之觸點及BE金屬
化層(此文中也稱作「互連接層」)之間引入氣隙以解決RC延遲。本文中所述之實施例可全局地(例如,應用於晶片的所有區域)或選擇性地(例如,應用於晶片的選擇性區域)實行。經由範例且並非限制性,在電晶體級(例如,在局部互連接之間)處所形成的氣隙佔據約30%與約70%之間的可用體積,且在電晶體級(例如,在BE內之第一金屬化層之內)之上方所形成的氣隙佔據約40%與約90%之間的可用體積。注意上述範圍並非為限制性的,且此等範圍之外的值亦在本揭露內容的精神及範圍之內。在一些實施例中,在電晶體級處、電晶體級之上方、此兩個位置中、及/或其他適用位置形成氣隙。在進一步實施例中,源極/汲極觸點比電晶體的閘極結構的高度高。在一些實施例中,源極/汲極觸點的高度約為(包含任何介入矽酸鹽層之)電晶體閘極結構的高度的2.5倍。源極/汲極觸點與電晶體閘極之其他高度比亦在本揭露內容的精神及範圍之內。在一些實施例中,減少閘極觸點的高度以改善觸點電阻。在一些實施例中,局部互連接在高度上之減少及氣隙存在的組合,在電路中達成最佳RC延遲減少。
根據一些實施例,第1A圖為形成在第一晶片區域A'中之示例性電晶體結構A的局部截面視圖。在一些實施例中,在基材102的一部分上形成電晶體結構A。經由範例且並非限制性,電晶體結構A可為平面電晶體結構或非平面電晶體結構,如在基材102的鰭結構上形成的鰭式場效電晶體(FinFET)。經由範例且並非限制性,電晶體
結構A包含通道區100、源極/汲極區105、閘極結構110、及間隔件115a及115b。在一些實施例中,如第1A圖及第1B圖(此二圖為晶片區域A'及A"的示例性佈局圖)中所示,來自電晶體結構A的垂直結構110及間隔件115a及115b在(設置在基材102上之介電層102'上之)第二晶片區域A"中延伸。在一些實施例中,閘極結構110進一步包含閘極電極110a及閘極介電堆疊110b。在晶片的其他區域中形成如同電晶體結構A的額外電晶體結構。為了簡單的目的,未在第1A圖中顯示此等額外的電晶體結構。經由範例且並非限制性,電晶體結構A可為RF電路(諸如RF切換電路、或LNA電路)的部分。替代地,電晶體結構A可為DC電路的部分,DC電路的操作會受到RC延遲的影響。
根據一些實施例,若閘極結構110包含多晶矽,在每個源極/汲極區105及閘極結構110上形成矽化物層120以減少第一晶片區域A'中之源極/汲極觸點125與源極/汲極區105之間之觸點電阻並減少第二晶片區域A"中之閘極觸點130與閘極結構110之間之觸點電阻。第一晶片區域A'中之源極/汲極觸點125及第二晶片區域A"中之閘極觸點130形成觸點結構的網路,在本文中統稱作局部互連接。
在一些實施例中,若閘極電極110a包含多晶矽,則在閘極結構110上所形成的矽化物層120與閘極電極110a直接接觸。在一些實施例中,若閘極電極110a包含
金屬堆疊,則省略矽化物層120,且閘極介電堆疊110b包含高k介電材料一例如,具有大於約3.9的介電常數(k值)的介電材料。
在一些實施例中,將局部互連接的觸點,如同源極/汲極觸點125及閘極觸點130般被縮短(例如,舉例而言,在z方向上減少高度)以減少觸點電阻一例如,減少RC電阻的電阻分量。舉例而言,已相對於源極/汲極觸點125及閘極觸點130原始高度縮短源極/汲極觸點125及閘極觸點130的各別高度H1及H3。根據一些實施例,源極/汲極觸點125的高度H1大於高度H2、等於或小於約2.5倍高度H2(例如1<H1/H22.5),其中H2,如本文中所述,界定成閘極結構110的高度,此高度包含閘極結構110上之二氧化矽結構層120的厚度。同樣地,高度H3現在等於或大於約0.25倍高度H2,且等於或小於大約1.5倍高度H2(例如,0.25<H3/H21.5)。如第1A圖中所示,從觸點的底部表面至觸點的頂部表面分別量測源極/汲極觸點125的高度H1及閘極觸點130的高度H3。
由於源極/汲極觸點125及閘極觸點130現在更短,第一金屬化層135被形成得更靠近電晶體結構A。這繼而增加在金屬線路135a及閘極結構110之間所形成的寄生電容,此舉影響電路的RC延遲。在一些實施例中,為了補償隨後增加的寄生電容,形成通過(第一晶體區域A'之內之電晶體結構A的晶體結構110之上之)層間介電質(ILD)145及金屬間介電質(IMD)150的氣隙140。在
一些實施例中,繞著電晶體結構A的晶體結構110及局部互連接(例如,源極/汲極觸點125及閘極觸點130)形成ILD 145,作為電隔離的手段。同樣地,形成IMD 150作為第一金屬化層135的金屬線路135a之間之電隔離的手段。歸因於氣隙140的形成程序及IMD 150的沉積特性,氣隙140可延伸至第二金屬化層155的IMD 150,此第二金屬化層155包含金屬線路155a及金屬垂直互連接存取線路(「通道」)155b。金屬化層,諸如第一金屬化層135及第二金屬化層155,在本文中亦統稱作全局互連接、全局互連接層、或互連接層。在一些實施例中,氣隙140並未延伸進入第二晶片區域A"。因而,氣隙140與閘極觸點130之間沒有重疊。
經由範例且並非限制性,第1B圖為上文參照第1A圖所論述之晶片區域A'及A"的佈局圖。第1B圖的佈局圖示出第1A圖之選擇性元件。在一些實施例中,第1A圖中所示的晶片區域A'的截面視圖對應至沿第1B圖的C-D線截取的截面視圖。據此,第1A圖中所示的晶片區域A"的截面視圖對應至沿第1B圖的E-F線截取的截面視圖。如第1B圖中所示且如上文所論述,在第一晶片區域A'中形成藉由虛線所表示的氣隙140,且氣隙140並未延伸進入第二晶片區域A"。其結果為,氣隙140與閘極觸點130之間沒有重疊。
如第1A圖中所示,氣隙140的內部表面被襯有內襯140a。在一些實施例中,內襯140a包含一個或更多
個介電層,諸如如氮化矽(Si3N4);碳化矽(SiC);Si3N4及SiC的堆層;ILD、Si3N4、及IMD的堆層;ILD、Si3N4、SiC、及IMD的堆層;或其等的任何組合。
在一些實施例中,在第二金屬化層155之上形成額外的金屬化層,諸如具有金屬線路160a及通孔160b之第三金屬化層160。經由範例且並非限制性,金屬化層可藉由蝕刻停止層165所分開。再者,如第1A圖中所示,可在第一晶片區域A'及第二晶片區域A"中之閘極結構100上分別形成觸點蝕刻停止層170。再者,觸點蝕刻停止層170可在(配置在第一晶片區域A'中之源極/汲極區105上及配置在第二晶片區域A"中之介電層102'上之)矽化物層120上延伸。蝕刻停止層(例如,蝕刻停止層165及觸點蝕刻停止層170)促進局部及全局互連接(諸如源極/汲極觸點125、閘極觸點130、金屬線路135a、及通孔155b/160b)的形成。在一些實施例中,在第1A圖的結構之間可形成額外的蝕刻停止層。為了簡單的目的,未在第1A圖中顯示此等額外蝕刻停止層。為便於說明,可能未在第1A圖中顯示額外層,諸如金屬線路中所包含的屏障層、通孔及觸點、閘極觸點110a中之功官能層、介電堆疊110b中之介電層、封蓋層、或隔離結構中。
在一些實施例中,ILD 145中之氣隙140佔據源極/汲極觸點125與電晶體結構A之間約30%及約70%之間的可用空間。另外地,第一金屬化層135中之氣隙140佔據第一金屬化層135的金屬線路135a之間約40%與約
90%之間的可用空間。在一些實施例中,氣隙140的形狀可與第1A圖中所示的形狀不同。舉例而言,氣隙140的最底部部分可朝向設置在源極/汲極區105上的矽化物層120延伸,或可佔據源極/汲極觸點125與蝕刻停止層170之間之整個空間。在一些實施例中,IMD 150中之氣隙140的體積大於ILD 145中之氣隙140的體積。在一些實施例中,當與較短的S/D觸點125及閘極觸點130組合時,ILD 145中佔據小於30%之氣隙以及第一金屬化層135中佔據小於40%之氣隙可能不足以減少RC延遲。另一方面,在一些實施例中,ILD 145中佔據大於約70%之氣隙以及第一金屬化層135中佔據大於約90%的氣隙可能損害ILD 145及第一金屬化層135的機械強度。
根據一些實施例,並為了進一步減少寄生電容及RC延遲,氣隙140可如第2圖中所示(例如,沿z方向)延伸至第二金屬化層155及第三金屬化層160。在一些實施例中,與僅延伸進入第一金屬化層135的氣隙相比,將氣隙140延伸進入第二金屬化155進一步減少寄生電容及RC延遲。在一些實施例中,例如,與僅延伸進入第二金屬化層155的氣隙相比,將氣隙140延伸進入第三金屬化層160進一步減少寄生電容及RC延遲。在一些實施例中,氣隙140的所有部分皆可在單個或多個操作中形成,如將於後文所論述者.在其他實施例中,可能未在ILD 145中形成氣隙140。舉例而言,如第3圖中所示,可選擇性地在第一金屬化層135中形成氣隙140,且氣隙140部分地
延伸至第二金屬化層155。因而,可在不同的位置中選擇性地形成氣隙140以抑制寄生電容的形成。
第4圖及第5圖為參照第1A圖中所示之實施例,用於上文所論述具有減少高度及氣隙的局部互連接的形成產製方法400的流程圖。方法400的修改可用於形成第2圖及第3圖中所示實施例的氣隙。可在方法400的各種操作之間進行額外產製操作,並僅因清楚及容易描述的目的而可省略此等額外產製操作。此等額外的產製操作亦在本揭露內容的精神及範圍之內。再者,並不需要進行本文所提供之揭露內容的所有操作。此外,可同時進行此等操作中的一些操作,或以與第4圖及第5圖中所示操作之不同順序進行。在一些實施例中,在本文所描述的操作外,亦可進行一個或更多個其他操作、或本文所描述的操作可被一個或更多個其他進行的操作所取代。為了說明的目的,將參考第6圖至第10圖中所示的實施例描述方法400。提供描述方法400的圖示僅為了說明目的,且未按比例繪製。為了說明的目的,可能故意增加了一些結構、薄膜、或幾何形狀。
在參閱第4圖中,方法400開始於操作410及在基材上形成電晶體結構(如同第6圖中所示的半導體基材102上的電晶體結構A)的程序。在一些實施例中,第1A圖及第6圖中所示的電晶體結構A大致類似。經由範例且並非限制性,半導體基材102可為塊狀半導體晶圓(例如,矽晶體)、絕緣體上的半導體(SOI)晶圓、或在塊狀半導體
晶圓或SOI晶圓上形成的半導體鰭片結構。在一些實施例中,若在鰭結構上形成電晶體結構A,則此等鰭結構將具有沿著第1A圖及第6圖的x方向之長度,以及沿著第1A圖及第6圖的y方向之寬度。在一些實施例中,通道區100可為半導體基材102的部分,或可為在半導體基材102上所形成或來自半導體基材102的半導體鰭片結構的部分。源極/汲極區105包含在半導體基材102的凹入部分或半導體鰭片結構的凹入部分中所形成的一個或更多外延層(例如,外延生長的矽鍺層、或摻雜有碳及磷、或碳及砷的外延生長的矽層)。在一些實施例中,源極/汲極區105僅為半導體基材102的摻雜區。在一些實施例中,矽化物層120為沉積金屬及下層矽原子(若存在)之間之矽化程序的產物。若不存在矽原子,將不會發生矽化物形成。舉例而言,若閘極電極100a為包含金屬功官能層及金屬填充物的金屬堆疊,則不在氮化物結構110上形成矽化物層120。然而,矽化物形成對於源極/汲極區105至關重要。在一些實施例中,閘極電極110a可包含摻雜的多晶矽或,替代地,金屬層。當閘極電極110a為金屬時,則閘極介電堆疊110b包含高k介電材料以提供最佳性能。金屬層包含一個或更多個功官能層及金屬填充物材料。
參閱第4圖及第6圖,方法400繼續至操作415及在第一晶片區域A'及第二晶片區域A"中之電晶體結構A的閘極結構110上分別沉積觸點蝕刻停止層170的程序。由於,觸點蝕刻停止層170促進局部互連接的形成,可將
觸點蝕刻停止層170全面地沉積在晶片將形成局部互連接(例如,源極/汲極及閘極觸點)之處的區域之上。經由範例且並非限制性,觸點蝕刻停止層170包含氮化物、Si3N4、及任何其他合適的材料,它們對周圍的材料(例如,ILD 145)提供良好的蝕刻選擇性。
參閱第4圖,方法400繼續至操作420及將ILD 145沉積在觸點蝕刻停止層170上的程序,以埋置如第6圖中所示之電晶體結構A。如上文所論述,ILD 145將電晶體結構A的閘極結構110與隨後形成的局部互連接(例如,源極/汲極接頭125)電隔離。經由範例且並非限制性,ILD 145可為摻雜有碳且包含氮、氫、或任何其他合適的介電材料的基於矽的介電質(例如,氧化矽)。ILD 145可藉由任何適當的沉積方法,諸如化學氣相沉積(CVD)、電漿增強CVD(PECVD)、可流動CVD等所沉積。
參閱第4圖及第6圖,方法400繼續至操作425及在第一晶片區域A'中形成源極/汲極觸點125並在第二晶片區域A"中形成具有符合需求的高度之閘極觸點130的程序425。如先前關於第1A圖所討論,調整源極/汲極觸點125及閘極觸點130的各自高度H1及H3,以便源極/汲極觸點125的高度H1大於高度H2且等於或小於約2.5倍高度H2(例如,1<H1/H22.5)、且閘極觸點130的高度H3等於或大於約0.25倍高度H2等於或小於約1.5倍高度H2(例如,0.25<H3/H21.5)。這些高度(及高度比)非為限制性,且其他值亦在本揭露內容的精神及範
圍之內。如上文所論述,在一些實施例中,大於約2.5倍高度H2之源極/汲極觸點125以及具有大於約1.5倍高度H1的高度H3之閘極觸點更具電阻性,並因而增加RC延遲的電阻分量。再者,在一些實施例中,比高度H2短之源極/汲極觸點125以及比0.25倍高度H2短之閘極觸點130,增加金屬線路135a與閘極結構110之間所形成的寄生電容,此舉並不符合需求。
有多種方法可實現上述高度比。經由範例且並非限制性,一種方法包含沉積厚的ILD 145(例如,比符合需求的高度H1及H3厚)、採用微影製程及蝕刻操作在ILD 145中形成開口、採用導電材料填充觸點開口、並以適當的量平面化ILD 145,以達成符合需求的H1及H3之比。舉例而言,可採用化學機械拋光(CMP)程序來達成ILD 145的平面化。若CMP程序引入不符需求的跨晶片厚度變化,一種替代方法包含將ILD 145沉積至更接近符合需求高度H1及H3的厚度,以便CMP程序在拋光期間中去除較少量的ILD材料。上述方法為示例性的而非限制性的。替代方法為可能的,且亦在本揭露內容的精神及範圍之內。
注意到用於形成各別源極/汲極觸點125及閘極觸點130的觸點開口的蝕刻化學物質,與ILD 145(例如,氮化矽)相比,被配置成對觸點蝕刻停止層170(例如,氮化矽)展現低選擇性。此舉為有益的,因為它促進具有不同高度之觸點形成。舉例而言,同時形成源極/汲極觸點開口
及閘極觸點開口。然而,由於閘極開口比源極/汲極觸點開口短,因此會首先形成閘極觸點開口。當源極/汲極觸點開口持續被蝕刻化學物質蝕刻時,由於蝕刻化學物質無法蝕刻通過觸點蝕刻停止層170,因此,蝕刻觸點開口的蝕刻會大量地減慢。當形成源極/汲極及閘極開口二者時,可將蝕刻化學物質轉換至不同的化學物質,此化學物質現在對觸點蝕刻停止層170為選擇性,以便可去除蝕刻停止層並暴露下層之層(例如,閘極電極110a及源極/汲極區105)。可基於形成源極/汲極觸點開口所需的額外時間來調整蝕刻停止層170的厚度。取決於整合方案,在一些實施例中,源極/汲極區105上的矽化物層120可在源極/汲極開口形成之後形成。
參閱第4圖,方法400繼續至操作430及在ILD 145上形成第一金屬化層的程序。參閱第1A圖,舉例而言,可藉由在拋光的ILD 145上沉積蝕刻停止層165而形成第一金屬化層135;隨後將IMD 150沉積在蝕刻停止層165上;在IMD 150及蝕刻停止層165中蝕刻開口,以暴露下層局部互連接;沉積一個或更多個導電材料以填充開口並形成線路135a;及拋光移除在IMD 150之上之多餘沉積材料,以便線路135a的頂部表面與IMD 150的頂部表面共平面,如第1A圖中所示。
如同觸點蝕刻停止層170,蝕刻停止層165亦可包含氮化物,如Si3N4。再者,如同ILD 145,IMD 150可為類似之基於氧化矽的介電質;諸如,含有氫或氮的碳
摻雜氧化矽。在一些實施例中,IMD 150可為(舉例而言,如同具有毛孔之氧化矽的)多孔材料。根據一些實施例,用於填充線路135a的導電材料與用於填充源極/汲極觸點125及閘極觸點130的導電材料不同。經由範例且並非限制性,可採用銅填充線路135a,而可採用鈷或鎢填充源極/汲極觸點125及閘極觸點130。再者,線路135a可比源極/汲極觸點125及閘極觸點130大(例如,更寬)。
參閱第5圖,方法400繼續至操作435及在第一金屬化層135中形成開口以暴露電晶體結構A之上之ILD 145的程序。在一些實施例中,在操作435中形成的開口將用於形成第1A圖中所示之氣隙140在第一晶片區域A'中形成操作435的開口,且如上文所論述,開口並未延伸至第二晶片區域A"。經由示例且並非限制性,可藉由在IMD 150上沉積光阻劑、圖案化光阻劑、並通過光阻劑中的開口蝕刻第一金屬化層135的IMD 150,來形成開口。在第一金屬化層135中的開口形成之後,舉例而言,可採用濕式蝕刻程序去除光阻劑。所得的結構如第6圖中所示,其中在第一金屬化層135的IMD 150中形成開口600以暴露ILD 145。在一些實施例中,在ILD 145中部分地形成開口600。
根據一些實施例,開口600的側壁角度θ可為約90°、大於約90°(例如,110°)、或小於約90°(例如,80°)。在一些實施例中,側壁角度θ為約90°±20°。然而,此等角度非為限制性,且開口600可形成具有大於110º
或小於約80º的角度。經由範例且並非限制性,開口600可具有頂部開口600t大致上等於底部開口600b(例如,600t=600b)之大致上垂直的側壁、頂部開口600t比底部開口600b(例如,600t>600b)寬之正錐度輪廓、或可具有頂部開口600t比底部開口600b窄(例如600t<600b)之負錐度輪廓。開口600的輪廓在一定程度上決定了操作450中所形成的氣隙的形狀。在一些實施例中,頂部開口600t在相鄰線路135a之間之距離605的約25%與約30%之間。然而,此等百分比非為限制性,且可形成更寬或更窄的頂部開口600t。
注意到可在其他電晶體結構之上之晶片的其他位置中之第一金屬化層135之內形成如同開口600的額外開口。經由範例且並非限制性,第7圖為第6圖中的電晶體結構A的頂部視圖。第7圖示出第6圖的選擇性部分,且僅因清楚的目的而省略其他部分。與第1A圖及第1B圖的情況類似,第6圖中所示的晶片區域A'的截面視圖對應至沿第7圖的C-D線截取的截面。據此,第6圖中所示的晶片區域A"的截面視圖對應至沿第7圖的E-F線截取的截面。如第7圖中所示且如上文所論述,在第一晶片區域A'中形成藉由虛線表示的開口600,且開口600並未延伸進入第二晶片區域A"。其結果為,開口600與閘極觸點130之間沒有重疊。第7圖的頂部視圖為示例性而非為限制性。因而,第6圖的元件之不同佈置皆為可能的且亦在本揭露內容的精神及範圍之內。在一些實施例中,沿y方向的開
口600的尺寸可界定該方向上氣隙的橫向尺寸。
參閱第5圖,方法400繼續至操作440及通過開口600移除第一金屬化層135中的一部分IMD 150及一部分ILD 145的程序,以形成如同第8圖中所示的延伸開口之延伸開口800。在一些實施例中,除了第8圖的截面視圖中所示的x-z平面外,延伸開口800亦沿y方向延伸。在一些實施例中,用來形成延伸開口800的蝕刻程序,包含乾式蝕刻化學物質、濕式蝕刻化學物質、或其等的組合。根據一些實施例,蝕刻化學物質為等向性、或等向性及異向性的組合,此蝕刻化學物質對基於氧化矽的材料(諸如IMD 150及ILD 145)具有高選擇性,而對蝕刻停止層165及蝕刻停止層170(例如,氮化矽或氮化物材料)具有低選擇性。此外,蝕刻化學物質配置成對線路135a及源極/汲極觸點125中使用的材料展現低選擇性。在一些實施例中,歸因於蝕刻程序的等向性,延伸開口800可能發展成彎曲或圓形的內部表面(例如,凸面或凹面)、直內部表面或其組合。由於相同的原因,延伸開口800可能發展成尖角、圓角或其等的組合。因而,延伸開口800的形狀可偏離第8圖中所示的形狀。
經由範例且並非限制性,乾式蝕刻化學物質可基於碳氟化合物化學物質,並可包含四氟甲烷(CF4)、八氟丙烷(C3F8)、八氟環丁烷(C4F8),氟仿(CHF3)、三氟化氮(NF3)、三氟化硫(SF3)或其等的組合。乾式蝕刻化學物質可亦包含緩沖氣體,諸如氬氣(Ar)或氦氣(He)。可藉
由氣體混合物中之氫氣或氧氣添加物微調乾式蝕刻化學物質的選擇性。
經由範例且並非限制性,濕式蝕刻化學物質可包含在氟化銨(NF4F)中緩衝的氫氟酸(HF),這被稱作緩衝氧化物蝕刻(BOE)或緩衝HF(BHF)。氧化矽為無定形材料,當被暴露於BOE時會等向性地蝕刻。
蝕刻程序可以預設時間,以便可控制延伸開口800的尺寸。在一些實施例中,延伸開口800可在觸點蝕刻停止層170與源極/汲極觸點125之間延伸至區域805,如上文所論述。
參閱第5圖,方法400繼續至操作445及在延伸開口800中沉積內襯(例如,如同第1A圖中所示的內襯140a)的程序。經由範例且並非限制性,第9圖示出被沉積在延伸開口800中的內襯140a。在一些實施例中,內襯140a亦被沉積在外部延伸開口800外部(例如,在蝕刻停止層165的水平表面上)。然而,若符合需求,如第10圖中所示,可經由異向性蝕刻操作去除在延伸開口800外部的內襯140a部分。如上文所論述,內襯140a包含單一層或介電層的堆層。舉例而言,內襯140a包含一個或更多個介電層,例如Si3N4;SiC;Si3N4及SiC的堆層;ILD、Si3N4及IMD的堆層;ILD、Si3N4、SiC及IMD的堆層;或其等的任何組合。經由範例且並非限制性,內襯140a的厚度在約10nm與約50nm的範圍之間。內襯140a並未填充延伸開口800,而是覆蓋開口800的內部
側壁(或內部側壁表面),如第10圖中所示。歸因於內襯140a的沉積,延伸開口800的頂部開口800t減少了相當於上方蝕刻停止層165的側壁上之內襯的140a厚度的量。在一些實施例中,且在沉積襯裡140a之前,當用於形成延伸開口800的蝕刻化學物質並未腐蝕蝕刻停止層165,頂部開口800t大致上等於第6圖中所示之開口600的頂部開口600t。
在一些實施例中,採用共形沉積程序,諸如原子層沉積(ALD)、電漿輔助ALD(PEALD)、化學氣相沉積(CVD)、電漿輔助CVD(PECVD)、或任何有能力在約10nm與約50nm之間之組合厚度下沉積共形層的沉積程序,來沉積內襯140a。
參閱第5圖,方法400繼續至操作450及在第一金屬化層135上形成第二金屬化層(例如,第1A圖中所示的第二金屬化層155)的程序,以密封延伸開口800並形成氣隙140。在參閱第1A圖中,舉例而言,可藉由在成第一金屬化層135的MID150上沉積另一蝕刻停止層165而形成第二金屬化層155;蝕刻IMD 150及蝕刻停止層165以暴露下層金屬線路135a並形成局部通孔及線路開口;沉積一個或更多個導電材料以填充通孔及線路開口,舉例而言,採用雙鑲嵌程序以形成通孔155b及金屬線路155a;及拋光移除在IMD 150之上之多餘沉積材料,以便金屬線路155a的頂部表面與IMD 150的頂部表面共平面,如第1A圖中所示。在一些實施例中,可在第二
金屬化層155上形成額外金屬層(例如,如第三金屬化層160)。
根據一些實施例,在第二金屬化層155的IMD 150的沉積期間,如第1A圖中所示,在IMD 150之內形成夾點或圓形頂表面140b。夾點或圓形頂表面140b可歸因於IMD沉積早期階段期間藉由IMD材料的懸伸部形成所致。在一些實施例中,第1A圖中所示的夾點或圓形頂表面140b為第2圖及第3圖(及隨後的第11圖至第16圖)中所示的氣隙140的特徵。在一些實施例中,夾點或圓形頂表面140b並未延伸進入超過相鄰金屬化層約60%的高度之相鄰金屬化層。舉例而言,在第1A圖中,夾點或圓形頂表面140b的高度140bh小於第二金屬化層155的高度155h的約60%(例如,140bh<0.6<155h)。當懸伸部如第10圖中所示關閉頂部開口800t時,可防止IMD材料在延伸開口800中的沉積。因而,頂部開口800t及IMD 150的沉積速率促進第1A圖中所示之氣隙140的形成。
經由範例且並非限制性,可藉由開口600(更具體而言,藉由第6圖中所示的頂部開口600t)調節頂部開口800t。在一些實施例中,可基於IMD 150的沉積速率來調整側壁角θ,以促進氣隙140的形成。舉例而言,具有頂部開口600t比底部開口600b(例如,600t>600b)寬的正錐形輪廓可適用於高沉積速率程序。同時,具有頂部開口600t比底部開口600b窄的負錐度輪廓(例如,600t
<600b)可適用於較低的沉積速率程序。再者,開口600的負錐度輪廓表示頂部開口800t會更小,並在沉積IMD 150期間會更快地密封。經由範例且並非限制性,可藉由用於形成開口600的圖案化及蝕刻程序來調整開口600的尺寸及輪廓,這在第5圖的操作435中所描述。
如上文所論述,頂部開口800t的尺寸與頂部開口600t的尺寸有關。再者,如上文所論述,頂部開口600t可被,舉例而言,在第6圖中所示的相鄰線路135a之間之距離605的約25%與約30%之間。在一些實施例中,若頂部開口600t小於距離605的約25%,用於形成延伸開口800的蝕刻化學物質可能無法到達ILD 145或可能需要更長的蝕刻時間,這並不符需求。另一方面,在一些實施例中,若頂部開口600t大於距離605的約30%,因為可將IMD材料沉積在第8圖中所示的延伸開口800中並填充第8圖中所示的延伸開口800,故第1A圖中所示的氣隙140的形成可能具有難度。
方法400的修改可用於形成第2圖中所示的氣隙140。在一些實施例中,為了產生第2圖中所示的氣隙,此方法可形成第一金屬化層135及第二金屬化層155;在第二金屬化層155中形成開口600,此開口600延伸至第一金屬化層135及ILD 145;在第二及第一金屬化層的IMD 150之內、及ILD 145之內形成延伸開口;沉積內襯140a;並形成第三金屬化層160。產生第2圖中所示的氣隙的替代方法為將第1A圖中所示的氣隙140延伸至
第二金屬化層155。舉例而言,從第1A圖中所示的氣隙140開始,在第三金屬化層160形成之前,在第二金屬化層155中形成開口600,以暴露第一金屬化層135中的氣隙140,而在第二金屬化層155中形成延伸開口800;在新的延伸開口800中沉積內襯140a;及形成第三金屬化層160以形成第2圖中所示的氣隙140。在一些實施例中,藉由在第2圖的第二金屬化層155中用於形成氣隙140的蝕刻化學物質,第1A圖的氣隙140中之現有內襯104a,保護第一金屬化層135中之周圍IMD 150及ILD 145不致進一步蝕刻。
在一些實施例中,方法400的修改可用於形成第3圖中所示的氣隙140。在一些實施例中,當第6圖中所示及操作435中所述之開口600停止在ILD 145上方的蝕刻停止層165時(例如,當開口600未暴露ILD 145時),形成第3圖中所示的氣隙。若開口600未暴露ILD 145,則在操作440中使用的後續蝕刻程序將不會去除ILD 145。採用前述修改,操作440、445、及450將導致第3圖中所示的氣隙140。
方法400的上述修改非為限制性且及替代修改皆為可能的。方法400的此等替代修改亦在本揭露內容的精神及範圍之內。
經由範例且並非限制性,第11圖至第16圖為根據上文所述之方法400的操作、或修改操作,在第一晶片區域A'中類似的電晶體結構A及B之上所形成之氣隙140
的範例。舉例而言,在第11圖中,電晶體結構A及B具有延伸通過第二金屬化層155、第一金屬化層135、及ILD 145的氣隙140。在第12圖中,在電晶體結構A及B之上形成第一金屬化層135及第二金屬化層155中的氣隙140。在第13圖中,在電晶體結構A之上選擇性地形成氣隙140,而相鄰的電晶體結構B之上則未包含氣隙。在第14圖中,如同在第11圖中,在電晶體結構A及B二者上皆形成氣隙140;然而,第二金屬化層155及第三金屬化層160的接線佈局與第11圖中所示的不同。在第15圖中,兩個電晶體結構A及B皆具有延伸通過第三金屬化層160、第二金屬化層155、第一金屬化層135、及ILD 145之氣隙140。最後,第16圖為兩個具有類似電晶體結構A及B之晶片區域K及R的截面視圖。在一些實施例中,晶片區域K與上文所論述之第一晶片區域A'大致類似,其中源極/汲極觸點125的高度H1配置成,舉例而言,大於高度H2並等於或小於約2.5倍高度H2。再者,在電晶體結構A之上形成氣隙140。反之,在晶片區域R中,源極/汲極觸點125'比約2.5倍高度H2高且在電晶體結構B之上並沒有氣隙。經由範例且並非限制性,晶片區域K之內的電晶體結構A為對RC延遲敏感的RF電路的部分,且因此較短的源極/汲極觸點125及氣隙140可減少RC延遲。另一方面,晶片區域R中的結構B為對RC延遲較不敏感的電路的部分。在一些實施例中,晶片區域K及R可彼此相鄰,並藉由隔離區1600分所開或藉由晶片
的其他區域所分開。第16圖的範例表明,方法400可應用於晶片的選定部分/區域,以減輕與RC延遲有關的問題。
除了上文之外,第1至3圖及第11至16圖中描述的實施例的不同排列為可能的,且亦在本揭露內容的精神及範圍之內。
本文中所述之實施例是針對用於減少無線射頻操作的裝置中或會受益於RC延遲減少的其他裝置中之RC延遲的方法。在一些實施例中,該方法包含形成局部互連接,如源極/汲極及閘極觸點,並減小高度,並在上述開口及BE金屬化層之間引入氣隙以減少寄生電容。本文中所述之實施例可全局地(例如,應用於晶片的所有區域)或選擇性地(例如,應用於晶片的選擇性區域)實行。在一些實施例中,在局部互連接之間所形成之氣隙部分佔據約30%與約70%之間的可用體積,且在電晶體級(例如,在BE中之第一金屬化層之內)之上方所形成的氣隙佔據約40%與約90%之間的可用體積。在一些實施例中,氣隙形成在電晶體級(例如,在局部互連接的ILD中),電晶體級以上(例如,在金屬化層的IMD中)或其組合。在進一步實施例中,源極/汲極觸點比電晶體的晶體結構的高度高,但並不比電晶體(包含矽化物層,若有的話)的晶體結構的高度的約2.5倍高。在一些實施例中,減少閘極觸點的高度以改善觸點電阻,並將閘極觸點的高度配置成介於((包含電晶體結構上的任何介入矽化物層的)電晶體的閘極結構的高
度的約0.25倍與約1.5倍之間。在一些實施例中,如本文中所述之局部互連接在高度上之減少及氣隙存在的組合,在電路中達成RC延遲減少。
在一些實施例中,此結構半導體包含基材,基材具有形成在其上之第一電晶體及第二電晶體,其中第一電晶體及第二電晶體具有相等高度,且每個皆包含源極/汲極區及閘極結構。此結構進一步包含局部互連接層,局部互連接層包括分別連接至第一電晶體及第二電晶體的源極/汲極區及閘極結構的源極/汲極觸點及閘極觸點,其中源極/汲極觸點比第一電晶體及第二電晶體的閘極結構高。此結構亦包含第一互連接層,第一互連接層具有連接至局部互連接層的源極/汲極觸點及閘極觸點之金屬線路,及延伸進入局部互連接層及第一互連接層之氣隙。此結構進一步包括在第一互連接層上之一第二互連接層,氣隙延伸進入第二互連接層。此結構進一步包括在第一互連接層上之一第二互連接層;以及在第二互連接層上之一第三互連接層,其中氣隙延伸進入第二互連接層及第三互連接層。氣隙佔據第一電晶體之上及第一互連接層之下方之該等源極/汲極觸點之間約30%至大約70%的一區域。氣隙佔據第一互連接層的該等金屬線路之間約40%至90%的一區域。氣隙包括一內襯,內襯覆蓋局部互連接層及第一互連接層內之氣隙的內側壁表面。內襯包含一個或更多個介電層,該等介電層包括氮化矽、碳化矽或其組合。每個該閘極觸點在該第一電晶體及該第二電晶體的該等閘極結構的高度
的約0.25倍至約1.5倍之間。每個該等源極/汲極觸點比該第一電晶體及該第二電晶體的該等閘極結構的高度之約2.5倍短。
在一些實施例中,此半導體結構包含基材,基材具有形成在其上之電晶體結構,其中電晶體結構包括源極/汲極區及閘極結構;局部互連接層,具有連接至電晶體結構的源極/汲極區的源極/汲極觸點;設置在局部互連接層上之第一互連接層,第一互連接層具有連接至局部互連接層的源極/汲極觸點之金屬線路;及第一互連接層中之氣隙,其中氣隙定位在電晶體結構之上方並在第一互連接層的相鄰金屬線路之間延伸。此結構進一步包括設置在第一互連接層上之一第二互連接層,其中氣隙的一部分從第一互連接層延伸進入第二互連接層。從第一互連接層延伸進入第二互連接層之氣隙的部分佔據一區域,該區域小於第二互連接層的該等金屬線路之間區域的約40%。從第一互連接層延伸進入第二互連接層之氣隙的部分具有藉由第二互連接層的一介電材料所圍繞的一圓形頂表面。該等源極/汲極觸點具有高度,該等高度在閘極結構的約1.0倍至約2.5倍高度之間。氣隙包括一內襯層,內襯層覆蓋第一互連接層之內之氣隙的內側壁表面。內襯層並不延伸進入第二互連接層。
在一些實施例中,此半導體結構的製造方法包含在基材上形成電晶體結構,其中電晶體結構包含設置在基材中之源極/汲極區、及閘極結構;在基材上沉積第一介電層
以埋置電晶體結構;在第一介電層之內,在電晶體結構的源極/汲極區上形成源極/汲極觸點;在第一介電層上沉積第二介電層;在第二介電層中形成金屬線路以連接至極/汲極觸點;在第二介電層中之金屬線路之間形成開口以暴露第一介電層;通過開口,蝕刻金屬線路之間之第二介電層及源極/汲極觸點之間之第一介電層,以形成延伸開口;及沉積第三介電層以以密封延伸開口並在第一介電層及第二介電層中及在電晶體結構之上形成氣隙。形成該等源極/汲極觸點之步驟包括:在閘極結構的約1.0倍與約2.5倍高度之間的高度,形成該等源極/汲極觸點。在蝕刻步驟之後,沉積一內襯以覆蓋延伸開口的內部表面。開口的頂部在該等金屬線路之間距離的約25%至約30%之間。
應當理解,實施方式段落,及非摘要段落意圖用於解釋請求項。摘要段落可闡明一個或更多個但並非發明人(等)所設想之本揭露內容的所有可能實施例,且因此,無意以任何方式限制任何所附請求項。
前文揭露內容概述數種實施例的特徵,以便熟習此項技藝者可更理解本揭露內容的態樣。熟習此項技藝者應當理解,熟習此項技藝者可輕易地使用本揭露內容作為設計或修改其他程序及結構的基礎,以實現本文介紹的實施例的相同的目的及/或達成相同優點。熟習此項技藝者亦應當認識到,此均等構造不脫離本揭露內容的精神及範圍,且在不脫離本揭露內容的精神及範圍的情況下,熟習此項技藝者可在此文中進行各種改變、替換、及變更。
A:電晶體結構
A':第一晶片區域
A":第二晶片區域
H1~H3:高度
100:通道區
102:基材
102':介電層
105:源極/汲極區
110:閘極結構
110a:閘極電極
110b:介電堆疊
115a,115b:間隔件
120:矽化物層
125:源極/汲極觸點
130:閘極觸點
135:第一金屬化層
135a,155a,160a:金屬線路
140:氣隙
140a:內襯
140b:夾點/圓形頂表面
140bh:高度
145:層間介電質/ILD
150:金屬間介電質/IMD
155:第二金屬化層
155h:高度
155b,160b:通孔
160:第三金屬化層
165:蝕刻停止層
170:蝕刻停止層
Claims (10)
- 一種半導體結構,包括:一基材,具有形成在其上之一第一電晶體及一第二電晶體,其中該第一電晶體及該第二電晶體具有一相等高度,且每個該第一電晶體及該第二電晶體包括源極/汲極區及一閘極結構;一局部互連接層,包括分別連接至該第一電晶體及該第二電晶體的該等源極/汲極區及該閘極結構的源極/汲極觸點及閘極觸點,其中該等源極/汲極觸點比該第一電晶體及該第二電晶體的該等閘極結構高;一第一互連接層,在該局部互連接層上,該第一互連接層包括連接至該局部互連接層的該等源極/汲極觸點及該等閘極觸點之金屬線路;及一氣隙,延伸進入該局部互連接層且低於該等閘極結構之一頂表面,並延伸至該第一互連接層中。
- 如請求項1所述之結構,進一步包括在該第一互連接層上之一第二互連接層,該氣隙延伸進入該第二互連接層。
- 如請求項1所述之結構,進一步包括:在該第一互連接層上之一第二互連接層;及在該第二互連接層上之一第三互連接層,其中該氣隙延伸進入該第二互連接層及該第三互連接層。
- 如請求項1所述之結構,其中該氣隙佔據該第一電晶體之上及該第一互連接層之下方之該等源極/汲極觸點之間約30%至大約70%的一區域。
- 如請求項1所述之結構,其中該氣隙佔據該第一互連接層的該等金屬線路之間約40%至90%的一區域。
- 如請求項1所述之結構,其中該氣隙包括一內襯,該內襯覆蓋該局部互連接層及該第一互連接層內之該氣隙的內側壁表面。
- 如請求項1所述之結構,其中每個該閘極觸點在該第一電晶體及該第二電晶體的該等閘極結構的高度的約0.25倍至約1.5倍之間。
- 如請求項1所述之結構,其中每個該等源極/汲極觸點比該第一電晶體及該第二電晶體的該等閘極結構的高度之約2.5倍短。
- 一種半導體結構,包括: 一基材,具有形成在其上之一電晶體結構,其中該電晶體結構包括源極/汲極區及一閘極結構;一局部互連接層,包括連接至該電晶體結構的該等源極/汲極區的源極/汲極觸點;一第一互連接層,設置在該局部互連接層上,該第一互連接層包括連接至該局部互連接層的該等源極/汲極觸點的金屬線路;及一氣隙,位於該第一互連接層中,其中該氣隙位於在該電晶體結構之上方,在該第一互連接層的相鄰金屬線路之間延伸,且該氣隙包括一內襯,該內襯覆蓋該第一互連接層內之該氣隙的內側壁表面。
- 一種半導體結構的製造方法,包括以下步驟:在一基材上形成一電晶體結構,其中該電晶體結構包括設置在該基材中之源極/汲極區及一閘極結構;在該基材上沉積一第一介電層以埋置該電晶體結構;在該第一介電層之內,在該電晶體結構的該等源極/汲極區上形成源極/汲極觸點;在該第一介電層上沉積一第二介電層;在該第二介電層中形成金屬線路以連接至該等源極/汲極觸點;在該第二介電層中之該等金屬線路之間形成一開口以暴露該第一介電層; 通過該開口,蝕刻該等金屬線路之間的該第二介電層及該等源極/汲極觸點之間的該第一介電層,以形成一延伸開口;及沉積一第三介電層以密封該延伸開口並在該第一介電層及該第二介電層中形成一氣隙,其中該氣隙延伸至該第一介電層且低於該閘極結構之一頂表面。
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DE102020111378B4 (de) | 2022-07-14 |
US20230378071A1 (en) | 2023-11-23 |
KR102421291B1 (ko) | 2022-07-15 |
US11335638B2 (en) | 2022-05-17 |
KR20210128307A (ko) | 2021-10-26 |
DE102020111378A1 (de) | 2021-10-21 |
CN113053884A (zh) | 2021-06-29 |
US20210327813A1 (en) | 2021-10-21 |
US11804439B2 (en) | 2023-10-31 |
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