CN109427655A - 半导体器件的互连结构及其制造方法 - Google Patents

半导体器件的互连结构及其制造方法 Download PDF

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Publication number
CN109427655A
CN109427655A CN201711290392.XA CN201711290392A CN109427655A CN 109427655 A CN109427655 A CN 109427655A CN 201711290392 A CN201711290392 A CN 201711290392A CN 109427655 A CN109427655 A CN 109427655A
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China
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dielectric layer
layer
conducting wire
dielectric
hole
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CN201711290392.XA
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CN109427655B (zh
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游佳达
李凯璿
陈燕铭
徐志安
杨世海
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种器件和形成方法，器件包括：导线，设置在衬底上方；第一介电层，设置在衬底上方并且与导线共面；第二介电层和第三介电层，第二介电层设置在导线上方，第三介电层设置在第一介电层上方；以及通孔，延伸穿过第二介电层并且连接至导线。第二介电层和第三介电层共面，并且第二介电层和第三介电层具有不同的组分。在一些实施例中，在导线上选择性地沉积第二介电层。本发明的实施例还涉及半导体器件的互连结构及其制造方法。

Description

半导体器件的互连结构及其制造方法
技术领域
本发明的实施例涉及半导体器件的互连结构及其制造方法。
背景技术
半导体集成电路(IC)工业已经经历了指数增长。IC材料和设计中的技术进步已经产生了多代IC，其中每一代都具有比前一代更小和更复杂的电路。在IC演化过程中，功能密度(即，每芯片面积的互连器件的数量)普遍增加，而几何尺寸(即，可以使用制造工艺产生的最小的组件(或线))减小。这种按比例缩小工艺通常通过提高生产效率和降低相关成本来提供益处。这种按比例缩小也已经增大了处理和制造IC的复杂度，并且为了实现这些进步，需要IC处理和制造中的类似发展。
例如，多层互连(MLI)用于连接各个器件(晶体管、电阻器、电容器等)以形成IC。在典型的多层互连结构中，导线(例如，铜线)位于堆叠的介电层中并且通过从一层至另一层的通孔连接。该工艺将多个导电部件与上面和下面的层对准。可以通过用光刻(或光刻法)工艺制造的图案限定该对准。有时，光刻工艺之间的覆盖误差可以导致通孔相对于目标导电部件的未对准。未对准的导电部件可以导致与附近的导电部件的意外的桥接(短路)，产生IC缺陷；导致下面的层的过度蚀刻，产生IC可靠性问题；或导致导电部件的期望的互连件之间的未对准，从而产生开口的风险。随着IC持续微型化，这种导电部件(例如，通孔-线)未对准问题越来越成为问题。
发明内容
本发明的实施例提供了一种半导体器件，包括：导线，设置在衬底上方；第一介电层，设置在所述衬底上方并且与所述导线共面；第二介电层和第三介电层，所述第二介电层设置在所述导线上方，所述第三介电层设置在所述第一介电层上方，其中，所述第二介电层和所述第三介电层共面，并且所述第二介电层和所述第三介电层具有不同的组分；以及通孔，延伸穿过所述第二介电层并且连接至所述导线。
本发明的另一实施例提供了一种制造半导体器件的方法，包括：在设置在衬底上方的第一介电层中形成导电部件；在所述导电部件上形成第二介电层，并且在所述第一介电层上方形成第三介电层，其中，所述第二介电层和所述第三介电层具有不同的组分；在图案化的第二介电层中蚀刻通孔开口，暴露所述导电部件；以及用导电材料填充所述通孔开口。
本发明的又一实施例提供了一种制造半导体器件的方法，包括：形成多层互连(MLI)结构的第一层，其中，所述第一层包括第一金属线和第一电介质；在所述第一金属线上方形成第二介电层，并且在所述第一电介质上方形成第三介电层；在所述第二介电层中选择性地蚀刻开口以暴露所述第一金属线；在所述开口中形成导电通孔；以及形成所述多层互连结构的第二层，所述第二层包括第二金属线，并且其中，所述导电通孔互连所述第二金属线和所述第一金属线。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1是根据本发明的各个方面的示出制造具有互连件的IC的方法的实施例的流程图。
图2A、图3A、图4A、图5A、图6A、图7A、图8A、图9A和图10A示出了处于图1的方法的各个处理阶段的器件的实施例的立体图；图2B、图3B、图4B、图5B、图6B、图7B、图8B、图9B、图10B和图10C示出了根据一些实施例的处于图1的方法的各个处理阶段的器件的实施例的相应的截面图。
图11示出了根据一些实施例的半导体器件的实施例的截面图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
本发明通常涉及半导体器件。更具体地，涉及用于集成电路(IC)的多层互连结构。然而，应该理解，期望下面的部件和下面的部件之间对准的其他结构也可以从本发明的方面受益。
图1示出了根据本发明的一个或多个方面的制造半导体器件的方法100的流程图。方法100仅是实例，并且不旨在限制本发明，除非权利要求中明确列举的。可以在方法100之前、期间和之后提供额外的操作，并且对于方法的额外的实施例，可以替换、消除或重排描述的一些操作。
方法100开始于框102，其中，提供衬底。示例性图2A示出了半导体器件200的立体图，并且图2B示出了图2A的沿着“A-A’”线的半导体器件200的截面图。参照图2A和图2B的实例，半导体器件200包括衬底202。
在实施例中，衬底202包括硅衬底(例如，晶圆)。可选地，衬底202可以包括其他元素半导体，诸如锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或它们的组合。在一些实施例中，衬底202是绝缘体上半导体(SOI)。衬底202包括有源器件，诸如p型场效应晶体管(PFET)、n型FET(NFET)、金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极晶体管、高压晶体管和高频晶体管。晶体管可以是平面晶体管或诸如FinFET的多栅极晶体管。衬底202还可以包括诸如电阻器、电容器和电感器的无源器件。在下面的详细描述中讨论的MLI结构204的部分可以用于互连设置在衬底202上的这些器件的任何一个或多个。
然后方法100进行至框104，其中，在衬底上方形成导线。参照图2A和图2B的实例，示出了导线206。导线206是多层互连(MLI)结构204的部分。MLI是互连的一系列导线和/或通孔或接触结构，其中合适的绝缘材料围绕MLI的部分，MLI为设置在下面的衬底上的一个或多个器件提供互连。应该注意，为了简化的目的，MLI结构204示出为具有导线的单层(以及具有下面讨论的导线的第二层)。然而，在各个实施例中，MLI结构204可以包括导电层的任何数量(例如，包括大于两个)的层，诸如五个、七个或复杂IC中的更多的层。每个导电层可以包括任何数量的金属线。此外，互连结构204可以包括位于金属化层下方的导线(包括示出的导线206)的一个或多个层。此外，导线206通过额外的导线或通孔连接至设置在衬底202上的一个或多个元件或器件。
导线206可以包括多个层，诸如阻挡层、粘合层和/或金属层。在一些实施例中，阻挡层或粘合层包括钽(Ta)、氮化钽(TaN)、钛(Ti)、氮化钛(TiN)、钴(Co)和/或其他合适的导电材料。在一些实施例中，铜层设置在阻挡层/粘合层上方。可以用于导线206的其他示例性导电材料包括铝(Al)、钨(W)、钴(Co)、多晶硅和/或其他合适的导体。在实施例中，导线206包括阻挡层(例如，Ta或TaN)和上面的导电材料铜。在实施例中，阻挡层包括一层或多层材料。
在实施例中，导线206形成在绝缘层208中。在一些实施例中，绝缘层208包括低k介电材料。用于绝缘层208的示例性材料包括但不限于正硅酸乙酯(TEOS)氧化物、未掺杂的硅酸盐玻璃或掺杂的硅氧化物(诸如硼磷硅酸盐玻璃(BPSG)、熔融硅酸盐玻璃(FSG)、磷硅酸盐玻璃(PSG)、硼掺杂的硅玻璃(BSG))和/或其他合适的介电材料。
可以通过诸如低压CVD(LPCVD)、等离子体增强CVD(PECVD)、可流动CVD(FCVD)的化学气相沉积(CVD)技术或其他合适的沉积技术在衬底202上方沉积绝缘层208。例如，FCVD工艺包括在衬底202上方沉积可流动材料(诸如液体化合物)，以及通过诸如热退火或紫外辐射的合适的技术将可流动材料转化成固体材料。然后通过CMP工艺平坦化绝缘层208或使绝缘层208凹进以具有平坦的顶面。在一些实施例中，随后，用一个或多个光刻和蚀刻工艺图案化绝缘层208以在其中形成沟槽。光刻工艺可以包括在绝缘层208上面形成光刻胶(抗蚀剂)层，将光刻胶曝光成图案，实施曝光后烘烤工艺以及显影光刻胶以形成包括光刻胶的掩蔽元件。然后掩蔽元件用于在绝缘层208中蚀刻沟槽。蚀刻工艺可以包括干蚀刻、湿蚀刻和/或其他合适的工艺。此后，可以在蚀刻的沟槽中形成导线206。例如，可以在图案化的绝缘层208上沉积用于形成导线206的阻挡/粘合层和/或金属层。在一些实施例中，可以通过诸如溅射、CVD和电镀或化学镀的一种或多种合适的技术沉积导线206的导电材料。在沉积之后，一种或多种导电材料(例如，阻挡层和金属导体层)可以过填充绝缘层208中的沟槽，并且此后，可以实施CMP工艺以平坦化器件200的顶面，以去除绝缘层208上方的过量的阻挡和金属材料。沟槽中的阻挡和金属材料保留，形成导线206。由于CMP工艺，在一些实施例中，绝缘层208的顶面与导线206的顶面变成基本共面。
然后方法100进行至框106，其中，在金属线上沉积材料的第一层。可以选择性地沉积材料的第一层，使得它基本覆盖金属线。在一种实施例中，图案化材料的第一层以形成基本不延伸超出金属线的末端的部件。换句话说，材料的第一层形成在金属线之上垂直对准的部件。金属线206上方的第一层的对准可以在制造工艺的对准公差内(例如，10％内)。参照图3A和图3B的实例，第一层302设置在衬底202上方并且具体地位于导线206上方并且与导线206对准。第一层302和下面的导线206的垂直对准示出为图3B中的虚线302A。
在实施例中，第一层302选择性地生长在导线206上。选择性生长包括在导线206上生长(或沉积)第一层302，而不在诸如介电层208的周围的层上生长(或沉积)第一层302的材料。在一些实施例中，选择性地生长氮化物材料以形成第一层302。
在实施例中，第一层302的选择性生长包括预处理步骤。在实施例中，预处理步骤包括将化学物引入至器件的表面，包括导线206的顶面和介电层208的表面。化学物的引入在介电层208的表面上提供悬空键。用于预处理步骤的示例性化学物包括诸如稀释的氢氟酸的酸的水溶液(HF和DI水)。用于预处理步骤的示例性化学物也包括气体形式的化学物的混合物，诸如例如氨(NH3)和HF3。
在一些实施例中，在预处理之后，第一层302的选择性生长包括处理步骤。处理步骤可以终止在预处理步骤中生成的悬空键。例如，可以实施处理以与介电层208中的悬空键(例如，氧原子)(例如，存在于介电层208(包括上面呈现的示例性组分)的氧化物材料中的氧)生成疏水键。例如，用于预处理步骤的工艺气体可以包括双(三甲基甲硅烷基)胺、六甲基二硅氮烷(HMDS)、四甲基二硅氮烷(TMDS)、三甲基氯硅烷(TMCS)、二甲基二氯硅烷(DMDCS)、甲基三氯硅烷(MTCS)等。
在一些实施例中，示例性工艺气体的一种或多种提供适合于通过甲硅烷基化工艺附接至介电层208的悬空键的组分。附接至介电层208的氧原子可以包括C-H键，其可以包括CH3官能团。例如，根据一些实施例，附接的键/材料可以包括Si(CH3)3。
由于上面讨论的键合，预处理步骤提供形成在介电层208的顶面上的抑制剂膜210。产生的抑制剂膜210可以非常薄，例如，膜210可以仅包括一些终止键。应该注意，膜210在下面讨论的上面的层402的沉积期间和之后保留在介电层208的顶面上。
在上面讨论的预处理步骤和处理步骤之后，可以实施形成第一层302的材料的选择性生长。根据一些实施例，用于第一层302的材料可以包括诸如氮化硅的介电材料。在一些实施例中，通过将工艺气体引入至导线206和抑制剂膜210的表面来实现选择性生长。工艺气体可以包括诸如SiBr4的含硅前体。在一些实施例中，工艺气体可以用于在介于约300℃和约400℃之间的范围内的温度下实施选择性生长。
应该注意，在一些实施例中，第一层302的选择性生长提供优势，包括第一层302相对于下面的导线206的自对准。该自对准缓解了实施图案化工艺(包括如下讨论的)的需求，该图案化工艺需要第一层302和下面的导线206之间的精确对准。应该注意，第一层302可以选择性地形成在包括示例性导线206的金属化层的每个暴露的金属线上方。
在一些其他实施例中，可以使用诸如低压CVD(LPCVD)、等离子体增强CVD(PECVD)、可流动CVD(FCVD)的化学气相沉积(CVD)技术或其他合适的沉积技术在衬底202上方沉积第一层302的材料。在实施例中，第一层302的材料的沉积为整个衬底202上的毯状或共形沉积。随后，在一些实施例中，然后用一个或多个光刻和蚀刻工艺图案化第一层302的材料以形成位于导线206上方并且与导线206对准的部件，示出为图3A和图3B中的第一层302的部件。将材料的第一层图案化成部件的光刻工艺可以包括在第一层302的材料的毯状沉积上面形成光刻胶(抗蚀剂)层，将光刻胶曝光成图案，实施曝光后烘烤工艺以及显影光刻胶以形成包括光刻胶的掩蔽元件。掩蔽元件可以限定第一层302的部件，使得它覆盖导线206并且与导线206对准。在一些实施例中，然后掩蔽元件用于蚀刻材料，从而从绝缘层208上方去除该材料。蚀刻工艺可以包括干蚀刻、湿蚀刻和/或其他合适的工艺。应该注意，可以在金属化层的每条金属线上方形成第一层302。在一些实施例中，第一层包括位于每条金属线上方的部件，其中上面的通孔连接至该金属线。应该注意，在使用诸如以上讨论的光刻图案化的方法中，不形成抑制剂层210。
第一层302的材料是介电材料。在实施例中，第一层302是氮化硅。用于第一层302的其他示例性介电材料包括SiCN和SiCON。可以使用以上讨论的选择性沉积工艺(例如，预处理、处理和选择性生长)形成氮化硅、SiCN和SiCON的任何组分和/或其他合适的组分。应该注意，第一层302的组分选择为给下面讨论的周围的绝缘层402提供蚀刻选择性。在实施例中，第一层302相对于周围的绝缘层402的蚀刻选择性等于或大于约50％。
第一层302具有导线206之上的高度H。在一些实施例中，高度H由形成第一层302所沉积的材料的厚度限定。在一些实例中，高度H在约5纳米(nm)和50纳米之间。由下面讨论的产生的通孔结构的期望长度(垂直延伸)确定高度H。在一些实例中，第一层302的部件的宽度W约等于导线206的宽度。在一些实例中，宽度W介于约5nm和25nm之间。
然后方法100进行至框108，其中，在衬底上形成绝缘层。如以上参照框106讨论的，绝缘层形成为邻近并且邻接第一层。绝缘层可以邻接第一层的部件的侧壁。参照图4A和图4B的实例，在衬底202上形成绝缘层402。层208和402可以包括相同或不同的介电材料。在一些实施例中，绝缘层402和绝缘层208均为氧化物组分。在一些实施例中，绝缘层402和绝缘层208是相同的组分，例如，相同的氧化物组分。在各个实施例中，绝缘层402包括诸如正硅酸乙酯(TEOS)氧化物、未掺杂的硅酸盐玻璃或掺杂的硅氧化物(诸如硼磷硅酸盐玻璃(BPSG)、熔融硅酸盐玻璃(FSG)、磷硅酸盐玻璃(PSG)、硼掺杂的硅玻璃(BSG))的低k介电材料和/或其他合适的介电材料。
可以使用诸如LPCVD、PECVD和FCVD的化学气相沉积(CVD)形成绝缘层402。
然后方法100进行至框110，其中实施诸如化学机械抛光(CMP)工艺的平坦化工艺。如图4A和图4B的实例所示，在一些实施例中，形成绝缘层402，使得它设置在第一层302上方。此后，如框110和图5A与图5B的实例所示，可以回蚀刻绝缘层402以暴露第一层302的顶面，绝缘层402示出为绝缘层402A。在一些实施例中，通过CMP工艺实施回蚀刻。如图5A与图5B的实例所示，绝缘层402A具有与第一层302的顶面共面的顶面。此外，如图所示，绝缘层402A可以邻接第一层302的侧壁。
然后方法100进行至框112，其中，在导线的部分上方的第一层中蚀刻开口。该开口可以暴露下面的导线的顶面。该开口可以由期望的通孔的尺寸限定，如下面讨论的，该通孔随后形成在开口内。参照图6A和图6B的实例，在第一层302中蚀刻开口602。开口602暴露导线206的顶面。开口602也由绝缘层402A和第一层302的侧壁限定。在实施例中，蚀刻是湿蚀刻、干蚀刻、等离子体蚀刻或其他合适的蚀刻技术的一种。在一些实例中，蚀刻是氟基等离子体蚀刻，使用包括CH3F、O2和/或CH4的蚀刻剂气体提供该蚀刻。
如上讨论的，绝缘层402A的组分使得它与第一层302的组分不同。因此，在一些实施例中，在第一层302的组分和周围的绝缘层402A的组分之间提供蚀刻选择性。因此，该蚀刻可以是对第一层302具有选择性的，并且限定为使得产生的开口602与导线206垂直对准，参见由图6B中的虚线602A示出的垂直对准。在一些实施例中，这可以提供开口602和下面的导线206之间的有益的自对准工艺。在一些实例中，第一层302的蚀刻速率比周围的层的蚀刻速率大至少50％。
开口602也可以称为贯通孔。开口602具有宽度W1，宽度W1可以与以上讨论的宽度W基本上相同。在一些实施例中，通过一个或多个光刻和蚀刻工艺(诸如以上讨论的)形成开口602。光刻工艺可以包括在绝缘层402A上面形成光刻胶层，将光刻胶曝光成限定开口602的图案，实施曝光后烘烤工艺，以及显影光刻胶以形成包括光刻胶的掩蔽元件。然后掩蔽元件用于在绝缘层402A内蚀刻开口，直到暴露导线206。蚀刻工艺对如上讨论的第一层302的材料具有选择性。应该注意，在一些实施例中，由于第一层302提供的蚀刻选择性，限定开口602的掩蔽元件的覆盖可以具有更大的对准窗口。例如，由掩蔽元件限定的开口可以向左/右偏移(见图6B)或在光刻胶掩蔽元件中提供比产生的开口602的宽度W1更大的宽度的开口，从而暴露绝缘层402A的部分。这是由于虽然绝缘层402A可以由掩蔽元件暴露，但是由于绝缘层402A和第一层302的组分之间的蚀刻选择性，绝缘层402A的暴露部分不会被蚀刻。因此，某些实施例在限定开口的掩蔽元件和导线206之间的覆盖中提供更大的裕度。
然后方法100进行至框114，其中，用导电材料填充开口以形成通孔。参照图7A和图7B的实例，用导电材料702填充开口602。导电材料702可以包括多个层，包括例如阻挡层、粘合层和上面的导体层。在一些实施例中，导电材料702包括阻挡层，诸如例如钽(Ta)或氮化钽(TaN)。在一些实施例中，导电材料702包括金属导体，诸如铜(Cu)、铝(Al)、钨(W)、钴(Co)或其他合适的金属。可以通过CVD、物理气相沉积(PVD)或ALD技术形成阻挡层；可以通过溅射、CVD或电镀技术形成金属导体。使用如图7A和图7B所示的以上沉积方法，导电材料702的层可以过填充开口602。
然后方法100进行至框116，其中，实施另一平坦化工艺。在一些实施例中，平坦化工艺包括CMP工艺。图8A和图8B的实例示出了在随后的平坦化之后的器件200。具体地，实施平坦化(例如，CMP)工艺以去除在框114中沉积的并且设置在绝缘层402A的顶面上方的过量的导电材料，留下填充先前的开口602的剩余的导电层(例如，阻挡层和金属导体)，并且因此提供通孔702A。通孔702A可以包括一个或多个层(例如，阻挡层和金属导体层)。
然后方法100进行至框118，其中，形成另一导线。可以基本上类似于以上参照框104讨论地形成另一导线。参照图9A、图9B、图10A、图10B和图10C的实例，沉积导电材料902以在通孔702A上方导线902A，导线902A与通孔702A交界。绝缘层904设置在绝缘层402A上方并且邻接导线902A。导线902A可以基本类似于导线206。在实施例中，导线902A和导线206包括相同的组分。在一些实施例中，导线902A是导电层或金属化层，其是比导线206的导电层或金属化层更大的一个层级。例如，导线902A可以设置在金属-2上；导线206设置在金属-1上。绝缘层904可以基本类似于以上参照绝缘层402A和/或绝缘层208所讨论的。在实施例中，绝缘层904、绝缘层402A和绝缘层208的两个或多个包括相同的组分。
导线902(并且因此导线902A)可以包括多个层，诸如阻挡层、粘合层和/或金属层。在一些实施例中，阻挡层或粘合层包括钽(Ta)、氮化钽(TaN)、钛(Ti)、氮化钛(TiN)、钴(Co)和/或其他合适的导电材料。在一些实施例中，铜层设置在阻挡/粘合层上方。可以用于导线902A的其他示例性导电材料包括铝(Al)、钨(W)、钴(Co)、多晶硅和/或其他合适的导体。在实施例中，导线902A包括阻挡层(例如，Ta或TaN)和上面的铜导线。在实施例中，阻挡层包括材料的一层或多层。
在实施例中，在绝缘层904中形成导线902A。在一些实施例中，绝缘层904包括低k介电材料。用于绝缘层904的示例性材料包括但不限于正硅酸乙酯(TEOS)氧化物、未掺杂的硅酸盐玻璃或掺杂的氧化硅(诸如硼磷硅酸盐玻璃(BPSG)、熔融硅玻璃(FSG)、磷硅酸盐玻璃(PSG)、硼掺杂的硅玻璃(BSG))和/或其它合适的介电材料。
可以通过诸如低压CVD(LPCVD)、等离子体增强CVD(PECVD)、可流动CVD(FCVD)的化学气相沉积(CVD)技术或其他合适的沉积技术在衬底202上方沉积绝缘层904。然后通过CMP工艺平坦化绝缘层904或使绝缘层904凹进以具有平坦的顶面。随后，在一些实施例中，然后用一个或多个光刻和蚀刻工艺图案化绝缘层904以在其中形成沟槽。光刻工艺可以包括在绝缘层904上面形成光刻胶(抗蚀剂)层，将光刻胶曝光成图案，实施曝光后烘烤工艺以及显影光刻胶以形成包括光刻胶的掩蔽元件。然后掩蔽元件用于在绝缘层904蚀刻沟槽。蚀刻工艺可以包括干蚀刻、湿蚀刻和/或其他合适的工艺。此后，如图9A和图9B所示，可以在蚀刻的沟槽中形成材料902以形成导线902A。例如，可以在图案化的绝缘层904上沉积用于形成导线902A的阻挡/粘合层和/或金属材料902。在一些实施例中，可以通过诸如溅射、CVD和电镀或化学镀的一种或多种合适的技术沉积导电材料902。在沉积之后，一种或多种导电材料(例如，阻挡层和金属导体层)可以过填充绝缘层904中的沟槽(见图9A、图9B)。此后，可以实施平坦化工艺(CMP工艺)以平坦化器件200的顶面，以去除绝缘层904上方的过量的阻挡和金属材料，见图10A和图10B的实例。沟槽中的阻挡和金属材料保留，形成导线902A。由于平坦化工艺，在一些实施例中，绝缘层904的顶面与导线902A的顶面变成基本共面。
导线206、通孔702A和导线902A提供MLI结构204的示例导电部件。MLI结构204设置在衬底202上方并且连接衬底202中和/或上方的各个有源和/或无源器件以形成包括器件200的IC。在如图所示的实施例中，导线206可以形成第一层金属线(例如，称为金属-1)，并且导线902A提供第二层金属线(例如，称为金属-2)，其中通孔702A互连金属线。然而，这仅是示例性的，并且在其他实施例中，导线206和902A可以形成MLI结构204的任何金属层。虽然未示出，但是导线206/902A和通孔702A通过MLI结构204的其他下面的层或通过有源和/或无源器件的端子(例如，源极、漏极和栅极接触件)连接至衬底202中的有源和/或无源器件。
应该注意，图10C示出截面B-B’处的导线206或从上面的通孔连接移位。第一层302设置在导线206上方并且由绝缘层904、402A和208围绕。在一些实施例中，层904、402A和208的组分是氧化物，并且第一层302的组分是氮化物。由此，第一层302是与层904、402A和208的一个或多个不同的组分。在一些实施例中，第一层302直接与导线206的顶面交界。
然后方法100进行至框120，其中，可以实施额外的制造工艺。在实施例中，实施额外的后段制程(BOEL)工艺，诸如额外的金属化层和插入的介电层的形成，例如，MLI结构的额外的部件。
以上的一个或多个工艺示出了使用镶嵌工艺形成通孔702A和上面的金属化层902A。也可以使用方法100实施包括双镶嵌工艺的其他工艺。
现在参照图11，示出了可以使用包括方法100的一个或多个步骤制造的器件1100。器件1100包括衬底202，衬底202可以基本上类似于如上参照方法100的框102讨论的。在衬底202上制造有源器件1104。在示例性实施例中，有源器件1104是具有栅极结构1106和源极/漏极结构1108的晶体管。在实施例中，有源器件1104是设置在从衬底202延伸的有源区上的FinFET器件。有源器件1104设置在衬底202的有源区上，隔离部件1110设置为邻近衬底202的有源区。隔离部件1110可以是浅沟槽隔离(STI)部件。
栅极结构1106可以包括栅极介电层和栅电极。应该理解，栅极结构1106可以包括额外的层，诸如界面层、覆盖层、扩散/阻挡层、功函层和其他合适的层。在一些实施例中，栅极介电层是高k介电材料。高k介电材料的实例包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆、氧化铝、二氧化铪-氧化铝(HfO2-Al2O3)合金、其他合适的高k介电材料或它们的组合。在一些实施例中，栅极结构包括多晶硅栅电极。在一些实施例中，栅极结构包括金属栅电极。栅电极层可以包括任何合适的材料，诸如多晶硅、铝、钛、钽、钨、钼、氮化钽、硅化镍、硅化钴、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金属合金、其他合适的材料或它们的组合。在一些实施例中，在栅极结构中包括栅极间隔件。栅极间隔件可以是用于偏移随后形成的掺杂区(诸如源极/漏极区)的多层电介质。栅极间隔件还可以用于设计或修改源极/漏极区(结)轮廓。
源极/漏极结构1108可以包括合适的掺杂的半导体材料以提供有源器件1104。在一些实施例中，源极/漏极结构1108是掺杂有n型或p型掺杂剂的外延生长的部件。
接触结构1112可以从栅极结构1106和源极/漏极结构1108的一个或多个延伸。接触结构1112可以是钨或其他合适的导电材料。
多层互连(MLI)结构1114设置在有源器件1104上方并为有源器件1104提供互连。MLI结构1114包括第一金属化层(金属-1)1116、第二金属化层(金属-2)1118、第三金属化层(金属-3)1120和第四金属化层(金属-4)1122。然而，为了示例的目的提供四个金属化层，并且MLI结构1114可以包括任何数量的金属化层。
金属化层1116、1118、1120和/或1122的每个可以包括多层结构，诸如包括衬垫层或阻挡层和上面的金属化层。在一些实施例中，金属化层1116、1118、1120和/或1122包括Ti或Ta或其氮化物的阻挡层和上面的诸如铜的导电材料。在一些实施例中，金属化层1116、1118、1120和/或1122包括诸如钛(Ti)、钽(Ta)、包括Ti和Ta的金属的氮化物、铜(Cu)、铝(Al)、钨(W)、钴(Co)或其他合适的金属的材料。金属化层1116与接触结构1112交界。应该注意，多个层可以插入在金属化层1116和有源器件1104之间，包括层间介电(ILD)层、接触蚀刻停止层(CESL)、提供源极/漏极结构1108或栅极结构1106与上面的接触结构1112之间的接触的硅化物部件和/或本领域已知的其他部件。
通孔结构1124、1126和1128提供相应的金属化层1116、1118、1120和/或1122之间的垂直互连。通孔结构1124、1126和/或1128可以基本类似于以上参照方法100讨论的通孔702A。在一些实施例中，通孔结构1124、1126和1128包括诸如钛(Ti)、钽(Ta)、包括Ti和Ta的金属的氮化物、铜(Cu)、铝(Al)、钨(W)、钴(Co)或其他合适的金属的材料。通孔结构1124、1126和1128也可以是多层部件。
MLI结构1114也包括多个介电或绝缘层，包括称为层间介电(ILD)层的那些。MLI结构1114包括层1130，层1130可以基本类似于以上参照图1的方法100讨论的第一层302。在实施例中，层1130是介电层。在实施例中，层1130具有与MLI结构1114的邻近且共面的ILD层(未示出)不同的组分。层1130可以设置在金属化层1116上，使得它基本垂直对准在金属化层1116上方。例如，层1130的末端边缘可以与金属化层1116的末端边缘基本(垂直)共面。层1130可以延伸金属化层1116的宽度。通孔1124延伸穿过层1130的厚度(或高度)。
MLI结构1114也包括层1132，层1132也可以基本类似于以上参照图1的方法100讨论的第一层302。在实施例中，层1132是介电层。在实施例中，层1132具有与MLI结构1114的邻近且共面的ILD层(未示出)不同的组分。层1132可以设置在金属化层1120上，使得它基本垂直对准在金属化层1120上方。例如，层1132的末端边缘可以与金属化层1120的末端边缘基本(垂直)共面。层1132可以延伸金属化层1120的宽度。通孔1128延伸穿过层1132的厚度(或高度)。
MLI结构1114也包括绝缘层1134A、1134B和1134C。绝缘层1134A、1134B和/或1134C可以基本类似于以上参照图1的方法100描述的绝缘层208、绝缘层402A和/或绝缘层904。绝缘层1134A、1134B和/或1134C可以包括诸如正硅酸乙酯(TEOS)氧化物、未掺杂的硅酸盐玻璃或掺杂的硅氧化物(诸如硼磷硅酸盐玻璃(BPSG)、熔融硅酸盐玻璃(FSG)、磷硅酸盐玻璃(PSG)、硼掺杂的硅玻璃(BSG))的低k介电材料和/或其他合适的介电材料。绝缘层1134A、1134B和/或1134C包括与层1130和/或1132不同的组分。具体地，绝缘层1134A、1134B和1134C的组分相对于层1130和/或1132具有蚀刻选择性。在一些实施例中，绝缘层1134A、1134B和1134C的一个或多个是氧化物，而层1130和/或1132是氮化物。应该注意，绝缘层1134A、1134B和1134C仅是示例性的，并且在器件1100中也存在MLI结构1114的额外的ILD层。具体地，如上所述，存在与层1130和1132的每个共面的相应的ILD层(即，不位于诸如线1116的导线上方的金属化层的那些区域中)。
应该注意，在MLI结构1114中的示例性的点处的截面中示出了器件1100。在器件1100的其他截面点处，基本类似于层1130和/或1132的层与通孔1124和1128横向(例如，水平地)共面。类似的，在器件1100的其他截面点处，基本类似于绝缘层1134A、1134B和/或1134C的层与通孔1118、1126和1122横向(例如，水平地)共面。
虽然不旨在限制，本发明的一个或多个实施例为半导体器件及其形成提供了许多益处。例如，本发明的实施例在多层互连结构中的导线上方提供第一层。诸如当由于覆盖误差而存在限定通孔开口的未对准时，第一层限制了周围和/或下面的介电层的不良蚀刻。因此，某些实施例允许扩大的通孔临界尺寸覆盖窗口。如参照方法100所示，第一层的材料的蚀刻选择性(例如，与周围的介电层/绝缘层相比)可以提供能与BEOL金属化工艺集成的自对准工艺。一个或多个这些益处也可以引起改进的器件性能，诸如由于金属化部件(例如，通孔和下面的金属化层)之间的较大的接触面积而引起较小的接触电阻。
在一个示例性方面，本发明针对一种器件，包括：导线，设置在衬底上方；第一介电层，设置在衬底上方并且与导线共面；第二介电层和第三介电层，第二介电层设置在导线上方，第三介电层设置在第一介电层上方；以及通孔，延伸穿过第二介电层并且连接至导线。第二介电层和第三介电层共面，并且第二介电层和第三介电层具有不同的组分。
在实施例中，通孔的第一侧壁与第二介电层交界，并且通孔的第二侧壁与第三介电层交界。在又一实施例中，通孔的底面与导线交界，并且通孔的顶面与另一导线交界。在实施例中，第二介电层是氮化物，并且第三介电层是氧化物。在实施例中，第一介电层和第三介电层具有相同的组分。在实施例中，第二介电层是氮化硅。
在本文呈现的另一更广泛实施例中，一种方法包括：在设置在衬底上方的第一介电层中形成导电部件，以及在导电部件上形成第二介电层，并且在第一介电层上方形成第三介电层。第二介电层和第三介电层具有不同的组分。在图案化的第二介电层中蚀刻通孔开口，从而暴露导电部件。用导电材料填充通孔开口。
在形成第二介电层的方法的一些实施例中，包括在导电部件上选择性生长材料。在一些实施例中，形成第二介电层包括具有硅和氮的第一组分，并且形成第三介电层包括具有硅和氧的第二组分。在又一实施例中，选择性生长材料包括在第一介电层的顶面上形成抑制剂层。在实施例中，在蚀刻通孔开口之前，平坦化第二介电层和第三介电层。在实施例中，第二介电层的末端边缘垂直地对准在导电部件的末端边缘上方。在一些实施例中，填充通孔开口包括沉积阻挡层以及在阻挡层上方沉积导电材料。在实施例中，形成第二介电层包括在导电部件上选择性生长氮化硅。在实施例中，填充通孔开口包括在沉积导电材料之后实施平坦化工艺。
在本文呈现的另一更广泛实施例中，提供了一种方法，包括形成多层互连(MLI)结构的第一层。第一层包括第一金属线和第一电介质。在第一金属线上方形成第二介电层，并且在第一电介质上方形成第三介电层。在第二介电层中选择性地蚀刻开口以暴露第一金属线。在开口中形成导电通孔。然后形成多层互连结构的第二层(包括第二金属线)。导电通孔互连第二金属线和第一金属线。
在又一实施例中，在第二介电层中选择性地蚀刻开口包括实施蚀刻工艺，蚀刻工艺以比第三介电层大至少50％的选择性蚀刻第二介电层。在实施例中，第二介电层与第一金属线垂直对准。在实施例中，形成第二介电层和第三介电层包括[1]处理第一电介质；[2]在第一金属线上选择性地生长第二介电层；[3]在选择性生长之后，沉积第二材料以在处理的第一电介质上形成第三介电层。处理第一电介质抑制了第一电介质上方的第二介电层的生长。在又一实施例中，平坦化第二材料和第二介电层。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种半导体器件，包括：
导线，设置在衬底上方；
第一介电层，设置在所述衬底上方并且与所述导线共面；
第二介电层和第三介电层，所述第二介电层设置在所述导线上方，所述第三介电层设置在所述第一介电层上方，其中，所述第二介电层和所述第三介电层共面，并且所述第二介电层和所述第三介电层具有不同的组分；以及
通孔，延伸穿过所述第二介电层并且连接至所述导线。
2.根据权利要求1所述的半导体器件，其中，所述通孔的第一侧壁与所述第二介电层交界，并且所述通孔的第二侧壁与所述第三介电层交界。
3.根据权利要求2所述的半导体器件，其中，所述通孔的底面与所述导线交界，并且所述通孔的顶面与另一导线交界。
4.根据权利要求1所述的半导体器件，其中，所述第二介电层是氮化物，并且所述第三介电层是氧化物。
5.根据权利要求1所述的半导体器件，其中，所述第一介电层和所述第三介电层具有相同的组分。
6.根据权利要求1所述的半导体器件，其中，所述第二介电层是氮化硅。
7.一种制造半导体器件的方法，包括：
在设置在衬底上方的第一介电层中形成导电部件；
在所述导电部件上形成第二介电层，并且在所述第一介电层上方形成第三介电层，其中，所述第二介电层和所述第三介电层具有不同的组分；
在图案化的第二介电层中蚀刻通孔开口，暴露所述导电部件；以及
用导电材料填充所述通孔开口。
8.根据权利要求7所述的方法，其中，形成所述第二介电层包括在所述导电部件上选择性生长材料。
9.根据权利要求7所述的方法，其中，形成所述第二介电层包括具有硅和氮的第一组分，并且形成所述第三介电层包括具有硅和氧的第二组分。
10.一种制造半导体器件的方法，包括：
形成多层互连(MLI)结构的第一层，其中，所述第一层包括第一金属线和第一电介质；
在所述第一金属线上方形成第二介电层，并且在所述第一电介质上方形成第三介电层；
在所述第二介电层中选择性地蚀刻开口以暴露所述第一金属线；
在所述开口中形成导电通孔；以及
形成所述多层互连结构的第二层，所述第二层包括第二金属线，并且其中，所述导电通孔互连所述第二金属线和所述第一金属线。
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