JP4836092B2 - 半導体装置の形成方法 - Google Patents
半導体装置の形成方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 64
- 239000004065 semiconductor Substances 0.000 title claims description 44
- 239000010949 copper Substances 0.000 claims description 146
- 238000007747 plating Methods 0.000 claims description 40
- 239000002184 metal Substances 0.000 claims description 33
- 229910052751 metal Inorganic materials 0.000 claims description 33
- 229910044991 metal oxide Inorganic materials 0.000 claims description 24
- 150000004706 metal oxides Chemical class 0.000 claims description 24
- 230000004888 barrier function Effects 0.000 claims description 17
- 230000001590 oxidative effect Effects 0.000 claims description 15
- 238000009792 diffusion process Methods 0.000 claims description 14
- 238000010438 heat treatment Methods 0.000 claims description 14
- 229910052718 tin Inorganic materials 0.000 claims description 14
- 230000015572 biosynthetic process Effects 0.000 claims description 13
- 238000007654 immersion Methods 0.000 claims description 11
- 229910052725 zinc Inorganic materials 0.000 claims description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- 239000001301 oxygen Substances 0.000 claims description 8
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 claims description 7
- 239000002245 particle Substances 0.000 claims description 6
- 239000005751 Copper oxide Substances 0.000 claims description 5
- 229910000431 copper oxide Inorganic materials 0.000 claims description 5
- 238000005498 polishing Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 2
- 230000007935 neutral effect Effects 0.000 claims 1
- 239000010410 layer Substances 0.000 description 231
- 230000003647 oxidation Effects 0.000 description 30
- 238000007254 oxidation reaction Methods 0.000 description 30
- 239000010408 film Substances 0.000 description 23
- 230000008569 process Effects 0.000 description 18
- 229910004298 SiO 2 Inorganic materials 0.000 description 11
- 239000006104 solid solution Substances 0.000 description 10
- 239000000463 material Substances 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 7
- 229910000765 intermetallic Inorganic materials 0.000 description 6
- 239000010409 thin film Substances 0.000 description 6
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 4
- 238000009713 electroplating Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 229910020888 Sn-Cu Inorganic materials 0.000 description 3
- 229910019204 Sn—Cu Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- BZOVBIIWPDQIHF-UHFFFAOYSA-N 3-hydroxy-2-methylbenzenesulfonic acid Chemical compound CC1=C(O)C=CC=C1S(O)(=O)=O BZOVBIIWPDQIHF-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910017482 Cu 6 Sn 5 Inorganic materials 0.000 description 2
- 238000002441 X-ray diffraction Methods 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 239000013590 bulk material Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 238000002149 energy-dispersive X-ray emission spectroscopy Methods 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- RCIVOBGSMSSVTR-UHFFFAOYSA-L stannous sulfate Chemical compound [SnH2+2].[O-]S([O-])(=O)=O RCIVOBGSMSSVTR-UHFFFAOYSA-L 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 239000004094 surface-active agent Substances 0.000 description 2
- 229910000375 tin(II) sulfate Inorganic materials 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910017758 Cu-Si Inorganic materials 0.000 description 1
- 229910017931 Cu—Si Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910006404 SnO 2 Inorganic materials 0.000 description 1
- 238000003917 TEM image Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 239000003963 antioxidant agent Substances 0.000 description 1
- 230000003078 antioxidant effect Effects 0.000 description 1
- QRUDEWIWKLJBPS-UHFFFAOYSA-N benzotriazole Chemical compound C1=CC=C2N[N][N]C2=C1 QRUDEWIWKLJBPS-UHFFFAOYSA-N 0.000 description 1
- 239000012964 benzotriazole Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000003112 inhibitor Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000001247 metal acetylides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229920000412 polyarylene Polymers 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
図1は、第1の実施形態にかかる半導体集積回路の多層配線構造を示す概略断面図である。なお、図1では、第1および第2の層間絶縁膜2、6間に形成した一層のCu配線層4しか示していないが、第2の層間絶縁膜6を下層絶縁膜としてその上に同様の工程によって第2層のCu配線層等を形成することによって多層配線構造とすることが出来ることは勿論である。また、絶縁層にはSiO2を示しているが、メチル基を端持するSiOCH等の無機系絶縁層、あるいはポリアリレン等の有機系絶縁膜等、半導体集積回路の多層配線に用いられるものであれば何でも良い。
図4および図5に、第2の実施形態にかかる半導体集積回路の多層配線構造の形成方法を示す。この実施形態ではダマシンプロセスによってCuの多層配線構造を形成する。まず、図4の段階Iに示す様に、TEOS−SiO2絶縁層10上に、例えばシリコン窒化膜等のハードマスク兼キャップ層11を、配線溝12を形成する部分を残して形成し、エッチングを行って幅が150nmの配線溝12を形成する。なお、SiO2層10の下部には、ロジック回路、メモリ回路等を構成するための種々の拡散領域を作り込んだSiウェハが存在するが、図ではこれらは省略されている。
図8に第3の実施形態にかかる半導体集積回路の多層配線構造の形成方法を示す。本実施形態の多層配線構造は、第1のCu配線層と第2のCu配線層を、キャップ層を介さずに接続させたことを特徴とする。
図9に、第4の実施形態にかかる半導体集積回路の多層配線構造の形成方法を示す。図9の段階Iは、図2の実施形態の段階V(図5参照)に相当し、半導体ウェハ10に形成した第1のCu配線層15上にSnの浸漬メッキによって、メッキ層16を形成した状態を示す。段階IIは、段階Iの試料を酸化性雰囲気中で加熱処理(アニール)した状態を示す。この場合、メッキ層16の構造あるいはアニール処理条件によって、アニール後形成されたSn酸化物層17’の表面に酸化銅(CuO2)粒子40が析出する場合がある。この場合には、HF、H2O2等によって表面に析出したCuO2粒子40を除去し、主にSn酸化物からなるキャップ層17とする(段階III)。Sn酸化物のキャップ層17が形成されると、第2あるいは第3の実施形態の場合と同様にして、多層配線構造を形成する。
2 第1のSiO2層
3 Ta薄膜
4 Cu配線層
5 Sn酸化物層
6 第2のSiO2層
Claims (11)
- 半導体ウェハ上に第1の絶縁層を形成し、
前記第1の絶縁層表面にCuの配線層を形成し、
前記Cuの配線層上に浸漬メッキ法によって金属層を形成し、
前記金属層を酸素雰囲気中で熱処理して金属酸化物層を形成し、
前記金属酸化物層と前記第1の絶縁層上に第2の絶縁層を形成する、各ステップを含む、多層配線構造を有する半導体装置を形成するための方法。 - 請求項1に記載の方法において、前記金属層はSnまたはZnを材料として形成され、前記金属酸化物層はSn酸化物又はZn酸化物である、多層配線構造を有する半導体装置を形成するための方法。
- 請求項1又は2に記載の方法において、前記金属酸化物層は5nm〜50nmの厚さに形成されている、多層配線構造を有する半導体装置を形成するための方法。
- 請求項1乃至3の何れか1項に記載の方法において、前記第1の絶縁層を形成した後であって前記Cuの配線層を形成する以前に、前記第1の絶縁層上にバリア層となるCu拡散防止膜を形成するステップを含む、多層配線構造を有する半導体装置を形成するための方法。
- 請求項1乃至4の何れか1項に記載の方法において、前記金属層を熱処理するステップは、前記金属層を形成した前記半導体ウェハを150℃以上450℃以下の温度範囲において、酸化性雰囲気中で30秒以上60分以下の範囲で熱処理するステップを含む、多層配線構造を有する半導体装置を形成するための方法。
- 半導体ウェハ上に第1の絶縁層を形成し、
前記第1の絶縁層に配線溝を形成し、
前記配線溝中にCu層を埋め込み、
前記Cu層表面を化学機械研磨によって清浄化し、
前記清浄化された前記Cu層表面上に金属層を浸漬メッキによって選択形成し、
前記金属層を酸素雰囲気中で熱処理して金属酸化物層を形成し、
前記金属酸化物層と前記第1の絶縁層上に第2の絶縁層を形成する、各ステップを含む、多層配線構造を有する半導体装置を形成するための方法。 - 請求項6に記載の方法であって、前記金属層はSn又はZnを材料とし、前記金属酸化物層はSn酸化物又はZn酸化物である、多層配線構造を有する半導体装置を形成するための方法。
- 請求項6又は7に記載の方法であって、前記金属酸化物層は5nm〜50nmの厚さに形成されている、多層配線構造を有する半導体装置を形成するための方法。
- 請求項6乃至8の何れか1項に記載の方法であって、前記配線溝を形成するステップと前記Cu層を埋め込むステップ間に、前記配線溝の内面をバリア層となるCu拡散防止膜で被覆するステップを含む、多層配線構造を有する半導体装置を形成するための方法。
- 請求項6乃至8の何れか1項に記載の方法であって、前記金属酸化物を形成するステップは、前記金属層を形成した前記半導体ウェハを150℃以上450℃以下の温度範囲において、酸化性雰囲気中で30秒以上60分以下の範囲で加熱処理するステップを含む、多層配線構造を有する半導体装置を形成するための方法。
- 請求項6乃至8の何れか1項に記載の方法であって、前記金属層を酸化性雰囲気中で熱処理して金属酸化物層を形成するステップにおいて、前記金属酸化物層の表面に酸化銅の粒子が析出した場合、当該酸化銅の粒子を除去するステップを含む、多層配線構造を有する半導体装置を形成するための方法。
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JP2008071835A JP4836092B2 (ja) | 2008-03-19 | 2008-03-19 | 半導体装置の形成方法 |
US12/382,624 US8304908B2 (en) | 2008-03-19 | 2009-03-19 | Semiconductor device having a multilevel interconnect structure and method for fabricating the same |
US13/633,562 US8709939B2 (en) | 2008-03-19 | 2012-10-02 | Semiconductor device having a multilevel interconnect structure and method for fabricating the same |
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JP2011086837A (ja) * | 2009-10-16 | 2011-04-28 | Tohoku Univ | 半導体装置およびその形成方法 |
US10515896B2 (en) * | 2017-08-31 | 2019-12-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnect structure for semiconductor device and methods of fabrication thereof |
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US8709939B2 (en) | 2014-04-29 |
US20090236747A1 (en) | 2009-09-24 |
JP2009231355A (ja) | 2009-10-08 |
US20130089979A1 (en) | 2013-04-11 |
US8304908B2 (en) | 2012-11-06 |
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