CN107154432B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

Info

Publication number
CN107154432B
CN107154432B CN201611221320.5A CN201611221320A CN107154432B CN 107154432 B CN107154432 B CN 107154432B CN 201611221320 A CN201611221320 A CN 201611221320A CN 107154432 B CN107154432 B CN 107154432B
Authority
CN
China
Prior art keywords
gate
fin
forming
structures
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201611221320.5A
Other languages
English (en)
Other versions
CN107154432A (zh
Inventor
冯家馨
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN107154432A publication Critical patent/CN107154432A/zh
Application granted granted Critical
Publication of CN107154432B publication Critical patent/CN107154432B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/515—Insulating materials associated therewith with cavities, e.g. containing a gas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7846—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the lateral device isolation region, e.g. STI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明实施例公开了一种半导体器件，半导体器件包含隔离层、第一和第二鳍结构、栅极结构和源极/漏极结构。隔离绝缘层设置于衬底的上方。第一和第二鳍结构均设置于衬底的上方，并且沿平面图中的第一方向延伸。第一和第二鳍结构的上部暴露于隔离层。栅极结构设置于部分第一和第二鳍结构的上方，并且沿与第一方向交叉的第二方向延伸。源极/漏极结构形成于第一和第二鳍结构的上部上，其没有被第一栅极结构覆盖且暴露于隔离层，且包裹每个露出的第一和第二鳍结构的侧面和顶面。孔洞形成于源极/栅极结构和隔离层之间。本发明实施例涉及半导体器件及其制造方法。

Description

半导体器件及其制造方法
技术领域
本发明实施例涉及半导体集成电路，以及更具体地涉及具有外延源极区/漏极区(S/D)结构的半导体器件以及其制造工艺。
背景技术
随着半导体工业已经步入纳米技术工艺节点以追求更高器件密度、更高性能以及更低成本，来自制造和设计问题的挑战已经引起了三维设计的发展，例如，鳍场效应晶体管(Fin FET)以及具有高K(介电常数)材料的金属栅极结构的使用。经常通过使用栅极替换技术制造金属栅极结构，并且通过使用外延生长方法形成源极和漏极。
发明内容
根据本发明的一些实施例，提供了一种制造包含Fin FET半导体器件的方法，该方法包括：在衬底的上方形成第一鳍结构和第二鳍结构，所述第一鳍结构和所述第二鳍结构沿平面图中的第一方向延伸,在所述衬底的上方形成隔离绝缘层，从而使得所述第一鳍结构和第二鳍结构的下部嵌入在所述隔离绝缘层并且所述第一鳍结构和第二鳍结构的上部暴露于所述隔离绝缘层；在所述第一鳍结构和所述第二鳍结构的部分的上方形成栅极结构，所述栅极结构包括栅极图案、设置在所述栅极图案和所述第一鳍结构和第二鳍结构之间的介电层、设置在所述栅极图案上方的覆盖绝缘层，所述栅极结构在平面图中沿与所述第一方向交叉的第二方向延伸；在所述栅极结构的侧壁上形成栅极侧壁间隔件；凹进所述栅极侧壁间隔件的上部；在没有被所述栅极结构和所述栅极侧壁间隔件覆盖的所述第一鳍结构的上方形成第一源极/漏极结构，并且在没有被所述栅极结构和所述栅极侧壁间隔件覆盖的所述第二鳍结构的上方形成第二源极/漏极结构，其中：在凹进所述栅极侧壁间隔件的上部期间，也凹进没有被所述栅极结构覆盖的所述第一鳍结构和所述第二鳍结构的上部，在形成所述第一源极/漏极结构中，所述第一源极/漏极结构形成于凹进的所述第一鳍结构和第二鳍结构的侧面和顶面上，以及合并所述第一源极/漏极结构和所述第二源极/漏极结构，从而在合并的所述第一源极/漏极结构和第二源极/漏极结构和所述隔离绝缘层之间形成孔洞。
根据本发明的另一些实施例，还提供了一种制造包含Fin FET的半导体器件的方法，所述方法包括：在衬底的上方形成第一鳍结构和第二鳍结构，所述第一鳍结构和第二鳍结构沿平面图中的第一方向延伸；在所述衬底的上方形成隔离绝缘层，从而使得所述第一鳍结构和第二鳍结构的下部嵌入在所述隔离绝缘层中并且所述第一鳍结构和第二鳍结构的上部从所述隔离绝缘层暴露；在所述第一鳍结构和第二鳍结构的部分的上方形成第一栅极结构和第二栅极结构，每个所述第一栅极结构和第二栅极结构包括栅极图案、设置在所述栅极图案和所述第一鳍结构和第二鳍结构之间的介电层、设置在所述栅极图案上方的覆盖绝缘层，所述第一栅极结构和第二栅极结构在平面图中沿与所述第一方向交叉的第二方向延伸；在所述第一栅极结构的侧壁上形成第一栅极侧壁间隔件，并且在所述第二栅极结构的侧壁上形成第二栅极侧壁间隔件；凹进所述第一栅极侧壁间隔件和第二栅极侧壁间隔件的上部；以及在没有被所述第一栅极结构和第二栅极结构及所述第一栅极侧壁间隔件和第二栅极侧壁间隔件覆盖的所述第一鳍结构的上方形成第一源极/漏极结构，并且在没有被所述第一栅极结构和第二栅极结构及所述第一栅极侧壁间隔件和第二栅极侧壁间隔件覆盖的所述第二鳍结构的上方形成第二源极/漏极结构，其中：在凹进所述第一栅极侧壁间隔件和第二栅极侧壁间隔件的上部期间，也凹进没有被所述第一栅极结构和第二栅极结构覆盖的所述第一鳍结构和第二鳍结构的上部，在形成所述第一源极/漏极结构期间，所述第一源极/漏极结构形成在凹进的所述第一鳍结构和第二鳍结构的侧面和顶面上，以及合并所述第一源极/漏极结构和第二源极/漏极结构，从而通过合并的所述第一源极/漏极结构和第二源极/漏极结构、所述隔离绝缘层、所述第一栅极侧壁间隔件中的一个和所述第二栅极侧壁间隔件中的一个形成孔洞，所述第一侧壁间隔件中的一个面向所述第二栅极侧壁间隔件中的一个。
根据本发明的另一些实施例，还提供了一种半导体器件，包括：隔离绝缘层，设置在衬底上方；第一鳍结构和第二鳍结构，均设置在所述衬底的上方，所述第一鳍结构和第二鳍结构沿平面图中的第一方向延伸，所述第一鳍结构和第二鳍结构的上部暴露于所述隔离绝缘层；第一栅极结构，设置在部分的所述第一鳍结构和第二鳍结构的上方，所述第一栅极结构沿平面图中与所述第一方向交叉的第二方向延伸；以及源极/漏极结构，形成在所述第一鳍结构和第二鳍结构的上部上，没有被所述第一栅极结构覆盖并且暴露于所述隔离绝缘层，并且包裹每个暴露的所述第一鳍结构和第二鳍结构的侧面和顶面，其中，在所述源极/栅极结构和所述隔离绝缘层之间形成孔洞。
附图说明
结合附图并阅读以下详细说明，可更好地理解本发明。需强调的是，按照行业的标准做法，各部件不按照比例绘制，并且仅用于说明目的。实际上，为论述清楚，各部件的尺寸可任意放大或缩小。
图1示出Fin FET器件的示例性透视图。
图2是根据本发明的一实施例的Fin FET器件的示例性平面图。
图3A至图7B示出了根据本发明的一实施例的制造FinFET器件的不同阶段的示例性截面图。
图8是根据本发明的另一实施例的Fin FET器件的示例性截面图。
图9A至图11B示出了根据本发明的另一实施例的制造FinFET器件的不同阶段的示例性截面图。
具体实施方式
应了解，以下公开提供用于实施本发明的不同特征的多个不同的实施例或实例。为简化本发明，下面描述组件和设置的具体实施例。当然，这些仅仅是示例，并非旨在限制例如，元件的尺寸并非局限于所公开的范围或值，而是可取决于工艺条件和/或器件的所需性能。此外，在随后的描述中，第一部件形成于第二部件上或者上方可包含其中第一和第二部件形成为直接接触的实施例，也可包含其中额外部件形成于第一和第二部件之间，以便第一和第二部件可以不直接接触的实施例。出于简洁和清晰目的，各种部件可以按不同比例随意绘制。在附图中，为了简化，一些层/部件可被省略。
此外，为了便于描述，本文使用空间相对术语，例如“低于”、“下面”、“下方”、“上面”、“上部”等来描述如图中所示的一个元件或部件与另一元件或部件的关系。空间相对术语旨在包含除附图所示的方向之外使用或操作中的器件的不同方向。该装置可调整为其他方向(旋转90度或者面向其他方向)，而其中所使用的空间相对位置术语可做相应解释。此外，术语“由……制成”可表示“包括”或“由……组成”。进一步地，在以下制造过程中可在该过程之前、之中、与之后可提供一些附加操作，且在附加的该方法的实施例中，下文中所描述的某些操作可被取代或取消。操作/工艺的顺序可相互交换。
图1是具有鳍结构(Fin FET)的半导体FET器件的示例性透视图。
该Fin FET器件包括除其他部件外的衬底10、鳍结构20、隔离绝缘层30和栅极结构40。在一些实施例中，该衬底10是硅衬底。可选地，衬底10可包括诸如锗的另一元素半导体；包含诸如SiC和SiGe的IV-IV族化合物半导体、诸如GaAs、GaP、GaN、InP、InAs、InSb、GaAsP、AlGaN、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP的III-V族化合物半导体或其组合的化合物半导体。在一实施例中，衬底10为SOI(绝缘体上硅)衬底的硅层。诸如非晶Si或者非晶SiC的非晶衬底，或者诸如氧化硅的绝缘材料也可用作衬底10。衬底10可包含已使用杂质(例如，p型或者n型导电性)适当掺杂的各个区域。
一个或多个鳍结构20设置于该衬底10的上方。鳍结构20可由与衬底10相同的材料制成并且可从衬底10中连续延伸。在该实施例中，鳍结构由Si制成。鳍结构20的硅层可是固有的，或者使用n型杂质或者p型杂质适当地掺杂。
在图1中，一个鳍结构20设置于该衬底10的上方。然而，鳍结构的数目不限于一个。该数目可为一个以上。此外，一个或者多个伪鳍结构可设置于邻近鳍结构20的两侧以在图案化工艺中提高图案保真度。在一些实施例中，鳍结构20的宽度范围为约5nm至约40nm，而在其他实施例中为约7nm至约12nm。在一些实施例中，鳍结构20的高度范围为约100nm至约300nm，而在其他实施例中为约50nm至约100nm。
鳍结构20的位于栅极结构40下方的下部可称为阱区，且该鳍结构20的上部可称为沟道区。在该栅极结构40的下方，该阱区嵌入该隔离绝缘层30中，且该沟道区从该隔离绝缘层30突出。沟道区域的下部也可嵌入隔离绝缘层30至约1nm到约5nm的深度。
在一些实施例中，阱区的高度范围为约60nm至100nm，以及沟道区域的高度范围为约40nm至60nm，并且在其他实施例中范围为约38nm至约55nm。
进一步地，通过包含绝缘材料的隔离绝缘层30(或称之为“浅沟槽隔离(STI)”层)填充鳍结构之间的间隔和/或一个鳍结构与形成于该衬底10的上方的另一元件之间的间隔。隔离绝缘层30的隔离材料可包含一层或多层氧化硅、氮化硅、氧氮化硅(SiON)、SiOCN、掺氟硅酸盐玻璃(FSG)或者低k介电材料。隔离绝缘层通过LPCVD(低压化学汽相沉积)、等离子体CVD或者可流动CVD形成。在可流动CVD中，可流动介电材料代替氧化硅可被沉积。可流动介电材料，如其名称所指示的，在沉积期间可“流动”以填充具有高高宽比的缝隙或间隔。通常，各种化学成分被添加至含硅前体以允许沉积膜流动。在一些实施例中，氮氢键被添加。可流动介电前体，特别是可流动氧化硅前体的示例包含硅酸盐、硅氧烷、甲基倍半硅氧烷(MSQ)、氢倍半硅氧烷(HSQ)、MSQ/HSQ、全氢硅氮烷(TCPS)、全氢-聚硅氮烷(PSZ)、正硅酸乙酯(TEOS)或甲硅烷基胺，例如三甲硅烷基胺(TSA)。这些可流动氧化硅材料形成于多操作工艺中。沉积可流动膜之后，对其进行固化并且退火以去除不期望的元素来形成氧化硅。当不期望的元素被去除后，可流动膜致密化并且收缩。在一些实施例中，多种退火工艺被实施。可流动膜不止一次被固化并且被退火。可流动膜可使用硼和/或磷掺杂。
图2是根据本发明的一实施例的形成该栅极结构之后的Fin FET器件的示例性平面图。图3A-3D展示沿着图2中的(图3A)的线X1-X1、线Y1-Y1(图3B)、线X2-X2(图3C)和线Y2-Y2(图3D)的示例性截面图。
如图2和图3A-3D所示，第一鳍结构20A和第二鳍结构20B形成于该衬底10的上方。
根据一实施例，为了制造鳍结构，在衬底的上方形成掩模层。例如，通过热氧化工艺和/或化学汽相沉积(CVD)工艺形成掩模层。例如，衬底10为杂质浓度范围为约1×1015cm-3至约1×1016cm-3的p型硅或锗衬底。在其他实施例中，衬底为杂质浓度范围为约1×1015cm-3至约1×1016cm-3的n型硅或锗衬底。在一些实施例中，例如，掩模层包含衬垫氧化物(例如，氧化硅)层以及氮化硅掩模层。
衬垫氧化物层可通过使用热氧化或者CVD工艺形成。氮化硅掩模层可通过诸如溅射法的物理汽相沉积(PVD)、CVD、等离子体增强化学汽相沉积(PECVD)、常压化学汽相沉积(APCVD)、低压CVD(LPCVD)、高密度等离子体CVD(HDPCVD)、原子层沉积(ALD)和/或其他工艺形成。
在一些实施例中，衬垫氧化物层的厚度范围为约2nm至约15nm，以及氮化硅掩模层的厚度范围为约2nm至约50nm。在掩模层的上方还形成了掩模图案。掩模图案是，例如，通过光刻操作形成的光刻胶图案。
通过将掩模图案用作蚀刻掩模，形成衬垫氧化物层和氮化硅掩模层的硬掩模图案。在一些实施例中，该硬掩模图案的宽度范围为约5nm至约40nm。在一些实施例中，该硬掩模图案的宽度范围为约7nm至约12nm。
通过将硬掩模图案用作蚀刻掩模，通过使用干蚀刻法和/或湿蚀刻法的沟槽蚀刻将该衬底10图案化成鳍结构。在一些实施例中，鳍结构的宽度范围为约4nm至约15nm，并且在一些实施例中，两个鳍结构之间的间隔为约10nm至约50nm。
形成鳍结构20A和20B后，在鳍结构之间的间隔和/或一鳍结构和另一形成于衬底10的上方的元件之间的间隔中形成隔离绝缘层30。隔离绝缘层30也可被称为“浅沟槽隔离(STI)”层。隔离绝缘层30的绝缘材料可包含一层或多层氧化硅、氮化硅、氧氮化硅(SiON)、SiOCN、掺氟硅酸盐玻璃(FSG)或者低k介电材料。隔离绝缘层通过LPCVD(低压化学汽相沉积)、等离子体CVD或者可流动CVD形成。在可流动CVD中，可流动介电材料代替氧化硅可被沉积。可流动介电材料，如其名称所指示的，在沉积过程中可“流动”以填充具有高高宽比的缝隙或间隔。通常，各种化学物质被添加至含硅前体以允许沉积膜流动。在一些实施例中，氮氢键被添加。可流动介电前体，特别是可流动氧化硅前体的示例包含硅酸盐、硅氧烷、甲基倍半硅氧烷(MSQ)、氢倍半硅氧烷(HSQ)、MSQ/HSQ、全氢硅氮烷(TCPS)、全氢-聚硅氮烷(PSZ)、正硅酸乙酯(TEOS)或甲硅烷基胺，例如三甲硅烷基胺(TSA)。这些可流动氧化硅材料形成于多操作工艺中。沉积可流动膜之后，对其进行固化并且退火以去除不期望的元素来形成氧化硅。当不期望的元素被去除后，可流动膜致密化并且收缩。在一些实施例中，实施多次退火工艺。可流动膜不止一次固化并且被退火。可流动膜可使用硼和/或磷掺杂。
首先以厚层形成绝缘层30以便该鳍结构嵌入该厚层中，然后凹进该厚层以便暴露鳍结构20A和20B的上部。在凹进隔离绝缘层30之后或者之前，执行热工艺，例如，执行退火工艺以提高隔离绝缘层30的质量。在具体的实施例中，在惰性气体环境下，诸如N2、Ar或者He气体环境下，在范围为约900℃至约1050℃的温度下使用约1.5秒至约10秒的快速热退火(RTA)来实施热工艺。
在形成该绝缘层30之后，在该鳍结构20A和20B的上方形成第一栅极结构40A和第二栅极结构40B。
为了制造栅极结构，介电层和多晶硅层形成于隔离绝缘层30和暴露的鳍结构的上方，然后执行图案化操作以便获得包含由多晶硅制成的栅极图案43和介电层45的栅极结构。在一些实施例中，多晶硅层通过使用硬掩模被图案化以及该硬掩模作为覆盖绝缘层47保留在栅极图案43上。硬掩模(覆盖绝缘层47)包含一个或多个绝缘材料层。在一些实施例中，覆盖绝缘层47包含形成于氧化硅层上方的氮化硅层。在其他实施例中，覆盖绝缘层47包含形成于氮化硅层上方的氧化硅层。覆盖绝缘层47的绝缘材料可通过CVD、PVD、ALD、电子束蒸发或者其他合适的工艺形成。在一些实施例中，介电层45可包含一个或多个氧化硅、氮化硅、氮氧化硅或其他高k电介质层。介电层45的厚度范围在一些实施例中为约2nm至约20nm，而在其他实施例中为约2nm至约10nm。在一些实施例中，栅极结构的厚度范围为约50nm至约400nm，而在其他实施例中为约100nm至约200nm。
在本实施例中，使用了栅极替换技术。因此，栅极图案43和介电层45分别为伪栅电极和伪栅极介电层，其随后会被去除。
进一步地，栅极侧壁间隔件54形成于栅极结构40A、40B的两个侧壁上，且鳍侧壁间隔件52也形成于该鳍结构20A、20B的两个侧壁上。侧壁间隔件54、52包含一个或多个绝缘材料层，例如，SiO2、SiN、SiON、SiOCN或者SiCN，其通过CVD、PVD、ALD、电子束蒸发或者其他合适的工艺形成。低k介电材料可被用作侧壁间隔件。侧壁间隔件54、52通过形成绝缘材料的毯式层以及执行各向异性蚀刻形成。如图3B，暴露该鳍结构20A、20B的上表面。在一个实施例中，侧壁间隔件层是由基于氮化硅的材料制成，例如SiN、SiON、SiOCN或者SiCN。在一实施例中，具有该侧壁间隔件的该鳍结构20A和20B之间的间隔S1的范围为约5nm至约30nm。
接下来，如图4A和4B所示，该栅极侧壁间隔件54和该鳍侧壁间隔件52的上部被部分地去除(凹进)。图4A是对应于图2中的线X1-X1的示例性截面图，且图4B是对应于图2中的线Y1-Y1的示例性截面图。
通过使用各向异性干法蚀刻操作，该栅极侧壁间隔件54和该鳍侧壁间隔件52的上部被部分地去除(凹进)。该凹进量H1在约10nm至约50nm的范围内。
在蚀刻期间，该鳍结构20A、20B的上部也被轻微地蚀刻。因此，该鳍结构20A、20B的高度下降H2的量。
接下来，如图5A-5C所示，源极/漏极结构60形成于该鳍结构20A、20B的露出的上部的上方。图5A是对应于图2中的线X1-X1的示例性截面图，且图5B是对应于图2中的线Y1-Y1的示例性截面图，且图5C是对应于图2中的线X2-X2的示例性截面图。
该源极/漏极结构60是由具有不同于鳍结构(沟道区域)的晶格常数的一个或者多个半导体材料层制成的。当该鳍结构由硅制成时，该源极/漏极结构60包含用于n沟道FinFET的SiP、SiC或SiCP及用于p沟道Fin FET的SiGe或Ge。该源极/漏极结构60外延地形成于该鳍结构20A、20B的上部的上方。由于形成为鳍结构20A、20B的衬底的晶体取向(例如，(100)平面)，该源极/漏极结构60横向生长且具有类似菱形的形状。在一个实施例中，该量H2设置为小于该源极/漏极结构60的横向生长量。从该鳍结构的中心测量的该横向生长量的范围为约S1至约1.4×S1(见图3B)。
可在约600至800℃的温度下、约80至150托的压力下，通过使用含Si的气体，例如SiH4、Si2H6、SiCl2H2和诸如PH3的掺杂气体，生长该源极/漏极结构60。通过单独外延工艺可形成用于n型沟道FET的源极/漏极结构和用于p型沟道FET的源极/漏极结构。
如图5B所示，因为该鳍结构20A、20B的上部从该隔离绝缘层30和该鳍侧壁间隔件52突出，该源极/漏极结构形成于该第一和第二鳍结构20A和20B的上部的侧面和顶面上。如图5A所示，该源极/漏极结构60生长于该鳍结构20A、20B的最上部的上方。
进一步地，由于该鳍结构之间相对较小的间隔，形成于该第一鳍结构20A上方的源极/漏极结构和形成于该第二鳍结构20B上方的源极/漏极结构被合并，从而通过该合并的源极/漏极结构60、该隔离绝缘层30、该第一栅极结构40A的该栅极侧壁间隔件54中的一个和该第二栅极结构40B的该栅极侧壁间隔件中的一个形成孔洞或间隙(空气间隙)65。
在一些实施例中，孔洞65自隔离绝缘层30的表面的高度H3的范围为约10nm至约40nm。
接下来，如图6A和6B所示，硅化物层70形成于该源极/漏极结构60的上方。图6A是沿着图2中的线X1-X1的示例性截面图,且图6B是沿着图2中的线Y1-Y1的示例性截面图。
在形成该源极/漏极结构60之后，例如Ni、Ti、Ta和/或W的金属材料形成于该源极/漏极结构60的上方并且执行退火操作以形成硅化物层70。在其他实施例中，例如NiSi、TiSi、TaSi和/或WSi的硅化物材料形成于该源极/漏极结构60的上方，并且执行退火操作。退火操作在约250℃至约850℃的温度中被执行。金属材料或者硅化物材料通过CVD或者ALD形成。在一些实施例中，硅化物层70的厚度范围为约4nm至约10nm。在进行退火操作之前或之后，通过使用湿式蚀刻工艺选择性地去除形成于该隔离绝缘层30、该覆盖隔离材料47和侧壁间隔件52、54上方的该金属材料或该硅化物材料。
接下来，如图7A和7B所示，形成金属栅极结构，随后形成接触插塞。图7A是沿着图2中的线X1-X1的示例性截面图,且图7B是沿着图2中的线Y1-Y1的示例性截面图。
形成硅化物层70之后，伪栅极结构(伪栅电极43和伪栅极介电层45)被去除并且被金属栅极结构(金属栅电极90和栅极介电层95)替代。
在具体实施例中，第一层间介电层形成于伪栅极结构的上方，并且执行平坦化操作，例如化学机械抛光(CMP)工艺或者回蚀刻工艺，以暴露伪栅电极43的上表面。然后，伪栅电极43和伪栅极介电层45通过合适的蚀刻工艺分别被去除以形成栅极开口。包含栅极介电层95和金属栅电极90的金属栅极结构形成于栅极开口中。
栅极介电层95可形成于界面层(未示出)的上方，界面层设置于鳍结构20A、20B的沟道层的上方。在一些实施例中，界面层可包含氧化硅或者氧化锗，其具有0.2nm至1.5nm的厚度。在其他实施例中，界面层的厚度范围为约0.5nm至约1.0nm。
栅极介电层95包含一个或多个介电材料层，例如氧化硅、氮化硅、或者高k介电材料、其他合适的介电材料，和/或其组合。高k介电材料的示例包含HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆、氧化铝、氧化钛、氧化铪-氧化铝(HfO2-Al2O3)合金、其他合适的高k介电材料，和/或其组合。栅极介电层通过，例如，化学汽相沉积(CVD)、物理汽相沉积(PVD)、原子层沉积(ALD)、高密度等离子体CVD(HDPCVD)、或者其他合适的方法，和/或其组合形成。栅极介电层的厚度范围在一些实施例中为约1nm至约10nm，而在其他实施例中为约2nm至约7nm。
金属栅电极90形成于栅极介电层95的上方。金属栅电极90包含一个或多个任意合适的金属材料层，例如铝、铜、钛、钽、钴、钼、氮化钽、硅化镍、硅化钴、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金属合金、其他合适的材料，和/或其组合。
在本发明的一些实施例中，一个或多个功函调整层(没有显示)可被插入于栅极介电层95和金属栅电极90之间。功函调整层由导电材料制成，诸如，TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC的单层，或两种以上的这些材料的多层。针对n沟道Fin FET，将TaN、TaAlC、TiN、TiC、Co、TiAl、HfTi、TiSi和TaSi中的一种或多种用作功函调整层，而针对p沟道Fin FET，将TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC和Co中的一种或多种用作功函调整层。
沉积用于金属栅极结构的合适材料之后，实施诸如CMP的平坦化操作。
之后，第二层间介电层85形成于该成型的金属栅极结构的上方。在一些实施例中，用作接触蚀刻停止层的绝缘层80形成于该成型的金属栅极结构的上方，然后形成第二层间介电层85。
绝缘层80是一个或多个绝缘材料层。在一实施例中，绝缘层80由通过CVD形成的氮化硅制成。
通过使用包含光刻的图案化操作，接触孔形成于第二层间介电层85和绝缘层80中，以便暴露具有硅化物层70的源极和漏极结构60。然后，接触孔被导电材料填充，从而形成接触插塞100。接触插塞100可包含诸如Co、W、Ti、Ta、Cu、Al和/或Ni和/或它们的氮化物的任何合适的金属的单层或者多层。
形成接触插塞之后，执行进一步的CMOS工艺以形成不同的部件，例如附加层间介电层、接触件/通孔、互连金属层和钝化层等。
图8是根据本发明的另一实施例的Fin FET器件的示例性截面图。在图8的实施例中，三个鳍结构设置于该衬底的上方且两个孔洞65形成于两个邻近的鳍结构之间的间隔内。
图9A-11B示出了根据本发明的另一实施例的制造Fin FET器件的不同阶段的示例性截面图。在本实施例中，形成该硅化物层的时间与上述实施例不同。在本实施例中使用与上述实施例相同或相似的配置、材料或操作，其具体的说明可省略。
在形成如图5A-5C所示的该源极/漏极结构60之后，形成如图9A和9B所示的金属栅极结构90、95、绝缘层80(接触蚀刻停止层)和层间介电层85，而不形成硅化物层。图9A是沿着图2中的线X1-X1的示例性截面图，且图9B是沿着图2中的线Y1-Y1的示例性截面图。
接下来，如图10A和10B所示，接触孔105形成于绝缘层80和层间介电层85中以暴露源极/漏极结构60的上表面，然后硅化物层75形成于源极/漏极结构60的上表面上。图10A是沿着图2中的线X1-X1的示例性截面图,且图10B是沿着图2中的线Y1-Y1的示例性截面图。
形成硅化物层75之后，如图11A和11B所示，导电材料形成于接触孔105中，从而形成接触插塞100。图11A是沿着图2中的线X1-X1的示例性截面图，且图11B是沿着图2中的线Y1-Y1的示例性截面图。
形成接触插塞之后，进一步的CMOS工艺被执行以形成不同的部件，例如附加层间介电层、接触件/通孔、互连金属层和钝化层等。
在本发明中，因为孔洞形成于该源极/漏极外延层和该隔离绝缘层(STI)之间，能够降低该源极/漏极结构的寄生电容。
将要理解的是，本文不一定论述了所有的优势，所有实施例或示例不要求特定优势，并且其他实施例或示例可提供不同的优势。
根据本发明的一方面，在一种用于制造包含Fin FET的半导体器件的方法中，第一鳍结构和第二鳍结构形成于衬底的上方。第一和第二鳍结构在平面图中沿第一方向延伸。隔离绝缘层形成于衬底的上方，以便第一和第二鳍结构的下部嵌入隔离绝缘层以及第一和第二鳍结构的上部暴露于隔离绝缘层之外。栅极结构形成于部分第一和第二鳍结构的部分的上方。该栅极结构包括栅极图案、设置于该栅极图案和第一和第二鳍结构之间的介电层以及设置于栅极图案上方的覆盖绝缘层。该栅极结构沿平面图中与第一方向交叉的第二方向延伸。另外，栅极侧壁间隔件形成于栅极图案的两个侧壁上。凹进该栅极侧壁间隔件的上部。第一源极/漏极结构形成于没有被该栅极结构和该栅极侧壁间隔件覆盖的该第一鳍结构的上方且第二源极/漏极结构形成于没有被该栅极结构和该栅极侧壁间隔件覆盖的该第二鳍结构的上方。在凹进该栅极侧壁间隔件的上部期间，也凹进没有被该栅极结构覆盖的该第一和第二鳍结构的上部。在形成该第一源极/漏极结构期间，该源极/漏极结构形成于该凹进的第一和第二鳍结构的侧面和顶面上。合并该第一和第二源极/漏极结构，从而孔洞形成于该合并的第一和第二源极/漏极结构和该隔离绝缘层之间。
根据本发明的另一方面，在一种用于制造包含Fin FET半导体器件的方法中，第一鳍结构和第二鳍结构形成于衬底的上方。第一和第二鳍结构在平面图中沿第一方向延伸。隔离绝缘层形成于衬底的上方，以便第一和第二鳍结构的下部嵌入隔离绝缘层以及第一和第二鳍结构的上部暴露于隔离绝缘层之外。第一栅极结构形和第二栅极结构成于部分第一和第二鳍结构的上方。该第一和第二栅极结构中的每一个包括栅极图案、设置于栅极图案以及第一和第二鳍结构之间的介电层以及设置于栅极图案上方的覆盖绝缘层。该第一和第二栅极结构沿平面图中与第一方向交叉的第二方向延伸。第一栅极侧壁间隔件形成于该第一栅极结构的侧壁上且第二栅极侧壁间隔件形成于该第二栅极结构的侧壁上。凹进该第一和第二栅极侧壁间隔件的上部。第一源极/漏极结构形成于没有被该第一和第二栅极结构及该栅极侧壁间隔件覆盖的该第一鳍结构的上方且第二源极/漏极结构形成于没有被该第一和第二栅极结构及该第一和第二栅极侧壁间隔件覆盖的该第二鳍结构的上方。在凹进该第一和第二栅极侧壁间隔件的上部期间，也凹进没有被该第一和第二栅极结构覆盖的该第一和第二鳍结构的上部。在形成该第一源极/漏极结构期间，该第一源极/漏极结构形成于该凹进的第一和第二鳍结构的侧面和顶表面上。合并该第一和第二源极/漏极结构，从而孔洞经由该合并的第一和第二源极/漏极结构、该隔离绝缘层、该第一栅极侧壁间隔件中的一个和该第二栅极侧壁间隔件中的一个形成，该第一侧壁间隔件中的一个面向该第二栅极侧壁间隔件中的一个。
根据本发明的另一方面，半导体器件包含隔离绝缘层、第一鳍结构和第二鳍结构、第一栅极结构以及源极/漏极结构。隔离绝缘层设置于衬底的上方。第一鳍结构和第二鳍结构均设置于该衬底的上方。第一和第二鳍结构在平面图中沿第一方向延伸。所述第一和第二鳍结构的上部从所述隔离绝缘层暴露。所述第一栅极结构设置于部分第一和第二鳍结构的上方，并且中沿交叉于第一方向的第二方向延伸。源极/漏极结构形成于第一和第二鳍结构的上部上，其没有被第一栅极结构覆盖且从隔离绝缘层暴露，且包裹各个暴露的第一和第二鳍结构的侧面和顶面。孔洞形成于源极/栅极结构和隔离绝缘层之间。
根据本发明的一些实施例，提供了一种制造包含Fin FET半导体器件的方法，该方法包括：在衬底的上方形成第一鳍结构和第二鳍结构，所述第一鳍结构和所述第二鳍结构沿平面图中的第一方向延伸,在所述衬底的上方形成隔离绝缘层，从而使得所述第一鳍结构和第二鳍结构的下部嵌入在所述隔离绝缘层并且所述第一鳍结构和第二鳍结构的上部暴露于所述隔离绝缘层；在所述第一鳍结构和所述第二鳍结构的部分的上方形成栅极结构，所述栅极结构包括栅极图案、设置在所述栅极图案和所述第一鳍结构和第二鳍结构之间的介电层、设置在所述栅极图案上方的覆盖绝缘层，所述栅极结构在平面图中沿与所述第一方向交叉的第二方向延伸；在所述栅极结构的侧壁上形成栅极侧壁间隔件；凹进所述栅极侧壁间隔件的上部；在没有被所述栅极结构和所述栅极侧壁间隔件覆盖的所述第一鳍结构的上方形成第一源极/漏极结构，并且在没有被所述栅极结构和所述栅极侧壁间隔件覆盖的所述第二鳍结构的上方形成第二源极/漏极结构，其中：在凹进所述栅极侧壁间隔件的上部期间，也凹进没有被所述栅极结构覆盖的所述第一鳍结构和所述第二鳍结构的上部，在形成所述第一源极/漏极结构中，所述第一源极/漏极结构形成于凹进的所述第一鳍结构和第二鳍结构的侧面和顶面上，以及合并所述第一源极/漏极结构和所述第二源极/漏极结构，从而在合并的所述第一源极/漏极结构和第二源极/漏极结构和所述隔离绝缘层之间形成孔洞。
在上述方法中，在形成所述栅极侧壁间隔件期间，在所述第一鳍结构和所述第二鳍结构的侧壁上形成鳍侧壁间隔件。
在上述方法中，在凹进所述栅极侧壁间隔件的上部期间，也凹进所述鳍侧壁间隔件的上部。
在上述方法中，还包括，在形成所述第一源极/漏极结构和所述第二源极/漏极结构之后：在合并的所述第一源极/漏极结构和所述第二源极/漏极结构上形成硅化物层；形成层间绝缘层；在所述层间绝缘层中形成开口；以及在所述开口中的所述硅化物层的上方形成导电材料。
在上述方法中，在形成所述层间绝缘层之前形成所述硅化物层。
在上述方法中，在形成所述开口之后形成所述硅化物层。
在上述方法中，还包括，在形成所述层间绝缘层之前，形成所述绝缘层。
在上述方法中，还包括，在形成所述第一源极/漏极结构和所述第二源极/漏极结构之后：去除所述覆盖绝缘层、所述栅极图案和所述介电层，从而形成栅极空间；在所述栅极空间中形成栅极介电层；以及在所述栅极空间中的所述栅极介电层上形成栅电极。
根据本发明的另一些实施例，还提供了一种制造包含Fin FET的半导体器件的方法，所述方法包括：在衬底的上方形成第一鳍结构和第二鳍结构，所述第一鳍结构和第二鳍结构沿平面图中的第一方向延伸；在所述衬底的上方形成隔离绝缘层，从而使得所述第一鳍结构和第二鳍结构的下部嵌入在所述隔离绝缘层中并且所述第一鳍结构和第二鳍结构的上部从所述隔离绝缘层暴露；在所述第一鳍结构和第二鳍结构的部分的上方形成第一栅极结构和第二栅极结构，每个所述第一栅极结构和第二栅极结构包括栅极图案、设置在所述栅极图案和所述第一鳍结构和第二鳍结构之间的介电层、设置在所述栅极图案上方的覆盖绝缘层，所述第一栅极结构和第二栅极结构在平面图中沿与所述第一方向交叉的第二方向延伸；在所述第一栅极结构的侧壁上形成第一栅极侧壁间隔件，并且在所述第二栅极结构的侧壁上形成第二栅极侧壁间隔件；凹进所述第一栅极侧壁间隔件和第二栅极侧壁间隔件的上部；以及在没有被所述第一栅极结构和第二栅极结构及所述第一栅极侧壁间隔件和第二栅极侧壁间隔件覆盖的所述第一鳍结构的上方形成第一源极/漏极结构，并且在没有被所述第一栅极结构和第二栅极结构及所述第一栅极侧壁间隔件和第二栅极侧壁间隔件覆盖的所述第二鳍结构的上方形成第二源极/漏极结构，其中：在凹进所述第一栅极侧壁间隔件和第二栅极侧壁间隔件的上部期间，也凹进没有被所述第一栅极结构和第二栅极结构覆盖的所述第一鳍结构和第二鳍结构的上部，在形成所述第一源极/漏极结构期间，所述第一源极/漏极结构形成在凹进的所述第一鳍结构和第二鳍结构的侧面和顶面上，以及合并所述第一源极/漏极结构和第二源极/漏极结构，从而通过合并的所述第一源极/漏极结构和第二源极/漏极结构、所述隔离绝缘层、所述第一栅极侧壁间隔件中的一个和所述第二栅极侧壁间隔件中的一个形成孔洞，所述第一侧壁间隔件中的一个面向所述第二栅极侧壁间隔件中的一个。
在上述方法中，在形成所述第一栅极侧壁间隔件和第二栅极侧壁间隔件期间，在所述第一鳍结构和第二鳍结构的侧壁上形成鳍侧壁间隔件。
在上述方法中，在凹进所述第一栅极侧壁间隔件和第二栅极侧壁间隔件的上部期间，也凹进所述鳍侧壁间隔件的上部。
在上述方法中，还包括，在形成所述第一源极/漏极结构和第二源极/漏极结构之后：在合并的所述第一源极/漏极结构和第二源极/漏极结构上形成硅化物层；在形成所述硅化物层之后，形成层间绝缘层；在所述层间绝缘层中形成开口；以及在所述开口中的硅化物层的上方形成导电材料。
在上述方法中，还包括，在形成所述第一源极/漏极结构和第二源极/漏极结构之后：形成层间绝缘层；在所述层间绝缘层中形成开口；在暴露于所述开口中的所述合并的第一源极/漏极结构和第二源极/漏极结构上形成硅化物层；以及在所述开口中的所述硅化物层的上方形成导电材料。
在上述方法中，还包括，在形成所述第一源极/漏极结构和第二源极/漏极结构之后：从每个所述第一栅极结构和第二栅极结构去除所述覆盖绝缘层、所述栅极图案和所述介电层，从而形成第一栅极空间和第二栅极空间；在每个所述第一栅极空间和第二栅极空间中形成栅极介电层；以及在每个所述第一栅极空间和第二栅极空间中的所述栅极介电层上形成栅电极。
根据本发明的另一些实施例，还提供了一种半导体器件，包括：隔离绝缘层，设置在衬底上方；第一鳍结构和第二鳍结构，均设置在所述衬底的上方，所述第一鳍结构和第二鳍结构沿平面图中的第一方向延伸，所述第一鳍结构和第二鳍结构的上部暴露于所述隔离绝缘层；第一栅极结构，设置在部分的所述第一鳍结构和第二鳍结构的上方，所述第一栅极结构沿平面图中与所述第一方向交叉的第二方向延伸；以及源极/漏极结构，形成在所述第一鳍结构和第二鳍结构的上部上，没有被所述第一栅极结构覆盖并且暴露于所述隔离绝缘层，并且包裹每个暴露的所述第一鳍结构和第二鳍结构的侧面和顶面，其中，在所述源极/栅极结构和所述隔离绝缘层之间形成孔洞。
在上述半导体器件中，还包括：层间介电层，设置在所述第一栅极结构和所述源极/漏极结构的上方；硅化物层，形成在所述源极/漏极结构上；以及接触插塞，形成在所述层间介电层中并且连接到所述硅化物层。
在上述半导体器件中，所述硅化物层不形成在所述源极/漏极层的上表面的部分上，所述源极/漏极层的上表面的部分不接触所述接触插塞。
在上述半导体器件中，还包括设置在所述源极/漏极结构和所述层间介电层之间的绝缘层。
在上述半导体器件中，还包括设置在所述第一鳍结构和第二鳍结构的部分的上方的第二栅极结构，其中：所述栅极结构沿与所述第一方向交叉的所述第二方向延伸，且与平面图中第一方向上的所述第一栅极结构平行地布置，以及所述孔洞形成在通过平面图中的所述第一鳍结构和第二鳍结构和所述第一栅极结构和第二栅极结构限定的区域中。
在上述半导体器件中，还包括设置在所述第一鳍结构和第二鳍结构的部分的上方的第二栅极结构，其中：所述第二栅极结构沿与所述第一方向交叉的所述第二方向延伸，且与平面图中第一方向上的所述第一栅极结构平行地布置，以及所述孔洞形成在通过平面图中的所述第一鳍结构和第二鳍结构和所述第一栅极结构和第二栅极结构限定的区域内。
前述内容概述了多个实施例的特征，从而使得本领域的技术人员能较好地理解本发明的方面。本领域的技术人员应理解，其可以轻松地将本发明作为基础，用于设计或修改其他工艺或结构，从而达成与本文所介绍实施例的相同目的和/或实现相同的优点。本领域技术人员还应当意识到，这种等效结构不脱离本发明的精神和范围，并且在不脱离本发明的精神和范围的情况下，他们可以作出多种修改、替换和改变。

Claims (20)

1.一种制造包含Fin FET半导体器件的方法，所述方法包括：
在衬底的上方形成第一鳍结构和第二鳍结构，所述第一鳍结构和所述第二鳍结构沿平面图中的第一方向延伸,
在所述衬底的上方形成隔离绝缘层，从而使得所述第一鳍结构和第二鳍结构的下部嵌入在所述隔离绝缘层并且所述第一鳍结构和第二鳍结构的上部暴露于所述隔离绝缘层；
在所述第一鳍结构和所述第二鳍结构的部分的上方形成栅极结构，所述栅极结构包括栅极图案、设置在所述栅极图案和所述第一鳍结构和第二鳍结构之间的介电层、设置在所述栅极图案上方的覆盖绝缘层，所述栅极结构在平面图中沿与所述第一方向交叉的第二方向延伸；
在所述栅极结构的侧壁上形成栅极侧壁间隔件；
凹进所述栅极侧壁间隔件的上部；
在没有被所述栅极结构和所述栅极侧壁间隔件覆盖的所述第一鳍结构的上方形成第一源极/漏极结构，并且在没有被所述栅极结构和所述栅极侧壁间隔件覆盖的所述第二鳍结构的上方形成第二源极/漏极结构，其中：
在凹进所述栅极侧壁间隔件的上部期间，也凹进没有被所述栅极结构覆盖的所述第一鳍结构和所述第二鳍结构的上部，
在形成所述第一源极/漏极结构中，所述第一源极/漏极结构形成于凹进的所述第一鳍结构和第二鳍结构的侧面和顶面上，以及
合并所述第一源极/漏极结构和所述第二源极/漏极结构，从而在合并的所述第一源极/漏极结构和第二源极/漏极结构和所述隔离绝缘层之间形成孔洞。
2.根据权利要求1所述的方法，其中，在形成所述栅极侧壁间隔件期间，在所述第一鳍结构和所述第二鳍结构的侧壁上形成鳍侧壁间隔件。
3.根据权利要求2所述的方法，其中，在凹进所述栅极侧壁间隔件的上部期间，也凹进所述鳍侧壁间隔件的上部。
4.根据权利要求1所述的方法，还包括，在形成所述第一源极/漏极结构和所述第二源极/漏极结构之后：
在合并的所述第一源极/漏极结构和所述第二源极/漏极结构上形成硅化物层；
形成层间绝缘层；
在所述层间绝缘层中形成开口；以及
在所述开口中的所述硅化物层的上方形成导电材料。
5.根据权利要求4所述的方法，其中，在形成所述层间绝缘层之前形成所述硅化物层。
6.根据权利要求4所述的方法，其中，在形成所述开口之后形成所述硅化物层。
7.根据权利要求4所述的方法，还包括，在形成所述层间绝缘层之前，形成所述绝缘层。
8.根据权利要求1所述的方法，还包括，在形成所述第一源极/漏极结构和所述第二源极/漏极结构之后：
去除所述覆盖绝缘层、所述栅极图案和所述介电层，从而形成栅极空间；
在所述栅极空间中形成栅极介电层；以及
在所述栅极空间中的所述栅极介电层上形成栅电极。
9.一种制造包含Fin FET的半导体器件的方法，所述方法包括：
在衬底的上方形成第一鳍结构和第二鳍结构，所述第一鳍结构和第二鳍结构沿平面图中的第一方向延伸；
在所述衬底的上方形成隔离绝缘层，从而使得所述第一鳍结构和第二鳍结构的下部嵌入在所述隔离绝缘层中并且所述第一鳍结构和第二鳍结构的上部从所述隔离绝缘层暴露；
在所述第一鳍结构和第二鳍结构的部分的上方形成第一栅极结构和第二栅极结构，每个所述第一栅极结构和第二栅极结构包括栅极图案、设置在所述栅极图案和所述第一鳍结构和第二鳍结构之间的介电层、设置在所述栅极图案上方的覆盖绝缘层，所述第一栅极结构和第二栅极结构在平面图中沿与所述第一方向交叉的第二方向延伸；
在所述第一栅极结构的侧壁上形成第一栅极侧壁间隔件，并且在所述第二栅极结构的侧壁上形成第二栅极侧壁间隔件；
凹进所述第一栅极侧壁间隔件和第二栅极侧壁间隔件的上部；以及
在没有被所述第一栅极结构和第二栅极结构及所述第一栅极侧壁间隔件和第二栅极侧壁间隔件覆盖的所述第一鳍结构的上方形成第一源极/漏极结构，并且在没有被所述第一栅极结构和第二栅极结构及所述第一栅极侧壁间隔件和第二栅极侧壁间隔件覆盖的所述第二鳍结构的上方形成第二源极/漏极结构，其中：
在凹进所述第一栅极侧壁间隔件和第二栅极侧壁间隔件的上部期间，也凹进没有被所述第一栅极结构和第二栅极结构覆盖的所述第一鳍结构和第二鳍结构的上部，
在形成所述第一源极/漏极结构期间，所述第一源极/漏极结构形成在凹进的所述第一鳍结构和第二鳍结构的侧面和顶面上，以及
合并所述第一源极/漏极结构和第二源极/漏极结构，从而通过合并的所述第一源极/漏极结构和第二源极/漏极结构、所述隔离绝缘层、所述第一栅极侧壁间隔件中的一个和所述第二栅极侧壁间隔件中的一个形成孔洞，所述第一栅极侧壁间隔件中的一个面向所述第二栅极侧壁间隔件中的一个。
10.根据权利要求9所述的方法，其中，在形成所述第一栅极侧壁间隔件和第二栅极侧壁间隔件期间，在所述第一鳍结构和第二鳍结构的侧壁上形成鳍侧壁间隔件。
11.根据权利要求10所述的方法，其中，在凹进所述第一栅极侧壁间隔件和第二栅极侧壁间隔件的上部期间，也凹进所述鳍侧壁间隔件的上部。
12.根据权利要求9所述的方法，还包括，在形成所述第一源极/漏极结构和第二源极/漏极结构之后：
在合并的所述第一源极/漏极结构和第二源极/漏极结构上形成硅化物层；
在形成所述硅化物层之后，形成层间绝缘层；
在所述层间绝缘层中形成开口；以及
在所述开口中的硅化物层的上方形成导电材料。
13.根据权利要求9所述的方法，还包括，在形成所述第一源极/漏极结构和第二源极/漏极结构之后：
形成层间绝缘层；
在所述层间绝缘层中形成开口；
在暴露于所述开口中的所述合并的第一源极/漏极结构和第二源极/漏极结构上形成硅化物层；以及
在所述开口中的所述硅化物层的上方形成导电材料。
14.根据权利要求9所述的方法，还包括，在形成所述第一源极/漏极结构和第二源极/漏极结构之后：
从每个所述第一栅极结构和第二栅极结构去除所述覆盖绝缘层、所述栅极图案和所述介电层，从而形成第一栅极空间和第二栅极空间；
在每个所述第一栅极空间和第二栅极空间中形成栅极介电层；以及
在每个所述第一栅极空间和第二栅极空间中的所述栅极介电层上形成栅电极。
15.一种半导体器件，包括：
隔离绝缘层，设置在衬底上方；
第一鳍结构和第二鳍结构，均设置在所述衬底的上方，所述第一鳍结构和第二鳍结构沿平面图中的第一方向延伸，所述第一鳍结构和第二鳍结构的上部暴露于所述隔离绝缘层；
第一栅极结构，设置在部分的所述第一鳍结构和第二鳍结构的上方，所述第一栅极结构沿平面图中与所述第一方向交叉的第二方向延伸；以及
多个第一鳍侧壁间隔件，覆盖暴露的所述第一鳍结构的下部，以及
多个第二鳍侧壁间隔件，覆盖暴露的所述第二鳍结构的下部；以及
源极/漏极结构，形成在所述第一鳍结构和第二鳍结构的上部上，没有被所述第一栅极结构覆盖并且暴露于所述隔离绝缘层，并且包裹每个暴露的所述第一鳍结构和第二鳍结构的侧面和顶面，
其中，在所述源极/漏极结构和所述隔离绝缘层之间形成孔洞，
所述多个第一鳍侧壁间隔件中的一个和所述多个第二鳍侧壁间隔件中的一个暴露在所述孔洞，以及
所述多个第一鳍侧壁间隔件中的所述一个的整个侧表面和所述多个第二鳍侧壁间隔件中的所述一个的整个侧表面暴露在所述孔洞中。
16.根据权利要求15所述的半导体器件，还包括：
层间介电层，设置在所述第一栅极结构和所述源极/漏极结构的上方；
硅化物层，形成在所述源极/漏极结构上；以及
接触插塞，形成在所述层间介电层中并且连接到所述硅化物层。
17.根据权利要求16所述的半导体器件，其中，所述硅化物层不形成在所述源极/漏极层的上表面的部分上，所述源极/漏极层的上表面的部分不接触所述接触插塞。
18.根据权利要求16所述的半导体器件，还包括设置在所述源极/漏极结构和所述层间介电层之间的绝缘层。
19.根据权利要求15所述的半导体器件，还包括设置在所述第一鳍结构和第二鳍结构的部分的上方的第二栅极结构，其中：
所述第二栅极结构沿与所述第一方向交叉的所述第二方向延伸，且与平面图中第一方向上的所述第一栅极结构平行地布置，以及
所述孔洞形成在通过平面图中的所述第一鳍结构和第二鳍结构和所述第一栅极结构和第二栅极结构限定的区域中。
20.根据权利要求16所述的半导体器件，还包括设置在所述第一鳍结构和第二鳍结构的部分的上方的第二栅极结构，其中：
所述第二栅极结构沿与所述第一方向交叉的所述第二方向延伸，且与平面图中第一方向上的所述第一栅极结构平行地布置，以及
所述孔洞形成在通过平面图中的所述第一鳍结构和第二鳍结构和所述第一栅极结构和第二栅极结构限定的区域内。
CN201611221320.5A 2016-03-03 2016-12-26 半导体器件及其制造方法 Active CN107154432B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/060,286 2016-03-03
US15/060,286 US9755019B1 (en) 2016-03-03 2016-03-03 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
CN107154432A CN107154432A (zh) 2017-09-12
CN107154432B true CN107154432B (zh) 2020-01-14

Family

ID=59701515

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201611221320.5A Active CN107154432B (zh) 2016-03-03 2016-12-26 半导体器件及其制造方法

Country Status (4)

Country Link
US (2) US9755019B1 (zh)
KR (1) KR101879051B1 (zh)
CN (1) CN107154432B (zh)
TW (1) TWI638459B (zh)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9570556B1 (en) * 2016-03-03 2017-02-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US9865504B2 (en) * 2016-03-04 2018-01-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and manufacturing method thereof
TWI745365B (zh) * 2017-03-23 2021-11-11 聯華電子股份有限公司 半導體元件及其製作方法
US10147787B1 (en) 2017-05-31 2018-12-04 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and manufacturing method thereof
US10181425B1 (en) * 2017-07-17 2019-01-15 Taiwan Semiconductor Manufacturing Company, Ltd. Gate-end structure engineering for semiconductor applications
KR102519551B1 (ko) * 2017-08-03 2023-04-10 삼성전자주식회사 반도체 소자
KR102432467B1 (ko) * 2017-08-30 2022-08-12 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US10483378B2 (en) * 2017-08-31 2019-11-19 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial features confined by dielectric fins and spacers
KR102337408B1 (ko) * 2017-09-13 2021-12-10 삼성전자주식회사 수직 채널을 가지는 반도체 소자 및 그 제조 방법
WO2019066768A1 (en) * 2017-09-26 2019-04-04 Intel Corporation DIRECTIONAL SPACER REMOVAL FOR INTEGRATED CIRCUIT STRUCTURES
US10276693B1 (en) * 2017-10-31 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10749007B2 (en) * 2018-03-14 2020-08-18 Taiwan Semiconductor Manufacturing Co., Ltd. Gate structure with desired profile for semiconductor devices
KR102574320B1 (ko) 2018-06-20 2023-09-04 삼성전자주식회사 핀펫을 구비하는 반도체 소자
US10707333B2 (en) * 2018-07-30 2020-07-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US11227918B2 (en) 2018-07-31 2022-01-18 Taiwan Semiconductor Manufacturing Company, Ltd. Melt anneal source and drain regions
US10680075B2 (en) * 2018-09-28 2020-06-09 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including source/drain epitaxial layer having facets and manufacturing method thereof
US10943829B2 (en) * 2018-10-23 2021-03-09 Taiwan Semiconductor Manufacturing Company, Ltd. Slot contacts and method forming same
TWI730291B (zh) * 2019-02-13 2021-06-11 新唐科技股份有限公司 靜電放電(esd)保護元件
US11004725B2 (en) * 2019-06-14 2021-05-11 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a FinFET device with gaps in the source/drain region
US11222980B2 (en) * 2019-07-18 2022-01-11 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a semiconductor device and a semiconductor device
CN113809044A (zh) * 2020-06-12 2021-12-17 联华电子股份有限公司 半导体元件

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102077353A (zh) * 2008-06-30 2011-05-25 先进微装置公司 形成在体衬底上的双栅极与三栅极晶体管及形成该晶体管的方法
CN102117828A (zh) * 2009-12-30 2011-07-06 中国科学院微电子研究所 半导体器件及其制造方法

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7667271B2 (en) 2007-04-27 2010-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field-effect transistors
US7910453B2 (en) 2008-07-14 2011-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Storage nitride encapsulation for non-planar sonos NAND flash charge retention
US20110147840A1 (en) 2009-12-23 2011-06-23 Cea Stephen M Wrap-around contacts for finfet and tri-gate devices
US8310013B2 (en) 2010-02-11 2012-11-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a FinFET device
US8399931B2 (en) 2010-06-30 2013-03-19 Taiwan Semiconductor Manufacturing Company, Ltd. Layout for multiple-fin SRAM cell
US8729627B2 (en) 2010-05-14 2014-05-20 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel integrated circuit devices
US8816444B2 (en) 2011-04-29 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. System and methods for converting planar design to FinFET design
US8466027B2 (en) 2011-09-08 2013-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Silicide formation and associated devices
US8723272B2 (en) 2011-10-04 2014-05-13 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and method of manufacturing same
KR20180070718A (ko) 2011-12-30 2018-06-26 인텔 코포레이션 집적 회로 구조물 및 집적 회로 구조물의 제조 방법
US8377779B1 (en) 2012-01-03 2013-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of manufacturing semiconductor devices and transistors
US8735993B2 (en) 2012-01-31 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET body contact and method of making same
US8785285B2 (en) 2012-03-08 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US8716765B2 (en) 2012-03-23 2014-05-06 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8860148B2 (en) 2012-04-11 2014-10-14 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for FinFET integrated with capacitor
CN103579295B (zh) 2012-07-25 2016-12-28 中国科学院微电子研究所 半导体器件及其制造方法
US8736056B2 (en) 2012-07-31 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Device for reducing contact resistance of a metal
US8703556B2 (en) * 2012-08-30 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making a FinFET device
US9105490B2 (en) 2012-09-27 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8823065B2 (en) 2012-11-08 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8772109B2 (en) 2012-10-24 2014-07-08 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for forming semiconductor contacts
US9236300B2 (en) 2012-11-30 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Contact plugs in SRAM cells and the method of forming the same
US8921191B2 (en) 2013-02-05 2014-12-30 GlobalFoundries, Inc. Integrated circuits including FINFET devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same
KR102038486B1 (ko) * 2013-04-09 2019-10-30 삼성전자 주식회사 반도체 장치 및 그 제조 방법
KR102068980B1 (ko) 2013-08-01 2020-01-22 삼성전자 주식회사 반도체 장치 및 그 제조 방법
US9214556B2 (en) * 2013-08-09 2015-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned dual-metal silicide and germanide formation
US20150076607A1 (en) * 2013-09-18 2015-03-19 International Business Machines Corporation Fin field effect transistor with merged metal semiconductor alloy regions
US9196522B2 (en) * 2013-10-16 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with buried insulator layer and method for forming
KR102146469B1 (ko) * 2014-04-30 2020-08-21 삼성전자 주식회사 반도체 장치 및 이의 제조 방법
KR102202753B1 (ko) 2014-08-11 2021-01-14 삼성전자주식회사 반도체 장치 및 그 제조 방법
KR102235578B1 (ko) * 2014-11-19 2021-04-02 삼성전자주식회사 반도체 장치 및 그 제조 방법

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102077353A (zh) * 2008-06-30 2011-05-25 先进微装置公司 形成在体衬底上的双栅极与三栅极晶体管及形成该晶体管的方法
CN102117828A (zh) * 2009-12-30 2011-07-06 中国科学院微电子研究所 半导体器件及其制造方法

Also Published As

Publication number Publication date
US10141307B2 (en) 2018-11-27
US20170256613A1 (en) 2017-09-07
TW201733119A (zh) 2017-09-16
KR20170103613A (ko) 2017-09-13
US20170287910A1 (en) 2017-10-05
CN107154432A (zh) 2017-09-12
TWI638459B (zh) 2018-10-11
KR101879051B1 (ko) 2018-07-16
US9755019B1 (en) 2017-09-05

Similar Documents

Publication Publication Date Title
CN107154432B (zh) 半导体器件及其制造方法
US10879374B2 (en) Semiconductor device and manufacturing method thereof
US11101143B2 (en) Semiconductor device and manufacturing method thereof
CN107154384B (zh) 半导体器件及其制造方法
KR102183123B1 (ko) 반도체 디바이스 및 이의 제조 방법
CN108269850B (zh) 半导体器件及其制造方法
US10158007B2 (en) Semiconductor device and manufacturing method thereof
US20190229120A1 (en) Semiconductor device and manufacturing method thereof
CN106252231B (zh) 包括鳍结构的半导体器件及其制造方法
US11121217B2 (en) Semiconductor device and manufacturing method thereof
CN107665825B (zh) 半导体器件以及PMOS FET的源极/漏极结构和PMOS FinFET的制造方法
US11804489B2 (en) Semiconductor device and manufacturing method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant