TW201733119A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TW201733119A
TW201733119A TW105126054A TW105126054A TW201733119A TW 201733119 A TW201733119 A TW 201733119A TW 105126054 A TW105126054 A TW 105126054A TW 105126054 A TW105126054 A TW 105126054A TW 201733119 A TW201733119 A TW 201733119A
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gate
fin
source
forming
fin structure
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TW105126054A
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TWI638459B (zh
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家馨 馮
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台灣積體電路製造股份有限公司
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Abstract

半導體裝置包含隔離層、第一鰭結構及第二鰭結構、閘極結構和源極/汲極結構，隔離層設置於基底之上，第一鰭結構及第二鰭結構設置於基底之上且於上視圖中沿第一方向延伸，第一鰭結構及第二鰭結構之上部分從隔離層露出，閘極結構設置於部分的第一鰭結構及第二鰭結構之上，且沿與第一方向交叉的第二方向延伸，源極/汲極結構形成於未被第一閘極結構覆蓋且從隔離層露出的第一鰭結構及第二鰭結構之上部分上，且包裹每一個露出的第一鰭結構及第二鰭結構之側表面及頂表面，孔洞形成於源極/汲極結構與隔離層之間。

Description

半導體裝置及其製造方法
本揭露係有關於半導體積體電路，且特別是有關於具有磊晶(epitaxial)源極/汲極結構的半導體裝置及其製造方法。
隨著半導體工業演進至奈米技術製程節點以追求更高之裝置密度、更高之效能與更低之成本，來自於製造與設計問題的挑戰進而發展出了三維(three-dimensional)設計，如鰭型場效電晶體(fin field effect transistor,Fin FET)及使用具有高介電常數(high-k)材料的金屬閘極結構。金屬閘極結構通常藉由使用閘極取代(gate replacement)技術製造，而源極/汲極係藉由使用磊晶成長的方式形成。
根據本揭露之一方面，包含鰭型場效電晶體之半導體裝置的製造方法中，形成第一鰭結構及第二鰭結構於基底之上，第一鰭結構及第二鰭結構於上視圖中沿第一方向延伸。形成隔離絕緣層於基底之上使得第一鰭結構及第二鰭結構之下部分嵌入隔離絕緣層，且第一鰭結構及第二鰭結構之上部分從隔離絕緣層露出。形成閘極結構於部分的第一鰭結構及第二鰭結構之上，閘極結構包含閘極圖案、設置於閘極圖案與第一 鰭結構和第二鰭結構之間的介電層以及設置於閘極圖案之上的蓋絕緣層，閘極結構於上視圖中沿與第一方向交叉的第二方向延伸。形成閘極側壁間隔元件於閘極結構之側壁上，使閘極側壁間隔元件之上部分凹入。在未被閘極結構及閘極側壁間隔元件覆蓋的第一鰭結構之上形成第一源極/汲極區結構，及在未被閘極結構及閘極側壁間隔元件覆蓋的第二鰭結構之上形成第二源極/汲極區結構。在使閘極側壁元件之上部分凹入的步驟中，也使未被閘極結構覆蓋的第一鰭結構及第二鰭結構之上部分凹入。在形成第一源極/汲極區結構的步驟中，第一源極/汲極區結構形成於凹入的第一鰭結構及第二鰭結構之側表面及頂表面之上。合併第一源極/汲極區結構及第二源極/汲極區結構，使得孔洞形成於合併的第一源極/汲極區結構及第二源極/汲極區結構與隔離絕緣層之間。
根據本揭露之另一方面，包含鰭型場效電晶體之半導體裝置的製造方法中，形成第一鰭結構及第二鰭結構於基底之上，第一鰭結構及第二鰭結構於上視圖中沿第一方向延伸。形成隔離絕緣層於基底之上，使得第一鰭結構及第二鰭結構之下部分嵌入隔離絕緣層，且第一鰭結構及第二鰭結構之上部分從隔離絕緣層露出。形成第一閘極結構及第二閘極結構於部分的第一鰭結構及第二鰭結構之上，每個第一閘極結構及第二閘極結構包含閘極圖案、設置於閘極圖案與第一鰭結構和第二鰭結構之間的介電層及設置於閘極圖案之上的蓋絕緣層，第一閘極結構及第二閘極結構於上視圖中沿與第一方向交叉的第二方向延伸。形成第一閘極側壁間隔元件於第一閘極結構之 側壁上，及形成第二閘極側壁間隔元件於第二閘極結構之側壁上。使第一閘極側壁間隔元件及第二閘極側壁間隔元件之上部分凹入。在未被第一閘極結構及第二閘極結構和第一閘極側壁間隔元件及第二閘極側壁間隔元件覆蓋的第一鰭結構之上形成第一源極/汲極區結構，及在未被第一閘極結構及第二閘極結構和第一閘極側壁間隔元件及第二閘極側壁間隔元件覆蓋的第二鰭結構之上形成第二源極/汲極區結構。在使第一閘極側壁間隔元件及第二閘極側壁間隔元件之上部分凹入的步驟中，也使未被第一閘極結構及第二閘極結構覆蓋的第一鰭結構及第二鰭結構之上部分凹入。在形成第一源極/汲極區結構的步驟中，第一源極/汲極區結構形成於凹入的第一鰭結構及第二鰭結構之側表面及頂表面之上。合併第一源極/汲極區結構及第二源極/汲極區結構，使得孔洞由合併的第一源極/汲極區結構及第二源極/汲極區結構、隔離絕緣層、第一閘極側壁間隔元件中的一個及第二閘極側壁間隔元件中的一個形成，前述之第一閘極側壁間隔元件中的一個面對前述之第二閘極側壁間隔元件中的一個。
根據本揭露之另一方面，半導體裝置包含隔離絕緣層、第一鰭結構及第二鰭結構、第一閘極結構及源極/汲極結構。隔離絕緣層設置於基底之上。第一鰭結構及第二鰭結構兩者皆設置於基底之上，第一鰭結構及第二鰭結構於上視圖中沿第一方向延伸，第一鰭結構及第二鰭結構之上部分從隔離絕緣層露出。第一閘極結構設置於部分的第一鰭結構及第二鰭結構之上，且第一閘極結構沿與第一方向交叉的第二方向延伸。 源極/汲極結構形成於未被第一閘極結構覆蓋且從隔離絕緣層露出的第一鰭結構及第二鰭結構之上部分上，且包裹每一個露出的第一鰭結構及第二鰭結構之側表面及頂表面，孔洞形成於源極/汲極結構與隔離絕緣層之間。
10‧‧‧基底
20‧‧‧鰭結構
20A‧‧‧第一鰭結構
20B‧‧‧第二鰭結構
30‧‧‧隔離絕緣層
40‧‧‧閘極結構
40A‧‧‧第一閘極結構
40B‧‧‧第二閘極結構
43‧‧‧閘極圖案
45‧‧‧介電層
47‧‧‧蓋絕緣層
52‧‧‧鰭側壁間隔元件
54‧‧‧閘極側壁間隔元件
60‧‧‧源極/汲極結構
65‧‧‧孔洞
70、75‧‧‧矽化物層
80‧‧‧絕緣層
85‧‧‧第二層間介電層
90‧‧‧金屬閘極電極
95‧‧‧閘極介電層
100‧‧‧接觸插塞
105‧‧‧接觸孔
S1‧‧‧空間
H1、H2‧‧‧量
H3‧‧‧高度
根據以下的詳細說明並配合所附圖式做完整揭露。應注意的是，根據本產業的一般作業，圖示中的各種特徵部件並未必按照比例繪製。事實上，可能任意的放大或縮小各種特徵部件的尺寸，以做清楚的說明。
第1圖係鰭型場效電晶體(Fin FET)裝置的透視示意圖。
第2圖係依據本揭露的一實施例之鰭型場效電晶體裝置的上視示意圖。
第3A-3D、4A-4B、5A-5C、6A-6B、7A-7B圖顯示依據本揭露的一實施例之製造鰭型場效電晶體裝置的各個階段之剖面示意圖。
第8圖係依據本揭露的其他實施例之鰭型場效電晶體裝置的剖面示意圖。
第9A-11A、9B-11B圖顯示依據本揭露的其他實施例之製造鰭型場效電晶體裝置的各個階段之剖面示意圖。
要瞭解的是本說明書以下的揭露內容提供許多不同的實施例或範例，以實施本發明的不同特徵。而本說明書以下的揭露內容是敘述各個構件及其排列方式的特定範例，以求簡化發明的說明。當然，這些特定的範例並非用以限定本發 明。例如，元件之尺寸並未侷限於揭露的範圍或數值，而取決於裝置的製程條件及/或需求性質，此外，本說明書以下的揭露內容敘述了將一第一特徵部件形成於一第二特徵部件之上或上方，即表示其包含了所形成的上述第一特徵部件與上述第二特徵部件是直接接觸的實施例，亦包含了尚可將附加的特徵部件形成於上述第一特徵部件與上述第二特徵部件之間，而使上述第一特徵部件與上述第二特徵部件可能未直接接觸的實施例。另外，為了簡化與清晰的目的，各種不同特徵部件可任意地以不同尺寸繪示，為了簡化與清晰的目的，本發明的一些圖示、一些層/特徵部件可能因重複使用而省略。
再者，為了方便描述圖式中一元件或特徵部件與另一(複數)元件或(複數)特徵部件的關係，可使用空間相關用語，例如“在...之下”、“下方”、“下部”、“上方”、“上部”及類似的用語。除了圖式所繪示的方位之外，空間相關用語涵蓋使用或操作中的裝置的不同方位。所述裝置也可被另外定位(例如旋轉90度或者位於其他方位)，並對應地解讀所使用的空間相關用語的描述。此外，用語”由...製成”可表示”包括”或”由..組成”。再者，在以下的製造過程中的各階段之前、之中及之後，可提供一些附加操作，且以下描述的一些操作可依據方法的附加實施例被代替或消除，操作/過程的順序為可互換的。
第1圖係具有鰭結構的半導體鰭型場效電晶體(Fin FET)裝置的透視示意圖。
鰭型場效電晶體裝置包含於其他特徵部件間的基底10、鰭結構20、隔離絕緣層30和閘極結構40。在這個實施例 中，基底10為矽基底。可替換的是，基底10可包含其他元素半導體，例如鍺；化合物半導體包含IV-IV族的化合物半導體例如碳化矽(SiC)和矽鍺(SiGe)，III-V族化合物半導體例如砷化鎵(GaAs)、磷化鎵(GaP)、氮化鎵(GaN)、磷化銦(InP)、砷化銦(InAs)、銻化銦(InSb)、砷磷化鎵(GaAsP)、氮化鋁鎵(AlGaN)、砷化銦鋁(AlInAs)、砷化鋁鎵(AlGaAs)、砷化鎵銦(GaInAs)、磷化銦鎵(GaInP)及/或砷磷化鎵銦(GaInAsP)；或上述的組合。在一實施例中，基底10是絕緣體上覆矽(silicon-on insulator,SOI)基底之矽層。非晶形(amorphous)基底，例如非晶形的矽(Si)、非晶形的碳化矽(SiC)，或絕緣材料例如氧化矽亦可作為基底10。基底10可包含已合適地摻雜雜質(例如p型或n型導電傳導性)的各種區域。
一或多個鰭結構20設置於基底10之上。鰭結構20可由與基底10相同材料製成，且可從基底連續地延伸。在這個實施例中，鰭結構20是由矽製成，鰭結構20之矽層可為本質的(intrinsic)或適當地摻雜n型雜質或p型雜質。
在第1圖中，一個鰭結構20設置於基底10之上，然而，鰭結構之數量並不侷限於一個，數量可多於一個，此外，一或多個虛設(dummy)鰭結構可設置於相鄰鰭結構20之兩側，以提升圖案化製程中的圖案逼真度(fidelity)。在一些實施例中，鰭結構20的寬度範圍從大約5奈米至大約40奈米，在其他一些實施例中，鰭結構20的寬度範圍從大約7奈米至大約12奈米。在一些實施例中，鰭結構20的高度範圍從大約100奈米至大約300奈米，在其他一些實施例中，鰭結構20的高度範圍從 大約50奈米至大約100奈米。
在閘極結構40下的鰭結構20之下部分可被稱為井區(well region)，而鰭結構20之上部分可被稱為通道區(channel region)。在閘極結構40下，井區嵌入於隔離絕緣層30中，而通道區從隔離絕緣層30凸出，通道區之下部分也可嵌入隔離絕緣層30至深度大約1奈米至大約5奈米。
在一些實施例中，井區之高度範圍從大約60奈米至大約100奈米，而通道區之高度範圍從大約40奈米至大約60奈米，在其他一些實施例中，通道區之高度範圍從大約38奈米至大約55奈米。
再者，鰭結構之間的空間及/或鰭結構與其他形成於基底10之上的元件之間的空間由包含絕緣材料的隔離絕緣層30(或稱為”淺溝槽隔離(shallow-trench-isolation,STI)”層)填充。隔離絕緣層30的絕緣材料可包含一或多層之氧化矽、氮化矽、氮氧化矽(SiON)、氮碳氧化矽(SiOCN)、摻氟矽玻璃(fluorinated silicate glass,FSG)或低介電常數(low-k)的介電材料。隔離絕緣層30透過低壓化學氣相沉積(LPCVD)、電漿輔助化學氣相沉積(plasma-CVD)或流動式化學氣相沉積(flowable CVD)形成。於流動式化學氣相沉積中，沉積流動式介電材料以代替氧化矽。流動式介電材料顧名思義可於沉積時”流動”以填入具高深寬比(high aspect ratio)的空隙或空間中。通常於含有矽(silicon-containing)的前驅物(precursor)中加入各種化學物使沉積的膜流動。在一些實施例中，加入氮氫鍵。流動式介電前驅物特別是流動式氧化矽前驅物的例子包含矽酸鹽 (silicate)、矽氧烷(siloxane)、甲基矽酸鹽(methyl silsesquioxane，MSQ)、氫矽酸鹽(hydrogen methyl silsesquioxane,HSQ)、甲基矽酸鹽與氫矽酸鹽混合物(MSQ/HSQ)、全氫矽氮烷(perhydrosilazane,TCPS)、全氫聚矽氮烷(per-hydro-polysilazane,PSZ)、四乙氧基矽烷(tetraethoxysilane,TEOS)或甲矽烷基胺(silyl-amine)，如三甲矽烷基(trisilylamine,TSA)。這些流動式氧化矽材料於多個操作製程(multiple-operation process)中形成。在沉積流動式膜之後，進行固化(cured)處理且接著進行退火處理(annealing)，以移除不需要的元素以形成氧化矽。在移除不需要的元素後，流動式膜稠密(densify)和收縮(shrink)。在一些實施例中，進行多個退火製程，流動式薄膜可固化及退火超過一次以上，流動式薄膜可摻雜硼(boron)及/或磷(phosphorous)。
第2圖係依據本揭露的一實施例之在閘極結構形成之後的鰭型場效電晶體裝置的上視示意圖。第3A-3D圖顯示沿第2圖之線段X1-X1(第3A圖)、線段Y1-Y1(第3B圖)、線段X2-X2(第3C圖)、線段Y2-Y2(第3D圖)之剖面示意圖。
如第2圖及第3A-3D圖所示，第一鰭結構20A及第二鰭結構20B形成於基底10之上。
依據一實施例製造鰭結構，形成遮罩層於基底之上，遮罩層透過例如熱氧化(thermal oxidation)製程及/或化學氣相沉積(chemical vapor deposition,CVD)製程形成。基底10例如為具有摻雜濃度範圍從大約1x1015原子/立方公分至大約1x1016原子/立方公分的p型矽或鍺基底。在其他一些實施例 中，基底10為具有摻雜濃度範圍從大約1x1015原子/立方公分至大約1x1016原子/立方公分的n型矽或鍺基底。在一些實施例中，遮罩層包含例如墊氧化物(pad oxide)(例如氧化矽)層和氮化矽遮罩層。
墊氧化物層可透過熱氧化製程或化學氣相沉積(CVD)製程形成，氮化矽遮罩層可由物理氣相沉積製程(physical vapor deposition,PVD)例如濺鍍(sputtering)法、化學氣相沉積(CVD)、電漿輔助化學氣相沉積(PECVD)、常壓化學氣相沉積(APCVD)、低壓化學氣相沉積(LPCVD)、高密度電漿化學氣相沉積(HDPCVD)、原子層沉積(ALD)及/或其他製程形成。
在一些實施例中，墊氧化物層的厚度範圍從大約2奈米至大約15奈米，氮化矽遮罩層的厚度範圍從大約2奈米至大約50奈米。進一步形成遮罩圖案於遮罩層之上，遮罩圖案為例如由微影(lithography)製程形成的光阻圖案(resist pattern)。
藉由使用遮罩圖案為蝕刻遮罩，形成墊氧化物層和氮化矽遮罩層之硬遮罩圖案。在一些實施例中，硬遮罩圖案的寬度範圍從大約5奈米至大約40奈米。在特定一些實施例中，硬遮罩圖案的寬度範圍從大約7奈米至大約12奈米。
藉由使用硬遮罩圖案為蝕刻遮罩，以乾蝕刻(dry etching)及/或濕蝕刻(wet etching)方法蝕刻出溝槽，將基底10圖案化形成鰭結構。在一些實施例中，鰭結構的寬度範圍從大約4奈米至大約15奈米，且在一些實施例中，兩個鰭結構之間的空間範圍從大約10奈米至大約50奈米。
在形成鰭結構20A及20B之後，形成隔離絕緣層30於鰭結構之間的空間及/或一個鰭結構與其他形成於基底10之上的元件之間的空間中。隔離絕緣層30也可稱為淺溝槽隔離(STI)層。隔離絕緣層30的絕緣材料可包含一或多層之氧化矽、氮化矽、氮氧化矽(SiON)、氮碳氧化矽(SiOCN)、摻氟矽玻璃(FSG)或低介電常數(low-k)的介電材料。隔離絕緣層30透過低壓化學氣相沉積(LPCVD)、電漿輔助化學氣相沉積(plasma-CVD)或流動式化學氣相沉積(flowable CVD)形成。於流動式化學氣相沉積中，沉積流動式介電材料以代替氧化矽，流動式介電材料顧名思義可於沉積時”流動”以填入具高深寬比(high aspect ratio)的空隙或空間。通常於含有矽(silicon-containing)的前驅物(precursor)中加入各種化學物，使沉積的膜流動。在一些實施例中，加入氮氫鍵。流動式介電前驅物特別是流動式氧化矽前驅物例如包含矽酸鹽(silicate)、矽氧烷(siloxane)、甲基矽酸鹽(methyl silsesquioxane，MSQ)、氫矽酸鹽(hydrogen methyl silsesquioxane,HSQ)、甲基矽酸鹽與氫矽酸鹽混合物(MSQ/HSQ)、全氫矽氮烷(perhydrosilazane,TCPS)、全氫聚矽氮烷(per-hydro-polysilazane,PSZ)、四乙氧基矽烷(tetraethoxysilane,TEOS)或甲矽烷基胺(silyl-amine)，如三甲矽烷基(trisilylamine,TSA)。這些流動式氧化矽材料形成於多個操作製程(multiple-operation process)中。在沉積流動式膜之後，進行固化(cured)處理且接著進行退火處理(annealing)，以移除不需要的元素以形成氧化矽。在移除不需要的元素後，流動式膜 稠密(densify)和收縮(shrink)。在一些實施例中，進行多個退火製程，流動式膜可固化及退火一次以上，流動式膜可摻雜硼(boron)及/或磷(phosphorous)。
首先，形成一厚層(thick layer)之隔離絕緣層30，使得鰭結構嵌入厚層中，且使厚層凹入，以露出鰭結構20A及20B的上部分。隔離絕緣層30凹入之後或之前，可實施熱製程(thermal process)例如退火製程，以提升隔離絕緣層30的品質。在特定實施例中，熱製程的實施係使用快速熱退火(rapid thermal annealing,RTA)，於溫度範圍從大約900度至大約1050度，在鈍化氣體環境例如氮氣(N2)、氬氣(Ar)或氦氣(He)環境中大約1.5秒至大約10秒。
形成隔離絕緣層30之後，第一閘極結構40A及第二閘極結構40B形成於鰭結構20A及20B之上。
為製造閘極結構，形成介電層及多晶矽層於隔離絕緣層30及露出的鰭結構20A和20B之上，接著實施圖案化製程以得到包含由多晶矽製成的閘極圖案43和介電層45之閘極結構。在一些實施例中，使用硬遮罩圖案化多晶矽層，且留在閘極圖案43上的硬遮罩作為蓋絕緣層47。硬遮罩(蓋絕緣層47)包含一或多層之絕緣材料。在一些實施例中，蓋絕緣層47包含氮化矽層形成於氧化矽層之上。在其他一些實施例中，蓋絕緣層47包含氧化矽層形成於氮化矽層之上。蓋絕緣層47之絕緣材料可透過化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)、電子束蒸鍍(e-beam evaporation)或其他適合的製程形成。在一些實施例中，介電層45可包含一或多層之氧化 矽、氧化氮、氮氧化矽、或高介電常數(high-k)的介電材料。在一些實施例中，介電層45之厚度範圍從大約2奈米至大約20奈米，在其他一些實施例中，介電層45之厚度範圍從大約2奈米至大約10奈米。在一些實施例中，閘極結構40A和40B之厚度範圍從大約50奈米至大約400奈米，在其他一些實施例中，閘極結構40A和40B之厚度範圍從大約100奈米至大約200奈米。
在這個實施例中，使用閘極取代(gate replacement)技術，因此，閘極圖案43及介電層45分別為接下來會被移除的虛設閘極電極及虛設閘極介電層。
再者，閘極側壁間隔元件54形成於閘極結構40A、40B之兩側壁，且鰭側壁間隔元件52也形成於鰭結構20A、20B之兩側壁。側壁間隔元件54、52包含一或多層之絕緣材料，例如二氧化矽(SiO2)、氮化矽(SiN)、氮氧化矽(SiON)、氮碳氧化矽(SiOCN)或氮碳化矽(SiCN)，且透過化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)、電子束蒸鍍(e-beam evaporation)或其他適合的製程形成。低介電常數(low-k)的介電材料可作為側壁間隔元件，側壁間隔元件54、52係藉由形成絕緣材料之毯覆層(blanket layer)和實施異向性(anisotropic)蝕刻形成。如第3B圖所示，露出鰭結構20A、20B之上表面。在一實施例中，側壁間隔元件層由氮化矽為主的材料製成，例如氮化矽(SiN)、氮氧化矽(SiON)、氮碳氧化矽(SiOCN)或氮碳化矽(SiCN)。在一實施例中，於帶有側壁間隔元件52的鰭結構20A與20B之間的空間S1之範圍從大約5奈米至大約30奈米。
接著，如第4A圖及第4B圖所示，部分移除(凹入)閘極側壁間隔元件54及鰭側壁間隔元件52之上部分。第4A圖係對應於第2圖之線段X1-X1的剖面示意圖，第4B圖係對應於第2圖之線段Y1-Y1的剖面示意圖。
藉由使用異向性乾蝕刻製程，部分移除(凹入)閘極側壁間隔元件54及鰭側壁間隔元件52之上部分，凹入量H1範圍從大約10奈米至大約50奈米。
在這個蝕刻過程中，鰭結構20A、20B之上部分也會被輕微地蝕刻，因此，鰭結構20A、20B之高度會降低H2量。
接著，如第5A-5C圖所示，源極/汲極結構60形成於鰭結構20A、20B之露出的上部分之上。第5A圖係對應於第2圖之線段X1-X1的剖面示意圖，第5B圖係對應於第2圖之線段Y1-Y1的剖面示意圖和第5C圖係對應於第2圖之線段X2-X2的剖面示意圖。
源極/汲極結構60由一或多層之具有與鰭結構20A、20B(通道區)不同晶格常數(lattice constant)的半導體材料製成。當鰭結構20A、20B由矽製成時，源極/汲極結構60包含用於n型通道(n-channel)鰭型場效電晶體的磷化矽(SiP)、碳化矽(SiC)或碳磷化矽(SiCP)及用於p型通道(p-channel)鰭型場效電晶體的矽鍺(SiGe)或鍺(Ge)。源極/汲極結構60係磊晶地形成於鰭結構20A、20B之上部分之上。由於形成鰭結構20A、20B之基底的結晶方向(crystal orientation)(例如(100)平面)，源極/汲極結構60側向地成長，且具有像鑽石(diamond-like)的形狀。在一實施例中，設定H2的量小於源極/汲極結構60側向成長的 量，側向成長的量係從鰭結構的中央量測，且側向成長的量之範圍從大約S1至大約1.4xS1(見第3B圖)。
源極/汲極結構60可藉由使用含矽的氣體如甲矽烷(SiH4)、乙矽烷(Si2H6)、二氯矽烷(SiCl2H2)和摻雜氣體(dopant gas)如磷化氫(PH3)，在大約80至150托(torr)的壓力下於約600℃至800℃的溫度下成長。n型通道鰭型場效電晶體的源極/汲極結構及p型通道鰭型場效電晶體的源極/汲極結構可透過分別的磊晶製程形成。
如第5B圖所示，由於鰭結構20A、20B之上部分從隔離絕緣層30及鰭側壁間隔元件52凸出，源極/汲極結構60形成於第一鰭結構20A及第二鰭結構20B之上部分的側表面及頂表面上。如第5A圖所示，源極/汲極結構60成長於鰭結構20A、20B之最上部分之上。
再者，由於鰭結構間相對小的空間，形成於第一鰭結構20A之上的源極/汲極結構60及形成於第二鰭結構20B之上的源極/汲極結構60會合併，使得孔洞或間隙(空氣間隙(air gap))65由合併的源極/汲極結構60、隔離絕緣層30、第一閘極結構40A之閘極側壁間隔元件54中的一個及第二閘極結構40B之閘極側壁間隔元件54中的一個形成。
在一些實施例中，孔洞65從隔離絕緣層30之表面開始的高度H3範圍從大約10奈米至大約40奈米。
接著，如第6A圖及第6B圖所示，矽化物層70形成於源極/汲極結構60之上。第6A圖係對應於第2圖之線段X1-X1的剖面示意圖，第6B圖係對應於第2圖之線段Y1-Y1的剖面示 意圖。
形成源極/汲極結構60之後，金屬材料如鎳(Ni)、鈦(Ti)、鉭(Ta)及/或鎢(W)形成於源極/汲極結構60之上，且實施退火製程以形成矽化物層70。在其他一些實施例中，矽化物材料例如矽化鎳(NiSi)、矽化鈦(TiSi)、矽化鉭(TaSi)及/或矽化鎢(WSi)形成於源極/汲極結構60之上，且可實施退火製程。退火製程實施於大約250℃至大約850℃的溫度。金屬材料或矽化物材料透過化學氣相沉積(CVD)或原子層沉積(ALD)形成。在一些實施例中，矽化物層70之厚度範圍從大約4奈米至大約10奈米。退火製程之前或之後，形成於隔離絕緣層30、蓋絕緣層47及側壁間隔元件52、54之上的金屬材料或矽化物材料藉由濕蝕刻(wet etching)製程選擇性地移除。
接著，如第7A及7B圖所示，形成金屬閘極結構，且接著形成接觸插塞(contact plug)。第7A圖係對應於第2圖之線段X1-X1的剖面示意圖，第7B圖係對應於第2圖之線段Y1-Y1的剖面示意圖。
形成矽化物層70之後，移除虛設閘極結構(虛設閘極電極43及虛設閘極介電層45)，且以金屬閘極結構(金屬閘極電極90及閘極介電層95)取代。
在特定實施例中，第一層間(interlayer)介電層形成於虛設閘極結構之上，且實施平坦化製程例如化學機械研磨(chemical mechanical polishing,CMP)製程或回蝕刻(etch-back)製程，以露出虛設閘極電極43之上表面，接著，透過適當的蝕刻製程分別移除虛設閘極電極43及虛設閘極介電層45，以形成 閘極開口(opening)。金屬閘極結構包含閘極介電層95及金屬閘極電極90形成於閘極開口中。
閘極介電層95可形成於設置在鰭結構20A、20B之通道層之上的界面(interface)層(未繪示)之上。在一些實施例中，界面層可包含氧化矽或氧化鍺，且界面層具有厚度0.2奈米至1.5奈米。在其他一些實施例中，界面層之厚度範圍從大約0.5奈米至大約1.0奈米。
閘極介電層95包含一或多層之介電材料例如氧化矽、氮化矽或高介電常數(high-k)的介電材料、其他適合的介電材料及/或上述的組合。高介電常數的介電材料的範例包含二氧化鉿(HfO2)、矽氧化鉿(HfSiO)、氮氧矽化鉿(HfSiON)、氧鉭化鉿(HfTaO)、氧鈦化鉿(HfTiO)、氧鋯化鉿(HfZrO)、氧化鋯、氧化鋁、氧化鈦、二氧化鉿-氧化鋁(HfO2-Al2O3)合金或其他適合的高介電常數的介電材料及/或上述的組合。閘極介電層95可透過例如化學氣相沉積(CVD)製程、物理氣相沉積(PVD)製程、原子層沉積(ALD)製程、高密度電漿化學氣相沉積(HDPCVD)製程或其他適合的製程及/或上述的組合形成。在一些實施例中，閘極介電層95的厚度範圍從大約1奈米至大約10奈米。在其他一些實施例中，閘極介電層95的厚度範圍可從大約2奈米至大約7奈米。
金屬閘極電極90形成於閘極介電層95之上。金屬閘極電極90包含一或多層之任何適合的金屬材料例如鋁、銅、鈦、鉭、鈷、鉬、氮化鉭、矽化鎳、矽化鈷、氮化鈦(TiN)、氮化鎢(WN)、鈦鋁(TiAl)、氮化鋁鈦(TiAlN)、碳氮化鉭 (TaCN)、碳化鉭(TaC)、氮矽化鉭(TaSiN)、金屬合金、其他適合的材料及/或上述的組合。
在本揭露的特定一些實施例中，一或多個功函數調整層(未繪示)插入於閘極介電層95與金屬閘極電極90之間。功函數調整層由導電材料製成，例如單層之氮化鈦(TiN)、氮化鉭(TaN)、碳化鉭鋁(TaAlC)、碳化鈦(TiC)、碳化鉭(TaC)、鈷(Co)、鋁(Al)、鈦鋁(TiAl)、鉿鈦(HfTi)、矽化鈦(TiSi)、矽化鉭(TaSi)或碳化鈦鋁(TiAlC)或多層之兩個或多個上述材料。在n通道鰭型場效型電晶體中，使用氮化鉭(TaN)、碳化鉭鋁(TaAlC)、氮化鈦(TiN)、碳化鈦(TiC)、鈷(Co)、鈦鋁(TiAl)、鉿鈦(HfTi)、矽化鈦(TiSi)和矽化鉭(TaSi)中的一或多個作為功函數調整層，在p通道鰭型場效型電晶體中，使用碳化鈦鋁(TiAlC)、鋁(Al)、鈦鋁(TiAl)、氮化鉭(TaN)、碳化鉭鋁(TaAlC)、氮化鈦(TiN)、碳化鈦(TiC)和鈷(Co)中的一或多個作為功函數調整層。
於沉積適當的材料作為金屬閘極結構之後，實施平坦化製程例如化學機械研磨(CMP)。
接著，第二層間介電層85形成於金屬閘極結構之上。在一些實施例中，作為接觸蝕刻停止層的絕緣層80形成於已形成的金屬閘極結構之上，且接著形成第二層間介電層85。
絕緣層80係一或多層之絕緣材料。在一實施例中，絕緣層80係透過化學氣相沉積(CVD)由氮化矽形成。
藉由使用包含微影製程的圖案化製程，接觸孔(contact hole)形成於第二層間介電層85及絕緣層80中，以露出 帶有矽化物層70的源極/汲極結構60。接著，以導電材料填充接觸孔，藉此形成接觸插塞(contact plug)100。接觸插塞100可包含一層或多層之任何適合金屬如鈷(Co)、鎢(W)、鈦(Ti)、鉭(Ta)、銅(Cu)、鋁(Al)及/或鎳(Ni)及/或上述金屬的氮化物。
形成接觸插塞100之後，更進一步實施CMOS製程，以形成各種特徵部件如額外的層間介電層、接觸/導孔(contact/via)、內連線金屬層(interconnect metal layer)及鈍化層(passivation layer)等等。
第8圖係依據本揭露的其他實施例之鰭型場效電晶體裝置的剖面示意圖。在第8圖之實施例中，三個鰭結構設置於基底10之上，且兩個孔洞65形成於相鄰的兩個鰭結構之間的空間中。
第9A-11B圖顯示依據本揭露的其他實施例之製造鰭型場效電晶體裝置的各個階段之剖面示意圖。在這個實施例中，形成矽化物層的時間點與以上的實施例不同，而與以上的實施例相同或相似的設置、材料或操作可使用於這個實施例中，且可省略他們的詳細敘述。
如第5A-5C圖所示之源極/汲極結構60形成之後，如第9A及9B圖所示，形成金屬閘極結構90和95、絕緣層80(接觸蝕刻停止層)及層間介電層85，而並未形成矽化物層。第9A圖係對應於第2圖之線段X1-X1的剖面示意圖，第9B圖係對應於第2圖之線段Y1-Y1的剖面示意圖。
接著，如第10A及10B圖所示，形成接觸孔105於絕緣層80及層間介電層85中，以露出源極/汲極結構60之上表 面，且接著形成矽化物層75於源極/汲極結構60之上表面。第10A圖係對應於第2圖之線段X1-X1的剖面示意圖，第10B圖係對應於第2圖之線段Y1-Y1的剖面示意圖。
如第11A及11B圖所示，形成矽化物層75之後，形成導電材料於接觸孔105中，藉此形成接觸插塞100。第11A圖係對應於第2圖之線段X1-X1的剖面示意圖，第11B圖係對應於第2圖之線段Y1-Y1的剖面示意圖。
形成接觸插塞100之後，更進一步實施CMOS製程，以形成各種特徵部件如額外的層間介電層、接觸/導孔(contact/via)、內連線金屬層(interconnect metal layer)及鈍化層(passivation layer)等等。
在本揭露中，由於孔洞形成於源極/汲極結構與隔離絕緣層(STI)之間，可降低在源極/汲極結構的寄生電容(parasitic capacitance)。
可以理解的是，並不是所有的優點都已於此描述中討論，不需要有特定的優點對應所有的實施例和範例，且其他一些實施例或範例可提供不同的優點。
根據本揭露之一方面，包含鰭型場效電晶體之半導體裝置的製造方法中，形成第一鰭結構及第二鰭結構於基底之上，第一鰭結構及第二鰭結構於上視圖中沿第一方向延伸。形成隔離絕緣層於基底之上使得第一鰭結構及第二鰭結構之下部分嵌入隔離絕緣層，且第一鰭結構及第二鰭結構之上部分從隔離絕緣層露出。形成閘極結構於部分的第一鰭結構及第二鰭結構之上，閘極結構包含閘極圖案、設置於閘極圖案與第一 鰭結構和第二鰭結構之間的介電層以及設置於閘極圖案之上的蓋絕緣層，閘極結構於上視圖中沿與第一方向交叉的第二方向延伸。形成閘極側壁間隔元件於閘極結構之側壁上，使閘極側壁間隔元件之上部分凹入。在未被閘極結構及閘極側壁間隔元件覆蓋的第一鰭結構之上形成第一源極/汲極區結構，及在未被閘極結構及閘極側壁間隔元件覆蓋的第二鰭結構之上形成第二源極/汲極區結構。在使閘極側壁元件之上部分凹入的步驟中，也使未被閘極結構覆蓋的第一鰭結構及第二鰭結構之上部分凹入。在形成第一源極/汲極區結構的步驟中，第一源極/汲極區結構形成於凹入的第一鰭結構及第二鰭結構之側表面及頂表面之上。合併第一源極/汲極區結構及第二源極/汲極區結構，使得孔洞形成於合併的第一源極/汲極區結構及第二源極/汲極區結構與隔離絕緣層之間。
根據本揭露之另一方面，包含鰭型場效電晶體之半導體裝置的製造方法中，形成第一鰭結構及第二鰭結構於基底之上，第一鰭結構及第二鰭結構於上視圖中沿第一方向延伸。形成隔離絕緣層於基底之上，使得第一鰭結構及第二鰭結構之下部分嵌入隔離絕緣層，且第一鰭結構及第二鰭結構之上部分從隔離絕緣層露出。形成第一閘極結構及第二閘極結構於部分的第一鰭結構及第二鰭結構之上，每個第一閘極結構及第二閘極結構包含閘極圖案、設置於閘極圖案與第一鰭結構和第二鰭結構之間的介電層及設置於閘極圖案之上的蓋絕緣層，第一閘極結構及第二閘極結構於上視圖中沿與第一方向交叉的第二方向延伸。形成第一閘極側壁間隔元件於第一閘極結構之 側壁上，及形成第二閘極側壁間隔元件於第二閘極結構之側壁上。使第一閘極側壁間隔元件及第二閘極側壁間隔元件之上部分凹入。在未被第一閘極結構及第二閘極結構和第一閘極側壁間隔元件及第二閘極側壁間隔元件覆蓋的第一鰭結構之上形成第一源極/汲極區結構，及在未被第一閘極結構及第二閘極結構和第一閘極側壁間隔元件及第二閘極側壁間隔元件覆蓋的第二鰭結構之上形成第二源極/汲極區結構。在使第一閘極側壁間隔元件及第二閘極側壁間隔元件之上部分凹入的步驟中，也使未被第一閘極結構及第二閘極結構覆蓋的第一鰭結構及第二鰭結構之上部分凹入。在形成第一源極/汲極區結構的步驟中，第一源極/汲極區結構形成於凹入的第一鰭結構及第二鰭結構之側表面及頂表面之上。合併第一源極/汲極區結構及第二源極/汲極區結構，使得孔洞由合併的第一源極/汲極區結構及第二源極/汲極區結構、隔離絕緣層、第一閘極側壁間隔元件中的一個及第二閘極側壁間隔元件中的一個形成，前述之第一閘極側壁間隔元件中的一個面對前述之第二閘極側壁間隔元件中的一個。
根據本揭露之另一方面，半導體裝置包含隔離絕緣層、第一鰭結構及第二鰭結構、第一閘極結構及源極/汲極結構。隔離絕緣層設置於基底之上。第一鰭結構及第二鰭結構兩者皆設置於基底之上，第一鰭結構及第二鰭結構於上視圖中沿第一方向延伸，第一鰭結構及第二鰭結構之上部分從隔離絕緣層露出。第一閘極結構設置於部分的第一鰭結構及第二鰭結構之上，且第一閘極結構沿與第一方向交叉的第二方向延伸。 源極/汲極結構形成於未被第一閘極結構覆蓋且從隔離絕緣層露出的第一鰭結構及第二鰭結構之上部分上，且包裹每一個露出的第一鰭結構及第二鰭結構之側表面及頂表面，孔洞形成於源極/汲極結構與隔離絕緣層之間。
以上概略說明了本揭露數個實施例的特徵部件，使所屬技術領域中具有通常知識者對於本揭露的概念可更為容易理解。所屬技術領域中具有通常知識者應瞭解到本說明書可作為其他結構或製程的變更或設計基礎，以實現相同於本揭露實施例的目的及/或獲得相同的優點。所屬技術領域中具有通常知識者也可理解與上述等同的結構或製程並未脫離本揭露之精神及保護範圍內，且可在不脫離本揭露之精神及範圍內，當可作更動、替代與潤飾。
10‧‧‧基底
20A‧‧‧第一鰭結構
30‧‧‧隔離絕緣層
52‧‧‧鰭側壁間隔元件
54‧‧‧閘極側壁間隔元件
60‧‧‧源極/汲極結構
70‧‧‧矽化物層
80‧‧‧絕緣層
85‧‧‧第二層間介電層
90‧‧‧金屬閘極電極
95‧‧‧閘極介電層
100‧‧‧接觸插塞

Claims (16)

  1. 一種包含鰭型場效電晶體之半導體裝置的製造方法，包括：形成一第一鰭結構及一第二鰭結構於一基底之上，該第一鰭結構及該第二鰭結構於上視圖中沿一第一方向延伸；形成一隔離絕緣層於該基底之上，使得該第一鰭結構及該第二鰭結構之下部分嵌入該隔離絕緣層，且該第一鰭結構及該第二鰭結構之上部分從該隔離絕緣層露出；形成一閘極結構於部分的該第一鰭結構及該第二鰭結構之上，該閘極結構包含一閘極圖案、設置於該閘極圖案與該第一鰭結構和該第二鰭結構之間的一介電層以及設置於該閘極圖案之上的一蓋絕緣層，該閘極結構於上視圖中沿與該第一方向交叉的一第二方向延伸；形成複數個閘極側壁間隔元件於該閘極結構之複數個側壁上；使該些閘極側壁間隔元件之上部分凹入；以及在未被該閘極結構及該些閘極側壁間隔元件覆蓋的該第一鰭結構之上形成一第一源極/汲極區結構，及在未被該閘極結構及該些閘極側壁間隔元件覆蓋的該第二鰭結構之上形成一第二源極/汲極區結構，其中：在使該些閘極側壁元件之上部分凹入的步驟中，也使未被該閘極結構覆蓋的該第一鰭結構及該第二鰭結構之上部分凹入；在形成該第一源極/汲極區結構的步驟中，該第一源極/汲極區結構形成於凹入的該第一鰭結構及該第二鰭結構之側表 面及一頂表面之上；且合併該第一源極/汲極區結構及該第二源極/汲極區結構，使得一孔洞形成於合併的該第一源極/汲極區結構及該第二源極/汲極區結構與該隔離絕緣層之間。
  2. 如申請專利範圍第1項所述之包含鰭型場效電晶體之半導體裝置的製造方法，其中在形成該些閘極側壁間隔元件的步驟中，形成複數個鰭側壁間隔元件於該第一鰭結構及該第二鰭結構之複數個側壁上。
  3. 如申請專利範圍第2項所述之包含鰭型場效電晶體之半導體裝置的製造方法，其中在使該些閘極側壁間隔元件之上部分凹入的步驟中，也使該些鰭側壁間隔元件之上部分凹入。
  4. 如申請專利範圍第1項所述之包含鰭型場效電晶體之半導體裝置的製造方法，在形成該第一源極/汲極區結構及該第二源極/汲極區結構之後，更包括：形成一矽化物層於合併的該第一源極/汲極區結構及該第二源極/汲極區結構之上；形成一層間絕緣層；形成一開口於該層間絕緣層中；以及形成一導電材料於該開口中之該矽化物層之上。
  5. 如申請專利範圍第4項所述之包含鰭型場效電晶體之半導體裝置的製造方法，其中該矽化物層在形成該層間絕緣層之前形成。
  6. 如申請專利範圍第4項所述之包含鰭型場效電晶體之半導 體裝置的製造方法，其中該矽化物層在該開口形成之後形成。
  7. 如申請專利範圍第4項所述之包含鰭型場效電晶體之半導體裝置的製造方法，更包括於形成該層間絕緣層之前，形成一絕緣層。
  8. 如申請專利範圍第1項所述之包含鰭型場效電晶體之半導體裝置的製造方法，更包括在形成該第一源極/汲極區結構及該第二源極/汲極區結構之後：移除該蓋絕緣層、該閘極圖案及該介電層，以形成一閘極空間；形成一閘極介電層於該閘極空間中；以及於該閘極空間中形成一閘極電極於該閘極介電層上。
  9. 一種包含鰭型場效電晶體之半導體裝置的製造方法，包括：形成一第一鰭結構及一第二鰭結構於一基底之上，該第一鰭結構及該第二鰭結構於上視圖中沿一第一方向延伸；形成一隔離絕緣層於該基底之上，使得該第一鰭結構及該第二鰭結構之下部分嵌入該隔離絕緣層，且該第一鰭結構及該第二鰭結構之上部分從該隔離絕緣層露出；形成一第一閘極結構及一第二閘極結構於部分的該第一鰭結構及該第二鰭結構之上，每個該第一閘極結構及該第二閘極結構包含一閘極圖案、設置於該閘極圖案與該第一鰭結構和該第二鰭結構之間的一介電層及設置於該閘極圖案之上的一蓋絕緣層，該第一閘極結構及該第二閘極結構於上視圖中沿與該第一方向交叉的一第二方向延伸； 形成複數個第一閘極側壁間隔元件於該第一閘極結構之複數個側壁上及形成複數個第二閘極側壁間隔元件於該第二閘極結構之複數個側壁上；使該些第一閘極側壁間隔元件及該些第二閘極側壁間隔元件之上部分凹入；以及在未被該第一閘極結構及該第二閘極結構和該些第一閘極側壁間隔元件及該些第二閘極側壁間隔元件覆蓋的該第一鰭結構之上形成一第一源極/汲極區結構，及在未被該第一閘極結構及該第二閘極結構和該些第一閘極側壁間隔元件及該些第二閘極側壁間隔元件覆蓋的該第二鰭結構之上形成一第二源極/汲極區結構，其中：在使該些第一閘極側壁間隔元件及該些第二閘極側壁間隔元件之上部分凹入的步驟中，也使未被該第一閘極結構及該第二閘極結構覆蓋的該第一鰭結構及該第二鰭結構之上部分凹入；在形成該第一源極/汲極區結構的步驟中，該第一源極/汲極區結構形成於凹入的該第一鰭結構及該第二鰭結構之側表面及一頂表面之上；且合併該第一源極/汲極區結構及該第二源極/汲極區結構，使得一孔洞由合併的該第一源極/汲極區結構及該第二源極/汲極區結構、該隔離絕緣層、該些第一閘極側壁間隔元件中的一個及該些第二閘極側壁間隔元件中的一個形成，該些第一閘極側壁間隔元件中的該一個面對該些第二閘極側壁間隔元件中的該一個。
  10. 如申請專利範圍第9項所述之包含鰭型場效電晶體之半導體裝置的製造方法，在形成該第一源極/汲極區結構及該第二源極/汲極區結構之後，更包括：形成一矽化物層於合併的該第一源極/汲極區結構及該第二源極/汲極區結構之上；在形成該矽化物層之後，形成一層間絕緣層；形成一開口於該層間絕緣層中；以及形成一導電材料於該開口中之該矽化物層之上。
  11. 如申請專利範圍第9項所述之包含鰭型場效電晶體之半導體裝置的製造方法，更包括在形成該第一源極/汲極區結構及該第二源極/汲極區結構之後：形成一層間絕緣層；形成一開口於該層間絕緣層中；形成一矽化物層於該開口中露出之合併的該第一源極/汲極區結構及該第二源極/汲極區結構上；以及形成一導電材料於該開口中之該矽化物層。
  12. 一種半導體裝置，包括：一隔離絕緣層，設置於一基底之上；一第一鰭結構及一第二鰭結構，皆設置於該基底之上，該第一鰭結構及該第二鰭結構於上視圖中沿一第一方向延伸，該第一鰭結構及該第二鰭結構之複數個上部分從該隔離絕緣層露出；一第一閘極結構，設置於部分的該第一鰭結構及該第二鰭結構之上，該第一閘極結構沿與該第一方向交叉的一第二方 向延伸；以及一源極/汲極結構形成於未被該第一閘極結構覆蓋且從該隔離絕緣層露出的該第一鰭結構及該第二鰭結構之該些上部分上，且包裹每一個露出的該第一鰭結構及該第二鰭結構之側表面及一頂表面，其中一孔洞形成於該源極/汲極結構與該隔離絕緣層之間。
  13. 如申請專利範圍第12項所述之半導體裝置，更包括：一層間介電層設置於該第一閘極結構及該源極/汲極結構之上；一矽化物層形成於該源極/汲極結構上；以及一接觸插塞形成於該層間介電層中且與該矽化物層連接。
  14. 如申請專利範圍第13項所述之半導體裝置，其中該矽化物層並非形成於未與該接觸插塞接觸的該源極/汲極結構之一上表面之一部分上。
  15. 如申請專利範圍第13項所述之半導體裝置，更包括一絕緣層設置於該源極/汲極結構與該層間介電層之間。
  16. 如申請專利範圍第12項所述之半導體裝置，更包括一第二閘極結構設置於部分的該第一鰭結構與該第二鰭結構之上，其中：該第二閘極結構沿與該第一方向交叉的該第二方向延伸，且與在上視圖中在該第一方向之該第一閘極結構平行排列；且該孔洞形成於該第一鰭結構及該第二鰭結構和該第一閘極結構及該第二閘極結構於上視圖中定義的一區域。
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