CN113675194A - 半导体器件及其形成方法 - Google Patents
半导体器件及其形成方法 Download PDFInfo
- Publication number
- CN113675194A CN113675194A CN202110158373.1A CN202110158373A CN113675194A CN 113675194 A CN113675194 A CN 113675194A CN 202110158373 A CN202110158373 A CN 202110158373A CN 113675194 A CN113675194 A CN 113675194A
- Authority
- CN
- China
- Prior art keywords
- source
- drain
- feature
- layer
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 162
- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
- 238000002161 passivation Methods 0.000 claims description 84
- 239000000758 substrate Substances 0.000 claims description 55
- 229910052710 silicon Inorganic materials 0.000 claims description 48
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 47
- 239000010703 silicon Substances 0.000 claims description 47
- 238000000151 deposition Methods 0.000 claims description 44
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 43
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 21
- CWQXQMHSOZUFJS-UHFFFAOYSA-N molybdenum disulfide Chemical compound S=[Mo]=S CWQXQMHSOZUFJS-UHFFFAOYSA-N 0.000 claims description 16
- 229910052732 germanium Inorganic materials 0.000 claims description 13
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 12
- 238000000059 patterning Methods 0.000 claims description 12
- ROUIDRHELGULJS-UHFFFAOYSA-N bis(selanylidene)tungsten Chemical compound [Se]=[W]=[Se] ROUIDRHELGULJS-UHFFFAOYSA-N 0.000 claims description 8
- JPIIVHIVGGOMMV-UHFFFAOYSA-N ditellurium Chemical compound [Te]=[Te] JPIIVHIVGGOMMV-UHFFFAOYSA-N 0.000 claims description 8
- 229910052735 hafnium Inorganic materials 0.000 claims description 8
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 8
- 229910052982 molybdenum disulfide Inorganic materials 0.000 claims description 8
- 239000010410 layer Substances 0.000 description 342
- 239000000463 material Substances 0.000 description 42
- 229910021332 silicide Inorganic materials 0.000 description 39
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 37
- 229910052751 metal Inorganic materials 0.000 description 26
- 239000002184 metal Substances 0.000 description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 25
- 229910052581 Si3N4 Inorganic materials 0.000 description 23
- 229910052814 silicon oxide Inorganic materials 0.000 description 22
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 21
- 238000005530 etching Methods 0.000 description 20
- 239000007789 gas Substances 0.000 description 20
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 18
- 125000006850 spacer group Chemical group 0.000 description 18
- 239000010936 titanium Substances 0.000 description 14
- 238000000231 atomic layer deposition Methods 0.000 description 13
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 12
- 239000003989 dielectric material Substances 0.000 description 12
- 238000001312 dry etching Methods 0.000 description 12
- 239000000203 mixture Substances 0.000 description 12
- 238000002955 isolation Methods 0.000 description 11
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 10
- 239000010941 cobalt Substances 0.000 description 10
- 229910017052 cobalt Inorganic materials 0.000 description 10
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 10
- 239000010949 copper Substances 0.000 description 10
- 229910052715 tantalum Inorganic materials 0.000 description 10
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 10
- 239000005350 fused silica glass Substances 0.000 description 9
- 230000003647 oxidation Effects 0.000 description 9
- 238000007254 oxidation reaction Methods 0.000 description 9
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 8
- 239000005380 borophosphosilicate glass Substances 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 8
- 239000005360 phosphosilicate glass Substances 0.000 description 8
- 238000000206 photolithography Methods 0.000 description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 7
- 229910000449 hafnium oxide Inorganic materials 0.000 description 7
- 229910052759 nickel Inorganic materials 0.000 description 7
- 229910052719 titanium Inorganic materials 0.000 description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 7
- 229910052721 tungsten Inorganic materials 0.000 description 7
- 239000010937 tungsten Substances 0.000 description 7
- 238000001039 wet etching Methods 0.000 description 7
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 6
- HEDRZPFGACZZDS-UHFFFAOYSA-N Chloroform Chemical compound ClC(Cl)Cl HEDRZPFGACZZDS-UHFFFAOYSA-N 0.000 description 6
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 6
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 6
- RVSGESPTHDDNTH-UHFFFAOYSA-N alumane;tantalum Chemical compound [AlH3].[Ta] RVSGESPTHDDNTH-UHFFFAOYSA-N 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 6
- 239000000460 chlorine Substances 0.000 description 6
- 230000008021 deposition Effects 0.000 description 6
- 239000002019 doping agent Substances 0.000 description 6
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 6
- 238000000927 vapour-phase epitaxy Methods 0.000 description 6
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 5
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000011737 fluorine Substances 0.000 description 5
- 229910052731 fluorine Inorganic materials 0.000 description 5
- 229910052707 ruthenium Inorganic materials 0.000 description 5
- 239000005368 silicate glass Substances 0.000 description 5
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 5
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 4
- 230000000295 complement effect Effects 0.000 description 4
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 238000001035 drying Methods 0.000 description 4
- 238000001704 evaporation Methods 0.000 description 4
- 230000008020 evaporation Effects 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 4
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 4
- 238000001451 molecular beam epitaxy Methods 0.000 description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 4
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
- 229910003468 tantalcarbide Inorganic materials 0.000 description 4
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 4
- 229910001928 zirconium oxide Inorganic materials 0.000 description 4
- ZCYVEMRRCGMTRW-UHFFFAOYSA-N 7553-56-2 Chemical compound [I] ZCYVEMRRCGMTRW-UHFFFAOYSA-N 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 229910015844 BCl3 Inorganic materials 0.000 description 3
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 description 3
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 3
- -1 GaAsP Inorganic materials 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 3
- 229910021529 ammonia Inorganic materials 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 description 3
- 229910052794 bromium Inorganic materials 0.000 description 3
- VZGDMQKNWNREIO-UHFFFAOYSA-N carbon tetrachloride Substances ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 description 3
- 229910052801 chlorine Inorganic materials 0.000 description 3
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 229910052740 iodine Inorganic materials 0.000 description 3
- 239000011630 iodine Substances 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 239000011733 molybdenum Substances 0.000 description 3
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000011295 pitch Substances 0.000 description 3
- 210000002381 plasma Anatomy 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- 229910004129 HfSiO Inorganic materials 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- GEIAQOFPUVMAGM-UHFFFAOYSA-N Oxozirconium Chemical compound [Zr]=O GEIAQOFPUVMAGM-UHFFFAOYSA-N 0.000 description 2
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910002370 SrTiO3 Inorganic materials 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 229910006501 ZrSiO Inorganic materials 0.000 description 2
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 2
- OBZUDFAHIZFVHI-UHFFFAOYSA-N [La].[Si]=O Chemical compound [La].[Si]=O OBZUDFAHIZFVHI-UHFFFAOYSA-N 0.000 description 2
- DBOSVWZVMLOAEU-UHFFFAOYSA-N [O-2].[Hf+4].[La+3] Chemical compound [O-2].[Hf+4].[La+3] DBOSVWZVMLOAEU-UHFFFAOYSA-N 0.000 description 2
- FAUIDPFKEVQLLR-UHFFFAOYSA-N [O-2].[Zr+4].[Si+4].[O-2].[O-2].[O-2] Chemical compound [O-2].[Zr+4].[Si+4].[O-2].[O-2].[O-2] FAUIDPFKEVQLLR-UHFFFAOYSA-N 0.000 description 2
- OQNXPQOQCWVVHP-UHFFFAOYSA-N [Si].O=[Ge] Chemical compound [Si].O=[Ge] OQNXPQOQCWVVHP-UHFFFAOYSA-N 0.000 description 2
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 description 2
- ZDZIJHSDFUXADX-UHFFFAOYSA-N azanium hydrogen peroxide hydroxide hydrate Chemical compound O.OO.[OH-].[NH4+] ZDZIJHSDFUXADX-UHFFFAOYSA-N 0.000 description 2
- 229910002113 barium titanate Inorganic materials 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000011066 ex-situ storage Methods 0.000 description 2
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 2
- ZQXQADNTSSMHJI-UHFFFAOYSA-N hafnium(4+) oxygen(2-) tantalum(5+) Chemical compound [O-2].[Ta+5].[Hf+4] ZQXQADNTSSMHJI-UHFFFAOYSA-N 0.000 description 2
- KQHQLIAOAVMAOW-UHFFFAOYSA-N hafnium(4+) oxygen(2-) zirconium(4+) Chemical compound [O--].[O--].[O--].[O--].[Zr+4].[Hf+4] KQHQLIAOAVMAOW-UHFFFAOYSA-N 0.000 description 2
- 230000036039 immunity Effects 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000012705 liquid precursor Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910001092 metal group alloy Inorganic materials 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000002086 nanomaterial Substances 0.000 description 2
- 239000002135 nanosheet Substances 0.000 description 2
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- HWEYZGSCHQNNEH-UHFFFAOYSA-N silicon tantalum Chemical compound [Si].[Ta] HWEYZGSCHQNNEH-UHFFFAOYSA-N 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 description 2
- 238000009736 wetting Methods 0.000 description 2
- 229910002938 (Ba,Sr)TiO3 Inorganic materials 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910010252 TiO3 Inorganic materials 0.000 description 1
- VSTCOQVDTHKMFV-UHFFFAOYSA-N [Ti].[Hf] Chemical compound [Ti].[Hf] VSTCOQVDTHKMFV-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- AJGDITRVXRPLBY-UHFFFAOYSA-N aluminum indium Chemical compound [Al].[In] AJGDITRVXRPLBY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000009969 flowable effect Effects 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- KUVFGOLWQIXGBP-UHFFFAOYSA-N hafnium(4+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Hf+4] KUVFGOLWQIXGBP-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000002070 nanowire Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8221—Three dimensional integrated circuits stacked in different levels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02293—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
- H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66818—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the channel being thinned after patterning, e.g. sacrificial oxidation on fin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Nanotechnology (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
- Semiconductor Memories (AREA)
Abstract
根据本公开的实施例的半导体器件包括第一晶体管和设置在第一晶体管上方的第二晶体管。第一晶体管包括彼此竖直堆叠的多个沟道构件以及邻接多个沟道构件的第一源极/漏极部件。第二晶体管包括鳍结构和邻接鳍结构的第二源极/漏极部件。半导体器件还包括电连接第一源极/漏极部件和第二源极/漏极部件的导电部件。本申请的实施例还提供了形成半导体器件的方法。
Description
技术领域
本申请的实施例涉及半导体器件及其形成方法。
背景技术
半导体集成电路(IC)工业经历了快速增长。IC材料和设计的技术进步产生了多代IC,其中,每一代都具有比先前一代更小且更复杂的电路。在IC演进过程中,随着几何尺寸(即,可使用制造工艺创建的最小组件(或线))的减小,功能密度(即,单位芯片面积中的互连器件的数量)通常在增加。这种规模缩小工艺通常通过增加产量效率和降低相关成本来提供很多益处。这种按比例缩小工艺也增大了加工和制造IC的复杂度。
例如,随着集成电路(IC)技术朝着更小的技术节点发展,已经引入了多栅极器件,以通过增加栅极-沟道耦合、减小截止状态电流和减小短沟道效应(SCE)来改善栅极控制。多栅极器件通常是指具有栅极结构或其一部分设置在沟道区域的多于一侧上方的器件。鳍式场效应晶体管(FinFET)和多桥沟道(MBC)晶体管是多栅极器件的示例,这些器件已成为高性能和低泄漏应用的流行和有希望的候选者。FinFET的升高的沟道在多于一侧上被栅极围绕(例如,栅极围绕从衬底延伸的半导体材料“鳍”的顶部和侧壁)。MBC晶体管的栅极结构可以部分或全部围绕沟道区域延伸,以提供对两侧或更多侧沟道区域的访问。由于MBC晶体管的栅极结构围绕沟道区域,所以MBC晶体管也可以称为环绕栅极晶体管(SGT)或全环栅(GAA)晶体管。MBC晶体管的沟道区域可以由纳米线、纳米片、其他纳米结构和/或其他合适的结构形成。
互补金属氧化物半导体场效应晶体管(CMOSFET或CFET)由于其高抗噪性和低静态功耗而在半导体工业中占主导地位。尽管现有的CFET结构通常足以满足其预期目的,但不是在所有方面都令人满意。
发明内容
在一些实施例中,一种半导体器件,包括:第一晶体管,包括:彼此竖直堆叠的多个沟道构件,和邻接所述多个沟道构件的第一源极/漏极部件;第二晶体管,设置在所述第一晶体管上方,包括:鳍结构,和邻接所述鳍结构的第二源极/漏极部件;以及导电部件,电连接所述第一源极/漏极部件和所述第二源极/漏极部件。
在一些实施例中,一种半导体器件,包括:第一晶体管,包括:第一源极部件和第一漏极部件,和彼此竖直堆叠并且在所述第一源极部件和所述第一漏极部件之间延伸的多个沟道构件;以及第二晶体管,设置在所述第一晶体管上方,包括:第二源极部件和第二漏极部件,和在所述第二源极部件和所述第二漏极部件之间延伸的鳍结构,其中,所述第二源极部件直接位于所述第一源极部件上方,其中,所述第二漏极部件直接位于所述第一漏极部件上方。
在一些实施例中,一种形成半导体器件的方法,包括:在第一衬底上形成第一晶体管,其中,所述第一晶体管包括:第一源极部件和第一漏极部件,彼此竖直堆叠并且在所述第一源极部件和所述第一漏极部件之间延伸的多个沟道构件,和包围在所述多个沟道构件中的每一个周围的第一栅极结构;在所述第一晶体管上方沉积第一钝化层;在第二衬底上方形成外延层;在所述外延层上方沉积第二钝化层;将所述第二钝化层接合至所述第一钝化层;接合后去除所述第二衬底;图案化所述外延层以在所述多个沟道构件上方形成鳍结构;以及形成第二栅极结构以包围在所述鳍结构上方,其中,所述第二栅极结构与所述第一栅极结构接触。
本申请的实施例提供了竖直定向的互补晶体管。
附图说明
当结合附图进行阅读时,从以下详细描述可更好地理解本发明。应该强调,根据工业中的标准实践,各个部件未按比例绘制并且仅仅用于说明的目的。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1示出根据本公开的一个或多个方面的用于形成具有竖直定向的互补晶体管的半导体器件的方法的流程图。
图2-图39示出根据本公开的一个或多个方面的在根据图1的方法的制造工艺期间的工件的局部截面图。
图40示出根据本公开的一个或多个方面的半导体器件的替代实施例。
具体实施方式
以下公开内容提供了许多不同实施例或实例,用于实现所提供主题的不同特征。以下将描述组件和布置的具体实例以简化本发明。当然,这些仅是实例并且不意欲限制本发明。例如,在以下描述中,在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例,也可以包括形成在第一部件和第二部件之间的附加部件使得第一部件和第二部件不直接接触的实施例。而且,本发明在各个实例中可以重复参考数字和/或字母。这种重复仅是为了简明和清楚,其自身并不表示所论述的各个实施例和/或配置之间的关系。
为了便于描述,本文中可以使用诸如“在...下方”、“在...下面”、“下部”、“在...上面”、“上部”等的空间关系术语,以描述如图中所示的一个元件或部件与另一元件或部件的关系。空间相对术语旨在包括除了附图中所示的方位之外,在使用中或操作中的器件的不同方位。装置可以以其他方式定位(旋转90度或在其他方位),并且在本文中使用的空间关系描述符可以同样地作相应地解释。
此外,当用“约”、“近似”等描述数值或数值的范围时,该词语旨在涵盖在合理范围内的数字,考虑到如本领域普通技术人员所理解的在制造期间固有地产生的变化。例如,基于与制造具有与数值相关联的特征的部件相关联的已知制造公差,数值或数值的范围涵盖包括所述数值的合理范围,诸如在所述数值的+/-10%以内。例如,厚度为“约5nm”的材料层可以涵盖4.25nm至5.75nm的尺寸范围,其中本领域普通技术人员已知与沉积材料层相关的制造公差为+/-15%。另外,本发明可以在各个实例中重复附图标号和/或字母。这种重复仅是为了简明和清楚,其自身并不表示所论述的各个实施例和/或配置之间的关系。
互补金属氧化物半导体场效应晶体管(CMOSFET或CFET)由于其高抗噪性和低静态功耗而在半导体工业中占主导地位。常规CFET包括并排设置在同一衬底上的n型FET(NFET)和p型FET(PFET),并且NFET和PFET共享相同的结构。例如,在一些常规设计中,NFET和PFET都是平面器件,都是FinFET,或者都是MBC晶体管。随着针对先进技术节点,器件尺寸不断缩小,至少出现了两个挑战。首先,共面CFET的占用面积比NFET或PFET大。其次,PFET中的空穴迁移率继续落后于NFET中的电子迁移率。
本公开提供了竖直定向的混合CFET的工艺和结构,以解决上述两个挑战。通过竖直定向,根据本公开的CFET包括底部晶体管和设置在底部晶体管上方的顶部晶体管。在一些情况下,底部晶体管是p型晶体管,顶部晶体管是n型晶体管。在其他情况下,底部晶体管是n型晶体管,顶部晶体管是p型晶体管。通过混合,根据本公开的CFET包括p型FinFET(p-FinFET)和n型MBC(n-MBC)晶体管。因此,本公开的CFET包括作为底部晶体管的p-FinFET和作为顶部晶体管的n-MBC晶体管,反之亦然。在一些实施例中,顶部晶体管的源极部件和漏极部件与底部晶体管的源极部件和漏极部件基本竖直对准。这种竖直对准使得能够通过导电部件将底部器件的源极/漏极部件耦合到顶部器件的源极/漏极部件。在一些实施例中,导电部件可以竖直延伸到源极部件和漏极部件中以进行耦合。背侧源极接触件和背侧电源轨也可以与本公开的CFET集成。
现在将参考附图更详细地描述本公开的各个方面。在这方面,图1是示出根据本公开的实施例的由工件形成半导体器件的方法100的流程图。方法100仅是示例,并且不旨在将本公开限制为在方法100中明确示出的内容。可在方法100之前、期间和之后提供附加步骤,并且对于方法的附加实施例,可将描述的一些步骤替换、消除或转移。为了简单起见,本文没有详细描述所有步骤。下面结合图2-图39描述方法100,其是根据方法100的实施例的工件200在制造的不同阶段的局部截面图。为避免疑问,在所有附图中,X方向垂直于Y方向,Z方向垂直于X方向和Y方向。应当注意,因为可以将工件200制造成半导体器件,所以根据上下文需要,可以将工件200称为半导体器件200。在整个本公开中,本公开中相似的附图标记表示相似的部件。
参考图1和图2,方法100包括框102,其中提供工件200。工件200可以包括第一衬底202。在一个实施例中,第一衬底202可以是硅(Si)衬底。在一些其他实施例中,第一衬底202可以包括其他半导体,诸如锗(Ge)、硅锗(SiGe)或III-V族半导体材料。示例性III-V族半导体材料可以包括砷化镓(GaAs)、磷化铟(InP)、磷化镓(GaP)、氮化镓(GaN)、磷砷化镓(GaAsP)、砷化铝铟(AlInAs)、砷化铝镓(AlGaAs)、磷化铟镓镓(GaInP)和砷化铟镓(InGaAs)。
如图2所示,工件200还包括设置在衬底202上的堆叠件204。堆叠件204包括由多个牺牲层206交错的多个沟道层208。沟道层208和牺牲层206可以具有不同的半导体组成。在一个实施例中,沟道层208由硅(Si)形成,而牺牲层206由硅锗(SiGe)形成。在这些实施方式中,牺牲层206中的附加锗含量允许牺牲层206的选择性去除或开槽而不会对沟道层208造成实质性损害。在一些替代实施例中,沟道层208可以包括锗(Ge)、硅锗(SiGe)或二维(2D)材料,诸如二硫化钼(MoS2)、二硒化钨(WSe2)或二碲化铪(HfTe2)。在沟道层208和牺牲层206由硅锗(SiGe)形成的实施例中,沟道层208具有比牺牲层206小的锗含量,以允许牺牲层206的选择性开槽/去除。牺牲层206和沟道层208是外延层,并且可以使用外延工艺沉积。合适的外延工艺包括气相外延(VPE)、超高真空化学气相沉积(UHV-CVD)、分子束外延(MBE)和/或其他合适的工艺。如图2所示,牺牲层206和沟道层208一个接一个地交替沉积,以形成堆叠件204。应当注意,如图2所示,三(3)层牺牲层206和三(3)层沟道层208交替地竖直布置,这仅是出于说明的目的,并不旨在限制权利要求中具体记载的内容。可以理解,可以在堆叠件204中形成任何数量的牺牲层206和沟道层208。层的数量取决于器件200的沟道构件的期望数量。在一些实施例中,沟道层208的数量在2和10之间。
参考图1和图3,方法100包括框104,其中由堆叠件204形成鳍状结构210。在一些实施例中,将堆叠件204和第一衬底202的一部分图案化以形成鳍状结构210。为了图案化的目的,可以在堆叠件204上方沉积硬掩模层。硬掩模层可以是单层或多层。在一个示例中,硬掩模层包括氧化硅层和氧化硅层上方的氮化硅层。如图3所示,鳍状结构210从第一衬底202沿Z方向竖直延伸,并沿Y方向纵向延伸。鳍状结构210可以包括由第一衬底202形成的基部210B和由堆叠件204形成的堆叠部210SP。可以使用包括双图案化或多图案化工艺的合适的工艺来图案化鳍状结构210。通常,双图案化或多图案化工艺将光刻和自对准工艺组合,从而允许创建具有例如间距小于使用单一、直接光刻工艺可获得的间距的图案。例如,在一个实施例中,在衬底上方形成材料层,并使用光刻工艺对其进行图案化。使用自对准工艺在图案化的材料层旁边形成间隔件。然后去除材料层,然后可以通过蚀刻堆叠件204和第一衬底202来使用剩余的间隔件或心轴来图案化鳍状结构210。蚀刻工艺可以包括干蚀刻、湿蚀刻、反应离子蚀刻(RIE)和/或其他适合的工艺。
参考图1、图4和图5,方法100包括框106,其中在鳍状结构210的沟道区域上方形成第一伪栅极堆叠件214。在图4所示的一些实施例中,在形成鳍状结构210之后,形成隔离部件212以围绕基部210B。隔离部件212也可以称为浅沟槽隔离(STI)部件212。在示例性工艺中,使用CVD、亚大气压CVD(SACVD)、可流动CVD、原子层沉积(ALD)、物理气相沉积(PVD)、旋涂和/或其他合适的工艺将用于隔离部件212的介电材料沉积在鳍状结构210上方。然后,将沉积的介电材料平坦化并开槽,直到鳍状结构210的堆叠部210SP至少上升到隔离部件212上方。也就是说,在隔离部件212开槽之后,鳍状结构210的基部210B被隔离部件212围绕。用于隔离部件212的介电材料可以包括氧化硅、氮氧化硅、掺氟硅酸盐玻璃(FSG)、低k电介质、其组合和/或其他合适的材料。
在采用栅极替换工艺(或后栅极工艺)的一些实施例中,第一伪栅极堆叠件214形成在鳍状结构210上方,用作功能栅极结构的占位件。其他工艺和配置也是可能的。为了形成第一伪栅极堆叠件214,在工件200上方沉积伪介电层216、伪栅电极层218和栅极顶部硬掩模层(未示出)。这些层的沉积可以包括使用低压CVD(LPCVD)、CVD、等离子体增强CVD(PECVD)、PVD、ALD、热氧化、电子束蒸发或其他合适的沉积技术或其组合。伪介电层216可以包括氧化硅,伪栅电极层218可以包括多晶硅,并且栅极顶部硬掩模层可以是包括氧化硅和氮化硅的多层。使用光刻和蚀刻工艺,可以对栅极顶部硬掩模层进行图案化。光刻工艺可以包括光刻胶涂覆(例如,旋涂)、软烘烤、掩模对准、曝光、曝光后烘烤、光刻胶显影、冲洗、干燥(例如,旋干和/或硬烘烤)、其他合适的光刻技术和/或其组合。蚀刻工艺可以包括干蚀刻(例如,RIE蚀刻)、湿蚀刻和/或其他的蚀刻方法。之后,使用图案化的栅极顶部硬掩模作为蚀刻掩模,然后蚀刻伪介电层216和伪栅电极层218,以形成第一伪栅极堆叠件214。如图4所示,第一伪栅极堆叠件214形成在隔离部件212和鳍状结构210的一部分上方。第一伪栅极堆叠件214沿X方向纵向延伸以包围在鳍状结构210上方。参考图5,,第一伪栅极堆叠件214下面的鳍状结构210的部分是第一沟道区域210C。第一沟道区域210C和第一伪栅极堆叠件214还限定未与第一伪栅极堆叠件214竖直地重叠的第一源极区域210S和第一漏极区域210D。第一沟道区域210C沿Y方向设置或夹在第一源极区域210S和第一漏极区域210D之间。
如图5中代表性地示出的,框106处的操作可以包括在第一伪栅极堆叠件214的侧壁上方形成第一栅极间隔件层220。在一些实施例中,第一栅极间隔件层220的形成包括在工件200上方共形沉积一个或多个介电层。在示例性工艺中,使用CVD、SACVD或ALD沉积一个或多个介电层。一个或多个介电层可以包括氧化硅、氮化硅、碳化硅、氮氧化硅、碳氮化硅、碳氧化硅、碳氮氧化硅和/或它们的组合。
参考图1和图5,方法100包括框108,其中鳍状结构210的第一源极区域210S和第一漏极区域210D被开槽以形成第一源极凹槽222S和第一漏极凹槽222D。在示例性工艺中,在沉积第一栅极间隔件层220之后,以选择性地使鳍状结构210的第一源极区域210S和第一漏极区域210D开槽的蚀刻工艺来蚀刻工件200。第一源极区域210S和第一漏极区域210D的选择性开槽获得第一源极凹槽222S和第一漏极凹槽222D。框108处的蚀刻工艺可以是干蚀刻工艺或合适的蚀刻工艺。示例性干蚀刻工艺可以实施含氧气体、氢气、含氟气体(例如,CF4、SF6、CH2F2、CHF3和/或C2F6)、含氯气体(例如,Cl2、CHCl3、CCl4和/或BCl3)、含溴气体(例如,HBr和/或CHBR3)、含碘气体、其他合适的气体和/或等离子体和/或它们的组合。如图5所示,第一沟道区域210C中的牺牲层206和沟道层208的侧壁在第一源极凹槽222S和第一漏极凹槽222D中暴露。
参考图1、图6和图7,方法100包括框110,其中形成内部间隔件部件226。首先参考图6。在框110处,选择性地且部分地开槽暴露在第一源极凹槽222S和第一漏极凹槽222D中的牺牲层206,以形成内部间隔件凹槽224,而暴露的沟道层208基本上未被蚀刻。在沟道层208主要由硅(Si)组成并且牺牲层206主要由硅锗(SiGe)组成的实施例中,牺牲层206的选择性和部分的开槽可以包括SiGe氧化工艺以及之后的SiGe氧化物去除。在该实施例中,SiGe氧化工艺可以包括使用臭氧(O3)。在一些其他实施例中,选择性开槽可以是选择性各向同性蚀刻工艺(例如,选择性干蚀刻工艺或选择性湿蚀刻工艺),并且牺牲层206被开槽的程度由蚀刻工艺的持续时间控制。选择性干蚀刻工艺可以包括使用一种或多种基于氟的蚀刻剂,诸如氟气或氢氟烃。选择性湿蚀刻工艺可以包括APM蚀刻(例如,氢氧化氨-过氧化氢-水的混合物)。
现在参考图7。在形成内部间隔件凹槽224之后,将内部间隔件材料层沉积在工件200上方,包括在内部间隔件凹槽224中。内部间隔件材料层可以包括氧化硅、氮化硅、碳氧化硅、碳氮氧化硅、碳氮化硅、金属氮化物或合适的介电材料。然后回蚀刻沉积的内部间隔件材料层,以去除第一栅极间隔件层220和沟道层208的侧壁上方的多余的内部间隔件材料层,从而形成如图7所示的内部间隔件部件226。在一些实施例中,框110处的回蚀刻工艺可以是干蚀刻工艺,其包括使用含氧气体、氢气、氮气、含氟气体(例如,CF4、SF6、CH2F2、CHF3和/或C2F6)、含氯气体(例如,Cl2、CHCl3、CCl4和/或BCl3)、含溴气体(例如,HBr和/或CHBr3)、含碘气体(例如,CF3I)、其他合适的气体和/或等离子体和/或它们的组合。
参考图1和图8,方法100包括框112,其中在第一源极凹槽222S和第一漏极凹槽222D中形成第一源极部件228S和第一漏极部件228D。在一些实施例中,可以使用诸如VPE、UHV-CVD、MBE和/或其他合适的工艺的外延工艺来形成第一源极部件228S和第一漏极部件228D。外延生长工艺可以使用气体和/或液体前体,其与衬底202以及沟道层208的成分相互作用。因此,第一源极部件228S和第一漏极部件228D耦合至沟道层。在一些实施例中,第一源极部件228S和第一漏极部件228D可以是n型源极/漏极部件。示例性n型源极/漏极部件可以包括Si、GaAs、GaAsP、SiP或其他合适的材料,并且可以在外延工艺期间通过引入n型掺杂剂(诸如,磷(P)、砷(As))进行原位掺杂或使用注入工艺(即,结注入工艺)进行异位掺杂。在一个实施例中,第一源极部件228S和第一漏极部件228D包括掺杂磷的硅(Si:P)。
参考图1、图9、图10和图11,方法100包括框114,其中用第一栅极结构240代替第一伪栅极堆叠件214。框114处的操作包括沉积第一接触蚀刻停止层(CESL)230(图9所示)、沉积第一层间介电(ILD)层232(图9所示)、去除第一伪栅极堆叠件214(图10所示)、选择性去除牺牲层206以释放沟道层208作为沟道构件2080(图10所示)、形成第一栅极结构240(图10所示)以及平坦化工件200以去除多余的材料。第一CESL 230可以包括氮化硅、氮氧化硅和/或本领域中已知的其他材料,并且可以通过ALD、等离子体增强化学气相沉积(PECVD)工艺和/或其他合适的沉积或氧化工艺来形成。如图9所示,第一CESL 230可以沉积在第一源极部件228S和第一漏极部件228D的顶面上。此后,在第一CESL 230上方沉积第一ILD层232。第一ILD层232可以包括诸如原硅酸四乙酯(TEOS)氧化物、未掺杂的硅酸盐玻璃或掺杂的氧化硅(诸如硼磷硅硅酸盐玻璃(BPSG)、熔融石英玻璃(FSG)、磷硅酸盐玻璃(PSG)、硼掺杂的硅玻璃(BSG))和/或其他合适的介电材料的材料。可以通过PECVD工艺或其他合适的沉积技术来沉积第一ILD层232。在一些实施例中,在形成第一ILD层232之后,可以对工件200进行退火以改善第一ILD层232的完整性。为了去除多余的材料并暴露第一伪栅极堆叠件214的顶面,可以执行平坦化工艺,诸如化学机械抛光(CMP)工艺。
在一些实施方式中,每个沟道构件2080具有的宽度(沿X方向)大于其厚度(沿Z方向),并且可以被称为纳米片。在一些实施例中,沟道构件2080的宽度可以在约8nm和约60nm之间,并且沟道构件2080的厚度可以在约3nm和约9nm之间。关于每个沟道构件2080,主表面是顶面和底面。当第一衬底202由硅形成并且在(100)表面上具有顶面时,沟道构件2080的主表面也在(100)表面上,这提供了优于其他表面的电子迁移率。
参考图10。随着第一伪栅极堆叠件214的暴露,框114进行到第一伪栅极堆叠件214的去除。第一伪栅极堆叠件214的去除可以包括一个或多个蚀刻工艺,其对第一伪栅极堆叠件214中的材料具有选择性。例如,可以使用选择性湿蚀刻、选择性干蚀刻或其组合来执行第一伪栅极堆叠件214的去除。在去除第一伪栅极堆叠件214之后,暴露第一沟道区域210C中的沟道层208和牺牲层206的侧壁。此后,选择性地去除第一沟道区域210C中的牺牲层206以释放作为沟道构件2080的沟道层208。这里,因为沟道构件2080的尺寸是纳米级的,所以沟道构件也可以被称为纳米结构。牺牲层206的选择性去除可以通过选择性干蚀刻、选择性湿蚀刻或其他选择性蚀刻工艺来实现。在一些实施例中,选择性湿蚀刻包括APM蚀刻(例如,氢氧化铵-过氧化氢-水的混合物)。在一些实施例中,选择性去除包括SiGe氧化以及之后的硅锗氧化物去除。例如,可以通过臭氧清洁来提供氧化,然后通过诸如NH4OH的蚀刻剂去除氧化硅锗。
然后参考图11。在释放沟道构件2080的情况下,沉积第一栅极结构240以包围在第一沟道区域210C中的每个沟道构件2080周围。第一栅结构240包括第一栅介电层236和第一栅电极层238。第一栅极介电层236可以包括界面层和高k介电层。在此,高k介电层是指由介电常数大于二氧化硅的介电常数(约3.9)的介电材料形成的层。在一些实施例中,界面层包括氧化硅并且可以在预清洁工艺中形成。示例性预清洁工艺可以包括使用RCA SC-1(氨、过氧化氢和水)和/或RCA SC-2(盐酸、过氧化氢和水)。然后使用ALD、CVD和/或其他合适的方法将高k介电层沉积在界面层上方。高k介电层可以包括氧化铪。替代地,高k介电层可以包括其他高k电介质,诸如氧化钛(TiO2)、氧化锆铪(HfZrO)、氧化钽(Ta2O5)、氧化硅铪(HfSiO4)、氧化锆(ZrO2)、氧化锆硅(ZrSiO2)、氧化镧(La2O3)、氧化铝(Al2O3)、氧化锆(ZrO)、氧化钇(Y2O3)、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、氧化镧铪(HfLaO)、氧化镧硅(LaSiO)、氧化铝硅(AlSiO)、氧化钽铪(HfTaO)、氧化钛铪(HfTiO)、(Ba,Sr)TiO3(BST)、氮化硅(SiN)、氮氧化硅(SiON)、它们的组合或其他合适的材料。
仍然参考图11,然后使用ALD、PVD、CVD、电子束蒸发或其他合适的方法在第一栅极介电层236上方沉积第一栅电极层238。第一栅电极层238可以包括单层或替代的多层结构,诸如具有增强器件性能的所选功函数的金属层(功函数金属层)、衬层、湿润层、粘合层、金属合金或金属硅化物的各种组合。举例来说,第一栅电极层238可以包括氮化钛(TiN)、钛铝(TiAl)、氮化钛铝(TiAlN)、氮化钽(TaN)、钽铝(TaAl)、氮化钽铝(TaAlN)、碳化钽铝(TaAlC)、碳氮化钽(TaCN)、铝(Al)、钨(W)、镍(Ni)、钛(Ti)、钌(Ru)、钴(Co)、铂(Pt)、碳化钽(TaC)、氮化钽硅(TaSiN)、铜(Cu)、其他难熔金属或其他合适的金属材料或其组合。
参考图1、图12和图13,方法100包括框116,其中形成下部漏极接触件244。在图12所示的示例性工艺中,光刻工艺用于形成暴露第一漏极部件228D的接触件开口。为了减小接触电阻,可以通过在第一漏极部件228D上方沉积金属层并执行退火工艺以在金属层和第一漏极部件228D之间引起硅化来在第一漏极部件228D上形成硅化物层242。合适的金属层可以包括钛(Ti)、钽(Ta)、镍(Ni)、钴(Co)或钨(W)。硅化物层242可以包括硅化钛(TiSi)、氮化钛硅(TiSiN)、硅化钽(TaSi)、硅化钨(WSi)、硅化钴(CoSi)或硅化镍(NiSi)。在形成硅化物层242之后,可以将金属填充层沉积到接触件开口中。金属填充层可以包括氮化钛(TiN)、钛(Ti)、钌(Ru)、镍(Ni)、钴(Co)、铜(Cu)、钼(Mo)、钨(W)、钽(Ta)或氮化钽(TaN)。可以接着进行平坦化工艺以去除多余的材料,从而形成下部漏极接触件244。由于平坦化工艺,所以下部漏极接触件244、第一CESL 230和第一ILD层232的顶面共面。
在图13所示的一些实施例中,下部漏极接触件244沿X方向突出在第一漏极部件228D上方。在这些实施例中,下部漏极接触件244包括第一突出部2440,其在第一漏极部件228D上突出约2nm和约20nm。也就是说,第一突出部2440没有直接或通过硅化物层242间接设置在第一漏极部件228D上。
框116处的操作是可选的,并且可以完全省略。如以下将描述的,在导电部件延伸到第一漏极部件228D中以将第一漏极部件228D耦合到上方的另一漏极部件的一些实施例中,下部漏极接触件244可以是不需要的并且可以被省略。
参考图1、图14和图15,方法100包括框118,其中外延层250接合到工件200上方。框118处的操作包括在第一栅极结构240上方沉积第一钝化层246(图14所示)、在第二衬底251上设置外延层250(图15所示)、在外延层250上方沉积第二钝化层248(图15所示)以及将第二钝化层248接合到第一钝化层246上(图15所示)。参考图14,在框118处,第一钝化层246毯式沉积在工件200上方。在一个实施例中,第一钝化层246包括氧化硅。在一些替代实施例中,第一钝化层246可以包括氮化硅、碳氮化硅、碳氮氧化硅、氧化铝或氧化铪。如图14所示,第一钝化层246可以设置在第一CESL 230、第一ILD层232、第一栅极结构240和第一栅极间隔件层220上。参考图15,第二衬底251可以类似于第一衬底202,并且为了简洁起见省略其详细描述。在一个实施例中,第一衬底202和第二衬底251都是具有在(100)晶体表面上的顶面的硅衬底。使用气相外延(VPE)、超高真空化学气相沉积(UHV-CVD)、分子束外延(MBE)和/或其他合适的工艺将外延层250外延沉积在第二衬底251上。外延层250由适合用作p型器件的沟道的半导体材料形成。在一个实施例中,外延层250可以包括锗含量在约15%和约60%之间的硅锗(SiGe)。在一些替代实施例中,外延层250可以包括锗(Ge)、硅锗(SiGe)或二维(2D)材料,诸如二硫化钼(MoS2)、二硒化钨(WSe2)或二碲化铪(HfTe2)。然后,将第二钝化层248沉积在外延层250上。在一个实施例中,第二钝化层248包括氧化硅。在一些替代实施例中,第二钝化层248可以包括氮化硅、碳氮化硅、碳氮氧化硅、氧化铝或氧化铪。
通过第一钝化层246和第二钝化层248之间的直接接合或熔融接合将外延层250接合至工件200。在示例性直接接合工艺中,第一钝化层246和第二钝化层248都使用RCA SC-1(氨、过氧化氢和水)和/或RCA SC-2(盐酸、过氧化氢和水)进行清洁。然后将清洁的第一钝化层246和第二钝化层248在室温下配接并压合在一起。可以通过退火工艺来加强直接接合。尽管在图15中未明确示出,但是在将第一钝化层246和第二钝化层248接合在一起之后,去除第二衬底251以在顶面上暴露外延层250。此时,外延层250和第二钝化层248成为工件200的一部分。
参考图1和图16,方法100包括框120,其中从外延层250形成鳍元件252。在去除第二衬底251的情况下,将外延层250图案化以形成一个或多个鳍元件252。在半导体器件200包括双鳍晶体管的一些实施例中,两个鳍元件252直接形成在沟道构件2080的竖直堆叠件上方,如图16所示。其他配置也是可能的。为了图案化的目的,可以在外延层250上方沉积硬掩模层。硬掩模层可以是单层或多层。在一个示例中,硬掩模层包括氧化硅层和氧化硅层上方的氮化硅层。如图16所示,鳍元件252从第二钝化层248沿Z方向竖直延伸,并沿Y方向纵向延伸。可以使用包括双图案化或多图案化工艺的合适的工艺来图案化鳍元件252。通常,双图案化或多图案化工艺将光刻和自对准工艺组合,从而允许创建具有例如间距小于使用单一、直接光刻工艺可获得的间距的图案。例如,在一个实施例中,在衬底上方形成材料层,并使用光刻工艺对其进行图案化。使用自对准工艺在图案化的材料层旁边形成间隔件。然后去除材料层,然后可以通过蚀刻外延层250来使用剩余的间隔件或心轴来图案化鳍元件252。蚀刻工艺可以包括干蚀刻、湿蚀刻、反应离子蚀刻(RIE)和/或其他适合的工艺。
在一些实施方式中,鳍元件252具有的高度(沿Z方向)大于其宽度(沿Y方向)。在一些实施例中,鳍元件252的高度可以在约10nm和约70nm之间,并且鳍元件252的宽度可以在约3nm和约12nm之间。当半导体器件200包括多个鳍元件252时,鳍元件252包括在约10nm和约50nm之间的鳍间距。关于每个鳍元件252,主表面是侧壁。当第二衬底251由硅形成并且在(100)表面上具有顶面时,鳍元件的主表面在(110)表面上,这提供了优于其他表面的空穴迁移率。
参考图1、图16和图17,方法100包括框122,其中在鳍元件252的沟道区域上方沉积第二伪栅极堆叠件258。在采用栅极替换工艺(或后栅极工艺)的一些实施例中,第二伪栅极堆叠件258形成在鳍元件252上方,用作功能栅极结构的占位件。其他工艺和配置也是可能的。为了形成第二伪栅极堆叠件258,在工件200上方(包括在鳍元件252上方)沉积伪介电层254、伪栅电极层256和栅极顶部硬掩模层(未示出)。这些层的沉积可以包括使用低压CVD(LPCVD)、CVD、等离子体增强CVD(PECVD)、PVD、ALD、热氧化、电子束蒸发或其他合适的沉积技术或其组合。伪介电层254可以包括氧化硅,伪栅电极层256可以包括多晶硅,并且栅极顶部硬掩模层可以是包括氧化硅和氮化硅的多层。使用光刻和蚀刻工艺,可以对栅极顶部硬掩模层进行图案化。光刻工艺可以包括光刻胶涂覆(例如,旋涂)、软烘烤、掩模对准、曝光、曝光后烘烤、光刻胶显影、冲洗、干燥(例如,旋干和/或硬烘烤)、其他合适的光刻技术和/或其组合。蚀刻工艺可以包括干蚀刻(例如,RIE蚀刻)、湿蚀刻和/或其他的蚀刻方法。之后,使用图案化的栅极顶部硬掩模作为蚀刻掩模,然后蚀刻伪介电层254和伪栅电极层256,以形成第二伪栅极堆叠件258。如图16所示,第二伪栅极堆叠件258包围在鳍元件252上方并且设置在第二钝化层248上。参考图17,第二伪栅极堆叠件258下面的鳍元件252的部分是第二沟道区域252C。第二沟道区域252C和第二伪栅极堆叠件258还限定未与第二伪栅极堆叠件258竖直地重叠的第二源极区域252S和第二漏极区域252D。第二沟道区域252C沿Y方向设置或夹在第二源极区域252S和第二漏极区域252D之间。
如图17中代表性地示出的,框122处的操作可以包括在第二伪栅极堆叠件258的侧壁上方形成第二栅极间隔件层260。在一些实施例中,第二栅极间隔件层260的形成包括在工件200上方共形沉积一个或多个介电层。在示例性工艺中,使用CVD、SACVD或ALD沉积一个或多个介电层。一个或多个介电层可以包括氧化硅、氮化硅、碳化硅、氮氧化硅、碳氮化硅、碳氧化硅、碳氮氧化硅和/或它们的组合。
在图17所示的一些实施例中,第二沟道区域252C直接位于第一沟道区域210C上方,第二源极区域252S直接位于第一源极区域210S上方,第二漏极区域252D直接位于第一漏极区域210D上方。换句话说,沿着Z方向,第二沟道区域252C可以与第一沟道区域210C基本重叠,第二源极区域252S可以与第一源极区域210S基本重叠,并且第二漏极区域252D可以与第一漏极区域210D基本重叠。
参考图1和图17,方法100包括框124,其中鳍元件252的源极/漏极区域被开槽以形成第二源极凹槽262S和第二漏极凹槽262D。在示例性工艺中,在沉积第二栅极间隔件层260之后,以选择性地使鳍元件252的第二源极区域252S和第二漏极区域252D开槽的蚀刻工艺来蚀刻工件200。第二源极区域252S和第二漏极区域252D的选择性开槽获得第二源极凹槽262S和第二漏极凹槽262D。框124处的蚀刻工艺可以是干蚀刻工艺或合适的蚀刻工艺。示例性干蚀刻工艺可以实施含氧气体、氢气、含氟气体(例如,CF4、SF6、CH2F2、CHF3和/或C2F6)、含氯气体(例如,Cl2、CHCl3、CCl4和/或BCl3)、含溴气体(例如,HBr和/或CHBR3)、含碘气体、其他合适的气体和/或等离子体和/或它们的组合。如图17所示,第二源极区域252S和第二漏极区域252D中的第二钝化层248暴露在第二源极凹槽262S和第二漏极凹槽262D中。
参考图1和图18,方法100包括框126,其中形成第二源极部件264S和第二漏极部件264D。在一些实施例中,可以使用诸如VPE、UHV-CVD、MBE和/或其他合适的工艺的外延工艺来形成第二源极部件264S和第二漏极部件264D。外延生长工艺可以使用与鳍元件252的组分相互作用的气体和/或液体前体。因此,第二源极部件264S和第二漏极部件264D耦合至鳍元件252。在一些实施例中,第二源极部件264S和第二漏极部件264D可以是p型源极/漏极部件。示例性p型源极/漏极部件可以包括Si、Ge、AlGaAs、SiGe或其他合适的材料,并且可以在外延工艺期间通过引入p型掺杂剂(诸如,硼(B))进行原位掺杂或使用注入工艺(即,结注入工艺)进行异位掺杂。在一个实施例中,第二源极部件264S和第二漏极部件264D包括掺杂硼的硅锗(SiGe:B)。
参考图1、图19、图20、图21和图22,方法100包括框128,其中用第二栅极结构274代替第二伪栅极堆叠件258。框128处的操作包括沉积第二接触蚀刻停止层(CESL)266(图19所示)、沉积第二层间介电(ILD)层268(图19所示)、去除第二伪栅极堆叠件258(图20所示)、沉积第二栅极介电层270(图20所示)、暴露第一栅极结构240(图21所示)、沉积第二栅电极层272(图22所示)以及平坦化工件200以去除多余的材料(图22所示)。第二CESL 266可以包括氮化硅、氮氧化硅和/或本领域中已知的其他材料,并且可以通过ALD、等离子体增强化学气相沉积(PECVD)工艺和/或其他合适的沉积或氧化工艺来形成。如图19所示,第二CESL 266可以沉积在第二源极部件264S和第二漏极部件264D的顶面上。此后,在第二CESL 266上方沉积第二ILD层268。与第一ILD层232类似,第二ILD层268可以包括诸如原硅酸四乙酯(TEOS)氧化物、未掺杂的硅酸盐玻璃或掺杂的氧化硅(诸如硼磷硅硅酸盐玻璃(BPSG)、熔融石英玻璃(FSG)、磷硅酸盐玻璃(PSG)、硼掺杂的硅玻璃(BSG))和/或其他合适的介电材料的材料。可以通过PECVD工艺或其他合适的沉积技术来沉积第二ILD层268。在一些实施例中,在形成第二ILD层268之后,可以对工件200进行退火以改善第二ILD层268的完整性。为了去除多余的材料并暴露第二伪栅极堆叠件258的顶面,可以执行平坦化工艺,诸如化学机械抛光(CMP)工艺。
参考图20。随着第二伪栅极堆叠件258的暴露,框128进行到第二伪栅极堆叠件258的去除。第二伪栅极堆叠件258的去除可以包括一个或多个蚀刻工艺,其对第二伪栅极堆叠件258中的材料具有选择性。例如,可以使用选择性湿蚀刻、选择性干蚀刻或其组合来执行第二伪栅极堆叠件258的去除。在去除第二伪栅极堆叠件258之后,第二栅极介电层270沉积在鳍元件252的第二沟道区域252C上方。第二栅极介电层270可以包括界面层和高k介电层。在一些实施例中,界面层包括氧化硅并且可以在预清洁工艺中形成。示例性预清洁工艺可以包括使用RCA SC-1(氨、过氧化氢和水)和/或RCA SC-2(盐酸、过氧化氢和水)。然后使用ALD、CVD和/或其他合适的方法将高k介电层沉积在界面层上方。高k介电层可以包括氧化铪。替代地,高k介电层可以包括其他高k电介质,诸如氧化钛(TiO2)、氧化锆铪(HfZrO)、氧化钽(Ta2O5)、氧化硅铪(HfSiO4)、氧化锆(ZrO2)、氧化锆硅(ZrSiO2)、氧化镧(La2O3)、氧化铝(Al2O3)、氧化锆(ZrO)、氧化钇(Y2O3)、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、氧化镧铪(HfLaO)、氧化镧硅(LaSiO)、氧化铝硅(AlSiO)、氧化钽铪(HfTaO)、氧化钛铪(HfTiO)、(Ba,Sr)TiO3(BST)、氮化硅(SiN)、氮氧化硅(SiON)、它们的组合或其他合适的材料。
参考图21,在沉积第二栅极介电层270之后,对工件200进行各向异性蚀刻工艺以去除不与鳍元件252重叠的第二钝化层248和第一钝化层246,直到第一栅极结构240暴露在鳍元件252之间。如图21所示,鳍元件252下面的第二钝化层248和第一钝化层246的部分可以基本未被蚀刻并保留在适当的位置。第二栅极介电层270的一部分设置在剩余的第二钝化层248上。此后,如图22所示,使用ALD、PVD、CVD、电子束蒸发或其他合适的方法将第二栅电极层272沉积在第二栅极介电层270、第一栅极结构240和鳍元件252上方。第二栅电极层272可以包括单层或替代的多层结构,诸如具有增强器件性能的所选功函数的金属层(功函数金属层)、衬层、湿润层、粘合层、金属合金或金属硅化物的各种组合。举例来说,第二栅电极层272可以包括氮化钛(TiN)、钛铝(TiAl)、氮化钛铝(TiAlN)、氮化钽(TaN)、钽铝(TaAl)、氮化钽铝(TaAlN)、碳化钽铝(TaAlC)、碳氮化钽(TaCN)、铝(Al)、钨(W)、镍(Ni)、钛(Ti)、钌(Ru)、钴(Co)、铂(Pt)、碳化钽(TaC)、氮化钽硅(TaSiN)、铜(Cu)、其他难熔金属或其他合适的金属材料或其组合。如图22所示,第二栅极介电层270和第二栅电极层272共同构成第二栅极结构274。因为第二栅电极层272与第一栅电极层238直接接触,所以框128处的操作将第二栅极结构274电耦合至第一栅极结构240。
参考图1、图23-图25、图32、图33、图38和图39,方法100包括框130,其中形成上部源极接触件280和上部漏极接触件282。在图23所示的示例性工艺中,光刻工艺用于形成暴露第二源极部件264S和第二漏极部件264D的接触件开口。为了减小接触电阻,可以通过在第二源极部件264S和第二漏极部件264D上方沉积金属层并执行退火工艺以在金属层与第二源极部件264S和第二漏极部件264D之间引起硅化来在第二源极部件264S和第二漏极部件264D上形成硅化物层281。合适的金属层可以包括钛(Ti)、钽(Ta)、镍(Ni)、钴(Co)或钨(W)。硅化物层281可以包括硅化钛(TiSi)、氮化钛硅(TiSiN)、硅化钽(TaSi)、硅化钨(WSi)、硅化钴(CoSi)或硅化镍(NiSi)。在形成硅化物层281之后,可以将金属填充层沉积到接触件开口中。金属填充层可以包括氮化钛(TiN)、钛(Ti)、钌(Ru)、镍(Ni)、钴(Co)、铜(Cu)、钼(Mo)、钨(W)、钽(Ta)或氮化钽(TaN)。可以接着进行平坦化工艺以去除多余的材料,从而在第二源极部件264S上方形成上部源极接触件280并且在第二漏极部件264D上方形成上部漏极接触件282。由于平坦化工艺,所以上部源极接触件280、上部漏极接触件282、第二CESL266和第二ILD层268的顶面共面。
在图24所示的一些实施例中,上部源极接触件280设置在第二源极部件264S上方,并且不突出于第二源极部件264S之上。相反,如图25所示,上部漏极接触件282沿X方向突出在第一漏极部件228D上方。上部漏极接触件282包括第二突出部2820,其在第二漏极部件264D上突出约2nm和约20nm。在一些实施例中,第二突出部2820直接设置在第一突出部上方,并且该配置允许形成第一导电部件284以耦合下部漏极接触件244和上部漏极接触件282。在一些实施方式中,在形成第二漏极部件264D上方的接触件开口之后,形成穿过第二ILD层268、第二钝化层248和第一钝化层246的通孔,以暴露下部漏极接触件244。在将金属填充层沉积在接触件开口中之前,可以以自下而上的方式沉积第一导电部件284。示例性的自下而上沉积可以包括使用可以优先沉积在金属表面上的金属有机前体。如图25所示,第一导电部件284可以邻近第二漏极部件264D的侧壁延伸。第一导电部件284可以与第二漏极部件264D接触,但是不竖直地穿透第二漏极部件264D。
在图32和图33所示的一些替代实施例中,替代的下部漏极接触件244'不突出在第一漏极部件228D上方,替代的上部漏极接触件282'不突出在第二漏极部件264D上方。用于替代的上部漏极接触件282'的接触件开口还包括第一通孔接触件开口302,其延伸穿过第二漏极部件264D、第二钝化层248和第一钝化层246,以暴露替代的下部漏极接触件244'。在这些替代实施例中,当金属填充层沉积到接触件开口和第一通孔接触件开口302中时,第二导电部件306与上部漏极接触件280一起形成。在一些实施例中,可以将硅化物层304设置在上部漏极接触件280和第二漏极部件264D之间以及第二导电部件306和第二漏极部件264D之间。硅化物层304的组成和形成可以类似于硅化物层242的组成和形成。在第二导电部件306和第二钝化层248之间或者在第二导电部件306和第一钝化层246之间不形成硅化物层304。第二导电部件306竖直延伸穿过第二漏极部件264D、第二钝化层248和第一钝化层246。
在图32和图33所示的一些替代实施例中,替代的下部漏极接触件244'不突出在第一漏极部件228D上方,替代的上部漏极接触件282'不突出在第二漏极部件264D上方。用于替代的上部漏极接触件282'的接触件开口还包括第一通孔接触件开口302,其延伸穿过第二漏极部件264D、第二钝化层248和第一钝化层246,以暴露替代的下部漏极接触件244'。在这些替代实施例中,当金属填充层沉积到接触件开口和第一通孔接触件开口302中时,第二导电部件306与替代的上部漏极接触件282'一起形成。在一些实施例中,可以将硅化物层304设置在替代的上部漏极接触件282'和第二漏极部件264D之间以及第二导电部件306和第二漏极部件264D之间。硅化物层304的组成和形成可以类似于硅化物层242的组成和形成。在第二导电部件306和第二钝化层248之间或者在第二导电部件306和第一钝化层246之间不形成硅化物层304。第二导电部件306竖直延伸穿过第二漏极部件264D、第二钝化层248和第一钝化层246。
在图38和图39所示的又一些替代实施例中,省略下部漏极接触件244,并且替代的上部漏极接触件282'不突出在第二漏极部件264D上方。替代地,用于替代的上部漏极接触件282'的接触件开口还包括第二通孔接触件开口332,其延伸穿过第二漏极部件264D、第二钝化层248、第一钝化层246、第一ILD层232、第一CESL 230和第一漏极部件228D。在这些替代实施例中,当金属填充层沉积到接触件开口和第二通孔接触件开口332中时,第三导电部件336与替代的上部漏极接触件282'一起形成。在一些实施例中,可以将硅化物层334设置在替代的上部漏极接触件282'和第二漏极部件264D之间以及第三导电部件336和第二漏极部件264D之间。另外,在第三导电部件336和第一漏极部件228D之间形成硅化物层338。硅化物层334和338的组成和形成可以类似于硅化物层242的组成和形成。第三导电部件336竖直延伸穿过第二漏极部件264D、第二钝化层248、第一钝化层246、第一ILD层232、第一CESL230。第三导电部件336可以接触或可以不接触第一衬底202。
在形成上部源极接触件280和上部漏极接触件282(或替代的上部漏极接触件282')之后,可以在工件200上方形成互连结构275。尽管附图中未明确示出,但是互连结构275可以包括多个互连层,每个互连层包括嵌入介电层中的导线和导电通孔。介电层可以被称为金属间层(IMD),并且可以包括诸如原硅酸四乙酯(TEOS)氧化物、未掺杂的硅酸盐玻璃或掺杂的氧化硅(诸如硼磷硅硅酸盐玻璃(BPSG)、熔融石英玻璃(FSG)、磷硅酸盐玻璃(PSG)、硼掺杂的硅玻璃(BSG))和/或其他合适的介电材料的材料。参考图23、图24和图25,第三钝化层276沉积在互连结构275上,以利于将工件200接合至其他结构。在一个实施例中,第三钝化层276包括氧化硅。在一些替代实施例中,第三钝化层276可以包括氮化硅、碳氮化硅、碳氮氧化硅、氧化铝或氧化铪。
参考图1、图26-图31和图34-图37,方法100包括框132,其中形成背侧源极接触件296以耦合至第一源极部件228S。框134处的操作可以包括在载体衬底288上沉积第四钝化层286(图26所示)、将第四钝化层286接合至第三钝化层276(图26所示)、翻转工件200以使第一衬底202向上(图27所示)、去除第一衬底202的一部分(图28所示)以及在第一源极部件228S上方形成背侧源极接触件296(图28所示)。载体衬底288可以包括硅或碳化硅。在一个实施例中,第四钝化层286包括氧化硅。在一些替代实施例中,第四钝化层286可以包括氮化硅、碳氮化硅、碳氮氧化硅、氧化铝或氧化铪。可以使用CVD或适当的沉积工艺将第四钝化层286沉积在载体衬底288上。通过第三钝化层276和第四钝化层286之间的直接接合而将载体衬底288接合至工件200。上面描述了示例性直接接合工艺,并且在此将不再重复。在将载体衬底288接合至工件200之后,将工件200翻转,使第一衬底朝上,如图27所示。通过研磨工艺和/或化学机械抛光(CMP)工艺对第一衬底202进行研磨和/或平坦化,直到隔离部件212、第一源极部件228S和第一漏极部件228D暴露在顶面上。
参考图28,在暴露的隔离部件212、第一源极部件228S和第一漏极部件228D上方沉积背侧接触蚀刻停止层(BCESL)290。与第一CESL 230和第二CESL 266类似,BCESL 290可以包括氮化硅、氮氧化硅和/或本领域中已知的其他材料,并且可以通过ALD、等离子体增强化学气相沉积(PECVD)工艺和/或其他合适的沉积或氧化工艺来形成。此后,在BCESL290上方沉积背侧介电层292。背侧介电层292可以包括诸如原硅酸四乙酯(TEOS)氧化物、未掺杂的硅酸盐玻璃或掺杂的氧化硅(诸如硼磷硅硅酸盐玻璃(BPSG)、熔融石英玻璃(FSG)、磷硅酸盐玻璃(PSG)、硼掺杂的硅玻璃(BSG))和/或其他合适的介电材料的材料。可以通过PECVD工艺或其他合适的沉积技术来沉积背侧介电层292。
还参考图28。为了形成背侧源极接触件296,形成背侧接触件开口以暴露第一源极部件228S。在背侧接触件开口中形成背侧硅化物层294和背侧源极接触件296。背侧硅化物层294可以包括硅化钛(TiSi)、氮化钛硅(TiSiN)、硅化钽(TaSi)、硅化钨(WSi)、硅化钴(CoSi)或硅化镍(NiSi)。背侧源极接触件296可以包括氮化钛(TiN)、钛(Ti)、钌(Ru)、镍(Ni)、钴(Co)、铜(Cu)、钼(Mo)、钨(W)、钽(Ta)或氮化钽(TaN)。图29和图30示出根据本公开的一些实施例的工件200现在上下颠倒时的第二源极区域252S和第二漏极区域252D的局部截面图。
背侧源极接触件296的替代实施例在图34-图37中示出。在图34和图35所示的第一替代实施例中,可以在形成背侧接触件开口之后形成第一贯通孔开口312,并且在第一贯通孔开口312中沉积第四导电部件314。如图34和图35所示,第一贯通孔开口312和第四导电部件314延伸穿过第一源极部件228S、第一CESL 230、第一ILD层232、第一钝化层246、第二钝化层248、第二源极部件264S和硅化物层281,以耦合至上部源极接触件280。在图35所示的一些实施方式中,可以在第四导电部件314和第一源极部件228S之间形成硅化物层316,并且可以在第四导电部件314和第二源极部件264S之间形成硅化物层318。硅化物层316和318的组成可以类似于硅化物层242,并且为了简洁起见省略其详细描述。类似地,第四导电部件314在材料方面类似于背侧源极接触件296,并且为简洁起见也省略了其详细描述。
在图36和图37所示的第二替代实施例中,可以在形成背侧接触件开口之后形成第二贯通孔开口322,并且在第二贯通孔开口322中沉积第五导电部件324。与图34和图35中所示的第一替代实施例不同,省略了上部源极接触件280。如图36和图37所示,第二贯通孔开口322和第五导电部件324延伸穿过第一源极部件228S、第一CESL 230、第一ILD层232、第一钝化层246和第二钝化层248,以耦合至第二源极部件264S。在图37所示的一些实施方式中,可以在第五导电部件324和第一源极部件228S之间形成硅化物层326,并且可以在第五导电部件324和第二源极部件264S之间形成硅化物层328。硅化物层326和328的组成可以类似于硅化物层242,并且为了简洁起见省略其详细描述。类似地,第五导电部件324在材料方面类似于背侧源极接触件296,并且为简洁起见也省略了其详细描述。
参考图1,方法100包括框134,其中执行进一步处理。这种进一步处理可以包括在背侧源极接触件296上方沉积第三ILD层以及在第三ILD层中形成背侧电源轨。
现在参考图31。在方法100中的操作结束时,半导体器件200包括作为底部晶体管的n型MBC晶体管1000和作为顶部器件的p型FinFET 2000。在图31中,p型FinFET 2000设置在n型MBC晶体管1000上方。n型MBC晶体管1000包括沿Z方竖直堆叠的多个沟道构件2080。沿着Y方向,沟道构件2080在第一源极部件228S和第一漏极部件228D之间延伸。第一栅极结构240包围在每个沟道构件2080周围。p型FinFET 2000包括从第二钝化层248凸起的一个或多个鳍元件252(如图31所示)。沿着Y方向,鳍元件252在第二源极部件264S和第二漏极部件264D之间延伸。第二栅极结构274包围在鳍元件252上方。n型MBC晶体管1000的第一源极部件228S和p型FinFET 2000的第二源极部件264S沿Z方向对准。n型MBC晶体管1000的第一漏极部件228D和p型FinFET 2000的第二漏极部件264D沿Z方向对准。这种竖直对准取向允许形成将第一源极部件228S和第二源极部件264S或第一漏极部件228D和第二漏极部件264D电耦合的导电部件。
在第二衬底251是具有(100)表面的硅衬底的实施例中,图31中的半导体器件200改善了p型FinFET 2000的空穴迁移率。在这些实施例中,第二衬底251上沉积的外延层250遵循第二衬底251的晶体取向。当外延层250被图案化以形成鳍元件252时。鳍元件252的侧壁在(110)表面上,其提供比(100)表面更大的空穴迁移率。因为鳍元件252的侧壁是鳍元件252的主表面,所以鳍元件252具有改善的空穴迁移率,并且p型FinFET2000具有改善的驱动电流。
尽管本公开的大部分描述了图31中所示的半导体器件200的工艺和结构,但是本公开的实施例不限于包括n型MBC上方的p-FinFET的实施例。图40示出半导体器件400中的替代配置。与图31中的半导体器件200不同,半导体器件400包括作为底部晶体管的p型FinFET 2000和作为顶部器件的n型MBC晶体管1000。即,在半导体器件400中,n型MBC晶体管1000设置在p型FinFET 2000上方。由于p型FinFET 2000现在是底部晶体管,所以省略了上部源极接触件280,并且替代的源极接触件245形成为通过硅化物层耦合至第一源极部件228S。由于替代的源极接触件245类似于下部漏极接触件244,所以为简洁起见,省略了替代的源极接触件245的详细描述。类似于图31中的半导体器件200,n型MBC晶体管1000的第一漏极部件228D和p型FinFET 2000的第二漏极部件264D沿Z方向对准。这种竖直对准取向允许形成将第一源极部件228S和第二源极部件264S或第一漏极部件228D和第二漏极部件264D电耦合的导电部件。在半导体器件200和替代的半导体器件400两者中,鳍元件252设置在第二钝化层248上以提供改善的栅极控制。
在一个示例性方面,本公开针对一种半导体器件。半导体器件包括第一晶体管和设置在第一晶体管上方的第二晶体管。第一晶体管包括彼此竖直堆叠的多个沟道构件以及邻接多个沟道构件的第一源极/漏极部件。第二晶体管包括鳍结构和邻接鳍结构的第二源极/漏极部件。半导体器件还包括电连接第一源极/漏极部件和第二源极/漏极部件的导电部件。
在一些实施例中,第一晶体管还包括包围在多个沟道构件中的每一个周围的第一栅极结构。第二晶体管还包括包围在鳍结构上方的第二栅极结构。第一栅极结构与第二栅极结构接触。在一些实施例中,多个沟道构件包括硅(Si),并且鳍结构包括硅锗(SiGe)。在一些实施方式中,多个沟道构件包括硅(Si)、锗(Ge)、硅锗(SiGe)、二硫化钼(MoS2)、二硒化钨(WSe2)或二碲化铪(HfTe2),并且鳍结构包括硅(Si)、锗(Ge)、硅锗(SiGe)、二硫化钼(MoS2)、二硒化钨(WSe2)或二碲化铪(HfTe2)。在一些情况下,导电部件延伸穿过第二源极/漏极部件。在一些实施例中,导电部件延伸穿过第一源极/漏极部件。在一些情况下,第一晶体管还包括设置在第一源极/漏极部件上方的第一源极/漏极接触件,第二晶体管还包括设置在第二源极/漏极部件上方的第二源极/漏极接触件,并且导电部件与第一源极/漏极接触件和第二源极/漏极接触件直接接触。在一些实施例中,第一晶体管还包括设置在第一源极/漏极部件下方的第三源极/漏极接触件,第二晶体管还包括设置在第二源极/漏极部件上方的第四源极/漏极接触件,并且导电部件与第三源极/漏极接触件和第四源极/漏极接触件直接接触。
在另一示例性方面中,本公开针对一种半导体器件。半导体器件包括第一晶体管和设置在第一晶体管上方的第二晶体管。第一晶体管包括第一源极部件和第一漏极部件以及彼此竖直堆叠并且在第一源极部件和第一漏极部件之间延伸的多个沟道构件。第二晶体管包括第二源极部件和第二漏极部件以及在第二源极部件和第二漏极部件之间延伸的鳍结构。第二源极部件直接位于第一源极部件上方,并且第二漏极部件直接位于第一漏极部件上方。
在一些实施例中,第一晶体管还包括设置在第一漏极部件上方的第一漏极接触件,并且第二晶体管还包括设置在第二漏极部件上方的第二漏极接触件。在一些实施方式中,第一漏极部件包括掺杂有n型掺杂剂的硅,第二漏极部件包括掺杂有p型掺杂剂的硅锗,并且第一漏极接触件和第二漏极接触件包括金属。在一些实施方式中,第一漏极接触件突出在第一漏极部件上方,并且第二漏极接触件突出在第二漏极部件上方。在一些实施例中,半导体器件还可以包括电耦合第一漏极接触件和第二漏极接触件的第一导电部件。在一些情况下,第一导电部件延伸穿过第二漏极部件。在一些实施方式中,第一晶体管还可以包括设置在第一漏极部件下方的第一源极接触件,并且第二晶体管还可以包括设置在第二漏极部件上方的第二源极接触件。
在又一示例性方面中,本公开针对一种方法。该方法包括:在第一衬底上形成第一晶体管,其中,第一晶体管包括第一源极部件和第一漏极部件、彼此竖直堆叠并且在第一源极部件和第一漏极部件之间延伸的多个沟道构件以及包围在多个沟道构件中的每一个周围的第一栅极结构。该方法还可以包括:在第一晶体管上方沉积第一钝化层;在第二衬底上方形成外延层;在外延层上方沉积第二钝化层;将第二钝化层接合至第一钝化层;在接合之后去除第二衬底;图案化外延层以在多个沟道构件上方形成鳍结构;并且形成第二栅极结构以包围在鳍结构上方,其中,第二栅极结构与第一栅极结构接触。
在一些实施例中,外延层包括硅锗。在一些实施方式中,该方法还可以包括:在形成第二栅极结构之前,在鳍结构的沟道区域上方形成伪栅极堆叠件;对鳍结构的源极区域和漏极区域进行开槽以形成源极凹槽和漏极凹槽,源极区域和漏极区域夹持沟道区域;在源极区域中形成第二源极部件,在漏极凹槽中形成第二漏极部件;在第二源极部件和第二漏极部件上方沉积介电层;并且去除伪栅极堆叠件。在一些情况下,该方法还可以包括:在形成第二栅极结构之后,形成穿过第二漏极部件和第一漏极部件的漏极接触件开口;并且在漏极接触件开口中形成导电部件。在一些情况下,该方法还可以包括:在形成第二栅极结构之后,在第二栅极结构上方沉积第三钝化层;在第三衬底上方沉积第四钝化层;将第四钝化层接合至第三钝化层;去除第一衬底;并且形成电耦合至第一源极部件的背侧源极接触件。
在一些实施例中,一种半导体器件,包括:第一晶体管,包括:彼此竖直堆叠的多个沟道构件,和邻接所述多个沟道构件的第一源极/漏极部件;第二晶体管,设置在所述第一晶体管上方,包括:鳍结构,和邻接所述鳍结构的第二源极/漏极部件;以及导电部件,电连接所述第一源极/漏极部件和所述第二源极/漏极部件。在一些实施例中,第一晶体管还包括包围在所述多个沟道构件中的每一个周围的第一栅极结构,其中,所述第二晶体管还包括包围在所述鳍结构上方的第二栅极结构,其中,所述第一栅极结构与所述第二栅极结构接触。在一些实施例中,多个沟道构件包括硅(Si),其中,所述鳍结构包括硅锗(SiGe)。在一些实施例中,多个沟道构件包括硅(Si)、锗(Ge)、硅锗(SiGe)、二硫化钼(MoS2)、二硒化钨(WSe2)或二碲化铪(HfTe2),其中,所述鳍结构包括硅(Si)、锗(Ge)、硅锗(SiGe)、二硫化钼(MoS2)、二硒化钨(WSe2)或二碲化铪(HfTe2)。在一些实施例中,导电部件延伸穿过所述第二源极/漏极部件。在一些实施例中,导电部件延伸穿过所述第一源极/漏极部件。在一些实施例中,第一晶体管还包括设置在所述第一源极/漏极部件上方的第一源极/漏极接触件,其中,所述第二晶体管还包括设置在所述第二源极/漏极部件上方的第二源极/漏极接触件,其中,所述导电部件与所述第一源极/漏极接触件和所述第二源极/漏极接触件直接接触。在一些实施例中,第一晶体管还包括设置在所述第一源极/漏极部件下方的第三源极/漏极接触件,其中,所述第二晶体管还包括设置在所述第二源极/漏极部件上方的第四源极/漏极接触件,其中,所述导电部件与所述第三源极/漏极接触件和所述第四源极/漏极接触件直接接触。
在一些实施例中,一种半导体器件,包括:第一晶体管,包括:第一源极部件和第一漏极部件,和彼此竖直堆叠并且在所述第一源极部件和所述第一漏极部件之间延伸的多个沟道构件;以及第二晶体管,设置在所述第一晶体管上方,包括:第二源极部件和第二漏极部件,和在所述第二源极部件和所述第二漏极部件之间延伸的鳍结构,其中,所述第二源极部件直接位于所述第一源极部件上方,其中,所述第二漏极部件直接位于所述第一漏极部件上方。在一些实施例中,第一晶体管还包括设置在所述第一漏极部件上方的第一漏极接触件,其中,所述第二晶体管还包括设置在所述第二漏极部件上方的第二漏极接触件。在一些实施例中,第一漏极部件包括掺杂有n型掺杂剂的硅,其中,所述第二漏极部件包括掺杂有p型掺杂剂的硅锗,其中,所述第一漏极接触件和所述第二漏极接触件包括金属。在一些实施例中,第一漏极接触件突出在所述第一漏极部件上方,其中,所述第二漏极接触件突出在所述第二漏极部件上方。在一些实施例中,还包括电耦合所述第一漏极接触件和所述第二漏极接触件的第一导电部件。在一些实施例中,第一导电部件延伸穿过所述第二漏极部件。在一些实施例中,第一晶体管还包括设置在所述第一漏极部件下方的第一源极接触件,其中,所述第二晶体管还包括设置在所述第二漏极部件上方的第二源极接触件。
在一些实施例中,一种形成半导体器件的方法,包括:在第一衬底上形成第一晶体管,其中,所述第一晶体管包括:第一源极部件和第一漏极部件,彼此竖直堆叠并且在所述第一源极部件和所述第一漏极部件之间延伸的多个沟道构件,和包围在所述多个沟道构件中的每一个周围的第一栅极结构;在所述第一晶体管上方沉积第一钝化层;在第二衬底上方形成外延层;在所述外延层上方沉积第二钝化层;将所述第二钝化层接合至所述第一钝化层;接合后去除所述第二衬底;图案化所述外延层以在所述多个沟道构件上方形成鳍结构;以及形成第二栅极结构以包围在所述鳍结构上方,其中,所述第二栅极结构与所述第一栅极结构接触。在一些实施例中,外延层包括硅锗。在一些实施例中,还包括:在形成所述第二栅极结构之前,在所述鳍结构的沟道区域上方形成伪栅极堆叠件;对所述鳍结构的源极区域和漏极区域进行开槽以形成源极凹槽和漏极凹槽,所述源极区域和所述漏极区域夹持所述沟道区域;在所述源极区域中形成第二源极部件,并且在所述漏极凹槽中形成第二漏极部件;在所述第二源极部件和所述第二漏极部件上方沉积介电层;并且去除所述伪栅极堆叠件。在一些实施例中,还包括:在形成所述第二栅极结构之后,形成穿过所述第二漏极部件和所述第一漏极部件的漏极接触件开口;并且在所述漏极接触件开口中形成导电部件。在一些实施例中,还包括:在形成所述第二栅极结构之后,在所述第二栅极结构上方沉积第三钝化层;在第三衬底上方沉积第四钝化层;将所述第四钝化层接合至所述第三钝化层;去除所述第一衬底;并且形成电耦合至所述第一源极部件的背侧源极接触件。
上面论述了若干实施例的部件,使得本领域技术人员可以更好地理解本发明的各个实施例。本领域普通技术人员应该理解,可以很容易地使用本发明作为基础来设计或更改其他用于达到与本文所介绍实施例相同的目的和/或实现相同优点的处理和结构。本领域普通技术人员也应该意识到,这种等效构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,可以进行多种变化、替换以及改变。
Claims (10)
1.一种半导体器件,包括:
第一晶体管,包括:
彼此竖直堆叠的多个沟道构件,和
邻接所述多个沟道构件的第一源极/漏极部件;
第二晶体管,设置在所述第一晶体管上方,包括:
鳍结构,和
邻接所述鳍结构的第二源极/漏极部件;以及
导电部件,电连接所述第一源极/漏极部件和所述第二源极/漏极部件。
2.根据权利要求1所述的半导体器件,
其中,所述第一晶体管还包括包围在所述多个沟道构件中的每一个周围的第一栅极结构,
其中,所述第二晶体管还包括包围在所述鳍结构上方的第二栅极结构,
其中,所述第一栅极结构与所述第二栅极结构接触。
3.根据权利要求1所述的半导体器件,
其中,所述多个沟道构件包括硅(Si),
其中,所述鳍结构包括硅锗(SiGe)。
4.根据权利要求1所述的半导体器件,
其中,所述多个沟道构件包括硅(Si)、锗(Ge)、硅锗(SiGe)、二硫化钼(MoS2)、二硒化钨(WSe2)或二碲化铪(HfTe2),
其中,所述鳍结构包括硅(Si)、锗(Ge)、硅锗(SiGe)、二硫化钼(MoS2)、二硒化钨(WSe2)或二碲化铪(HfTe2)。
5.根据权利要求1所述的半导体器件,其中,所述导电部件延伸穿过所述第二源极/漏极部件。
6.根据权利要求5所述的半导体器件,其中,所述导电部件延伸穿过所述第一源极/漏极部件。
7.根据权利要求1所述的半导体器件,
其中,所述第一晶体管还包括设置在所述第一源极/漏极部件上方的第一源极/漏极接触件,
其中,所述第二晶体管还包括设置在所述第二源极/漏极部件上方的第二源极/漏极接触件,
其中,所述导电部件与所述第一源极/漏极接触件和所述第二源极/漏极接触件直接接触。
8.根据权利要求1所述的半导体器件,
其中,所述第一晶体管还包括设置在所述第一源极/漏极部件下方的第三源极/漏极接触件,
其中,所述第二晶体管还包括设置在所述第二源极/漏极部件上方的第四源极/漏极接触件,
其中,所述导电部件与所述第三源极/漏极接触件和所述第四源极/漏极接触件直接接触。
9.一种半导体器件,包括:
第一晶体管,包括:
第一源极部件和第一漏极部件,和
彼此竖直堆叠并且在所述第一源极部件和所述第一漏极部件之间延伸的多个沟道构件;以及
第二晶体管,设置在所述第一晶体管上方,包括:
第二源极部件和第二漏极部件,和
在所述第二源极部件和所述第二漏极部件之间延伸的鳍结构,
其中,所述第二源极部件直接位于所述第一源极部件上方,
其中,所述第二漏极部件直接位于所述第一漏极部件上方。
10.一种形成半导体器件的方法,包括:
在第一衬底上形成第一晶体管,其中,所述第一晶体管包括:
第一源极部件和第一漏极部件,
彼此竖直堆叠并且在所述第一源极部件和所述第一漏极部件之间延伸的多个沟道构件,和
包围在所述多个沟道构件中的每一个周围的第一栅极结构;
在所述第一晶体管上方沉积第一钝化层;
在第二衬底上方形成外延层;
在所述外延层上方沉积第二钝化层;
将所述第二钝化层接合至所述第一钝化层;
接合后去除所述第二衬底;
图案化所述外延层以在所述多个沟道构件上方形成鳍结构;以及
形成第二栅极结构以包围在所述鳍结构上方,其中,所述第二栅极结构与所述第一栅极结构接触。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US202063059011P | 2020-07-30 | 2020-07-30 | |
US63/059,011 | 2020-07-30 | ||
US17/094,904 US11735669B2 (en) | 2020-07-30 | 2020-11-11 | Vertically-oriented complementary transistor |
US17/094,904 | 2020-11-11 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN113675194A true CN113675194A (zh) | 2021-11-19 |
Family
ID=77411535
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202110158373.1A Pending CN113675194A (zh) | 2020-07-30 | 2021-02-04 | 半导体器件及其形成方法 |
Country Status (7)
Country | Link |
---|---|
US (2) | US11735669B2 (zh) |
EP (1) | EP3945560A1 (zh) |
JP (1) | JP2022027654A (zh) |
KR (1) | KR102495803B1 (zh) |
CN (1) | CN113675194A (zh) |
DE (1) | DE102020130964A1 (zh) |
TW (1) | TWI815151B (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP4199062A1 (en) * | 2021-12-20 | 2023-06-21 | INTEL Corporation | Non-reactive epi contact for stacked transistors |
EP4199056A1 (en) * | 2021-12-15 | 2023-06-21 | IMEC vzw | Vertically stacked transistor structures |
EP4199060A1 (en) * | 2021-12-20 | 2023-06-21 | INTEL Corporation | Frontside and backside contact to epi regions |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20210081679A (ko) * | 2019-12-24 | 2021-07-02 | 삼성전자주식회사 | 반도체 장치 |
EP4283663A1 (en) * | 2022-05-24 | 2023-11-29 | Imec VZW | A method for forming a stacked transistor device |
US20230411397A1 (en) * | 2022-06-16 | 2023-12-21 | International Business Machines Corporation | Method and structure of forming sidewall contact for stacked fet |
Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040110331A1 (en) * | 2002-12-06 | 2004-06-10 | Yee-Chia Yeo | CMOS inverters configured using multiple-gate transistors |
CN107527801A (zh) * | 2016-06-17 | 2017-12-29 | 台湾积体电路制造股份有限公司 | 半导体器件及其形成方法 |
CN109216428A (zh) * | 2017-06-29 | 2019-01-15 | 台湾积体电路制造股份有限公司 | 半导体结构及其制造方法 |
CN109524468A (zh) * | 2017-09-18 | 2019-03-26 | 三星电子株式会社 | 半导体器件 |
US10249538B1 (en) * | 2017-10-03 | 2019-04-02 | Globalfoundries Inc. | Method of forming vertical field effect transistors with different gate lengths and a resulting structure |
US20190198400A1 (en) * | 2017-12-26 | 2019-06-27 | International Business Machines Corporation | Junction formation in thick-oxide and thin-oxide vertical fets on the same chip |
US20190319095A1 (en) * | 2017-11-02 | 2019-10-17 | International Business Machines Corporation | Vertically stacked nfets and pfets with gate-all-around structure |
US20200006331A1 (en) * | 2018-06-29 | 2020-01-02 | Intel Corporation | Techniques for forming gate structures for transistors arranged in a stacked configuration on a single fin structure |
US20200006330A1 (en) * | 2018-06-29 | 2020-01-02 | Intel Corporation | Leave-behind protective layer having secondary purpose |
US20200020689A1 (en) * | 2018-07-13 | 2020-01-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | High performance mosfet |
US20200126987A1 (en) * | 2018-10-22 | 2020-04-23 | International Business Machines Corporation | Interlayer via contacts for monolithic three-dimensional semiconductor integrated circuit devices |
US20200168606A1 (en) * | 2018-11-27 | 2020-05-28 | Imec Vzw | Stacked semiconductor device and method of fabricating same |
US20200194446A1 (en) * | 2018-12-17 | 2020-06-18 | Sandisk Technologies Llc | Three-dimensional memory device having stressed vertical semiconductor channels and method of making the same |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11923374B2 (en) * | 2013-03-12 | 2024-03-05 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US10199502B2 (en) | 2014-08-15 | 2019-02-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure of S/D contact and method of making same |
US9818872B2 (en) | 2015-06-30 | 2017-11-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-gate device and method of fabrication thereof |
US9899387B2 (en) | 2015-11-16 | 2018-02-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-gate device and method of fabrication thereof |
US10032627B2 (en) | 2015-11-16 | 2018-07-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming stacked nanowire transistors |
US9754840B2 (en) | 2015-11-16 | 2017-09-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Horizontal gate-all-around device having wrapped-around source and drain |
US9887269B2 (en) | 2015-11-30 | 2018-02-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-gate device and method of fabrication thereof |
US9899269B2 (en) | 2015-12-30 | 2018-02-20 | Taiwan Semiconductor Manufacturing Company, Ltd | Multi-gate device and method of fabrication thereof |
US9899398B1 (en) | 2016-07-26 | 2018-02-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Non-volatile memory device having nanocrystal floating gate and method of fabricating same |
US9711501B1 (en) | 2016-09-26 | 2017-07-18 | International Business Machines Corporation | Interlayer via |
US10290546B2 (en) | 2016-11-29 | 2019-05-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Threshold voltage adjustment for a gate-all-around semiconductor structure |
US10475902B2 (en) | 2017-05-26 | 2019-11-12 | Taiwan Semiconductor Manufacturing Co. Ltd. | Spacers for nanowire-based integrated circuit device and method of fabricating same |
US10867846B2 (en) | 2017-11-15 | 2020-12-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin field effect transistor (finFET) device structure with protection layer and method for forming the same |
US10304832B1 (en) | 2017-11-16 | 2019-05-28 | Globalfoundries Inc. | Integrated circuit structure incorporating stacked field effect transistors and method |
US10685887B2 (en) | 2017-12-04 | 2020-06-16 | Tokyo Electron Limited | Method for incorporating multiple channel materials in a complimentary field effective transistor (CFET) device |
US11374024B2 (en) | 2017-12-27 | 2022-06-28 | Intel Corporation | Integrated circuits with stacked transistors and methods of manufacturing the same using processes which fabricate lower gate structures following completion of portions of an upper transistor |
US11201152B2 (en) | 2018-04-20 | 2021-12-14 | Globalfoundries Inc. | Method, apparatus, and system for fin-over-nanosheet complementary field-effect-transistor |
US11374004B2 (en) | 2018-06-29 | 2022-06-28 | Intel Corporation | Pedestal fin structure for stacked transistor integration |
US11411082B2 (en) | 2018-10-31 | 2022-08-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Nanowire stack GAA device with selectable numbers of channel strips |
US11676966B2 (en) * | 2019-03-15 | 2023-06-13 | Intel Corporation | Stacked transistors having device strata with different channel widths |
-
2020
- 2020-11-11 US US17/094,904 patent/US11735669B2/en active Active
- 2020-11-24 DE DE102020130964.3A patent/DE102020130964A1/de active Pending
- 2020-12-28 KR KR1020200184939A patent/KR102495803B1/ko active IP Right Grant
-
2021
- 2021-02-04 CN CN202110158373.1A patent/CN113675194A/zh active Pending
- 2021-07-26 TW TW110127319A patent/TWI815151B/zh active
- 2021-07-29 JP JP2021124806A patent/JP2022027654A/ja active Pending
- 2021-07-29 EP EP21188625.4A patent/EP3945560A1/en not_active Withdrawn
-
2023
- 2023-07-24 US US18/357,345 patent/US20230369499A1/en active Pending
Patent Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040110331A1 (en) * | 2002-12-06 | 2004-06-10 | Yee-Chia Yeo | CMOS inverters configured using multiple-gate transistors |
CN107527801A (zh) * | 2016-06-17 | 2017-12-29 | 台湾积体电路制造股份有限公司 | 半导体器件及其形成方法 |
CN109216428A (zh) * | 2017-06-29 | 2019-01-15 | 台湾积体电路制造股份有限公司 | 半导体结构及其制造方法 |
CN109524468A (zh) * | 2017-09-18 | 2019-03-26 | 三星电子株式会社 | 半导体器件 |
US10249538B1 (en) * | 2017-10-03 | 2019-04-02 | Globalfoundries Inc. | Method of forming vertical field effect transistors with different gate lengths and a resulting structure |
US20190319095A1 (en) * | 2017-11-02 | 2019-10-17 | International Business Machines Corporation | Vertically stacked nfets and pfets with gate-all-around structure |
US20190198400A1 (en) * | 2017-12-26 | 2019-06-27 | International Business Machines Corporation | Junction formation in thick-oxide and thin-oxide vertical fets on the same chip |
US20200006331A1 (en) * | 2018-06-29 | 2020-01-02 | Intel Corporation | Techniques for forming gate structures for transistors arranged in a stacked configuration on a single fin structure |
US20200006330A1 (en) * | 2018-06-29 | 2020-01-02 | Intel Corporation | Leave-behind protective layer having secondary purpose |
US20200020689A1 (en) * | 2018-07-13 | 2020-01-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | High performance mosfet |
US20200126987A1 (en) * | 2018-10-22 | 2020-04-23 | International Business Machines Corporation | Interlayer via contacts for monolithic three-dimensional semiconductor integrated circuit devices |
US20200168606A1 (en) * | 2018-11-27 | 2020-05-28 | Imec Vzw | Stacked semiconductor device and method of fabricating same |
US20200194446A1 (en) * | 2018-12-17 | 2020-06-18 | Sandisk Technologies Llc | Three-dimensional memory device having stressed vertical semiconductor channels and method of making the same |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP4199056A1 (en) * | 2021-12-15 | 2023-06-21 | IMEC vzw | Vertically stacked transistor structures |
EP4199062A1 (en) * | 2021-12-20 | 2023-06-21 | INTEL Corporation | Non-reactive epi contact for stacked transistors |
EP4199060A1 (en) * | 2021-12-20 | 2023-06-21 | INTEL Corporation | Frontside and backside contact to epi regions |
Also Published As
Publication number | Publication date |
---|---|
US20230369499A1 (en) | 2023-11-16 |
JP2022027654A (ja) | 2022-02-10 |
US11735669B2 (en) | 2023-08-22 |
US20220037528A1 (en) | 2022-02-03 |
DE102020130964A1 (de) | 2022-02-03 |
TW202205449A (zh) | 2022-02-01 |
KR102495803B1 (ko) | 2023-02-07 |
KR20220016440A (ko) | 2022-02-09 |
TWI815151B (zh) | 2023-09-11 |
EP3945560A1 (en) | 2022-02-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR102495803B1 (ko) | 수직-배향된 상보형 트랜지스터 | |
US11532627B2 (en) | Source/drain contact structure | |
US11862701B2 (en) | Stacked multi-gate structure and methods of fabricating the same | |
US11777016B2 (en) | Method of forming backside power rails | |
CN114512442A (zh) | 半导体装置 | |
KR102495805B1 (ko) | 후면 콘택 | |
TWI793675B (zh) | 半導體裝置及其形成方法 | |
US11450664B2 (en) | Semiconductor device having nanosheet transistor and methods of fabrication thereof | |
US20220367482A1 (en) | Source/Drain Feature Separation Structure | |
US20220367483A1 (en) | Semiconductor device having an offset source/drain feature and method of fabricating thereof | |
TWI801864B (zh) | 半導體裝置及其形成方法 | |
CN113451307A (zh) | 半导体器件及其形成方法 | |
CN116133360A (zh) | 半导体器件及其形成方法 | |
CN114551352A (zh) | 半导体器件及其制造方法 | |
CN114284266A (zh) | 半导体装置 | |
US20230187518A1 (en) | Semiconductor Device With Tunable Channel Layer Usage And Methods Of Fabrication Thereof | |
US20230137766A1 (en) | Semiconductor Structures Having A Continuous Active Region | |
US20240178302A1 (en) | Semiconductor device with protective gate structure and methods of fabrication thereof | |
US11670691B2 (en) | Method for forming source/drain contacts utilizing an inhibitor | |
US20230361184A1 (en) | Semiconductor device structure and methods of forming the same | |
US20240072136A1 (en) | Semiconductor structure and method for manufacturing the same | |
CN115841983A (zh) | 半导体结构及其形成方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination |