TWI815151B - 半導體裝置及其形成方法 - Google Patents

半導體裝置及其形成方法 Download PDF

Info

Publication number
TWI815151B
TWI815151B TW110127319A TW110127319A TWI815151B TW I815151 B TWI815151 B TW I815151B TW 110127319 A TW110127319 A TW 110127319A TW 110127319 A TW110127319 A TW 110127319A TW I815151 B TWI815151 B TW I815151B
Authority
TW
Taiwan
Prior art keywords
drain
source
component
layer
transistor
Prior art date
Application number
TW110127319A
Other languages
English (en)
Other versions
TW202205449A (zh
Inventor
莊其毅
陳豪育
程冠倫
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW202205449A publication Critical patent/TW202205449A/zh
Application granted granted Critical
Publication of TWI815151B publication Critical patent/TWI815151B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221—Three dimensional integrated circuits stacked in different levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02293—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66818—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the channel being thinned after patterning, e.g. sacrificial oxidation on fin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Nanotechnology (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Semiconductor Memories (AREA)

Abstract

根據本發明實施例的半導體裝置包括第一電晶體與設置於第一電晶體上的第二電晶體。第一電晶體包括彼此垂直堆疊的複數個通道構件、以及鄰接複數個通道構件的第一源極/汲極部件。第二電晶體包括鰭片結構、以及鄰接鰭片結構的第二源極/汲極部件。半導體裝置更包括電性連接第一源極/汲極部件與第二源極/汲極部件的導電部件。

Description

半導體裝置及其形成方法
本揭露是關於半導體裝置，特別是關於一種包含通道構件的半導體裝置。
半導體積體電路產業經歷了快速成長。積體電路材料及設計的技術演進已經產生了多個世代的積體電路，其中各個世代具有比先前世代更小且更複雜的電路。積體電路演進期間，功能密度(亦即，單位晶片面積的互連裝置數目)通常會增加而幾何尺寸(亦即，即可使用製程生產的最小元件(或線))卻減少。此微縮化的過程通常會以增加生產效率與降低相關成本而提供助益。此微縮化也增加了處理及製造積體電路的複雜性。
舉例而言，隨著積體電路技術向更小的技術節點發展，已經引入了多閘極裝置以藉由增加閘極-通道耦合、降低截止狀態電流、以及減少短通道效應(short-channel effects，SCEs)以改善閘極控制。多閘極裝置通常是指具有設置於通道區的多於一側的閘極結構或其部分的裝置。鰭式場效電晶體(Fin-like field effect transistors，FinFETs)與多橋通道(multi-bridge-channel，MBC)電晶體為多閘極裝置的範例，它們已成為高效能且低漏電(leakage)應用之普及且有希望的候選裝置。FinFET具有在多於一側由閘極包覆之升高的通 道(舉例而言，閘極包覆從基板延伸的半導體材料的「鰭片」的頂部及側壁)。MBC電晶體具有能夠部分或完全地圍繞通道區延伸以在兩側或更多側提供對通道區的通路(access)的閘極結構。由於其閘極結構環繞通道區，MBC電晶體也可以被稱為環繞閘極電晶體(surrounding gate transistor，SGT)或全繞式閘極(gate-all-around，GAA)電晶體。MBC電晶體的通道區可以由奈米線、奈米片、其他奈米結構、及/或其他適合的結構所形成。
互補式金屬氧化物場效電晶體(complementary metal-oxide-semiconductor field effect transistors，CMOSFET或CFET)由於其高抗擾性(noise immunity)及低靜態功率消耗(static power consumption)主導了半導體產業。雖然現有的CFET結構大致滿足了其預期目的，它們並非在所有方面皆令人滿意。
一種半導體裝置，包括：第一電晶體，包括：複數個通道構件，彼此垂直堆疊；以及第一源極/汲極部件，鄰接(adjoining)通道構件；第二電晶體，設置於第一電晶體上，第二電晶體包括：鰭片結構；以及第二源極/汲極部件，鄰接鰭片結構；以及導電部件，電性連接第一源極/汲極部件與第二源極/汲極部件。
一種半導體裝置，包括：第一電晶體，包括：第一源極部件及第一汲極部件；以及複數個通道構件，彼此垂直堆疊且在第一源極部件與第一汲極部件之間延伸；以及第二電晶體，設置於第一電晶體上，第二電晶體包括：第二源極部件及第二汲極部件；以及鰭片結構，在第二源極部件與第二汲極部 件之間延伸，其中第二源極部件位於第一源極部件正上方，其中第二汲極部件位於第一汲極部件正上方。
一種半導體裝置的形成方法，包括：在第一基板上形成第一電晶體，其中第一電晶體包括：第一源極部件及第一汲極部件；複數個通道構件，彼此垂直堆疊且在第一源極部件與第一汲極部件之間延伸；以及第一閘極結構，第一閘極結構包繞各個通道構件；在第一電晶體上沉積第一鈍化層；在第二基板上形成磊晶層；在磊晶層上沉積第二鈍化層；將第二鈍化層接合至第一鈍化層；在接合之後，移除第二基板；圖案化磊晶層以在通道構件上形成鰭片結構；以及形成第二閘極結構以包覆在鰭片結構上，其中第二閘極結構與第一閘極結構接觸。
100:方法
102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132,134:方框
200:工件(半導體裝置)
202:第一基板
204:堆疊
206:犧牲層
208:通道層
210:鰭形結構
210B:基部
210C:第一通道區
210D:第一汲極區
210S:第一源極區
210SP:堆疊部
212:隔離部件
214:第一虛置閘極堆疊
216,254:虛置介電層
218,256:虛置閘極介電層
220:第一閘極間隔層
222D:第一汲極凹槽
222S:第一源極凹槽
224:內間隔凹槽
226:內間隔部件
228D:第一汲極部件
228S:第一源極部件
230:第一接觸蝕刻停止層(第一CESL)
232:第一層間介電層(第一ILD層)
236:第一閘極介電層
238:第一閘極電極層
240:第一閘極結構
242,281,304,316,318,326,328,334,338:矽化物層
244:下汲極接觸件
244’:替代的下汲極接觸件
246:第一鈍化層
248:第二鈍化層
250:磊晶層
251:第二基板
252:鰭片元件
258:第二虛置閘極堆疊
260:第二閘極間隔層
262D:第二汲極凹槽
262S:第二源極凹槽
264D:第二汲極部件
264S:第二源極部件
266:第二接觸蝕刻停止層(第二CESL)
268:第二層間介電層(第二ILD層)
270:第二閘極介電層
272:第二閘極電極層
274:第二閘極結構
275:內連線結構
276:第三鈍化層
280:上源極接觸件
282:上汲極接觸件
282’:替代的上汲極接觸件
284:第一導電部件
286:第四鈍化層
288:承載基板
290:背側接觸蝕刻停止層(BCESL)
292:背側介電層
294:背側矽化物層
296:背側源極接觸件
302:第一導孔接觸件開口
306:第二導電部件
312:第一導通孔開口
314:第四導電部件
322:第二導孔開口
324:第五導電部件
332:第二導孔接觸件開口
336:第三導電部件
400:半導體裝置
1000:n型MBC電晶體
2000:p型FinFET
2080:通道構件
2440:第一懸突部
2820:第二懸突部
X,Y,Z:方向
以下將配合所附圖式詳述本發明實施例。應注意的是，依據在業界的標準做法，各種特徵並未按照比例繪製且僅用以說明例示。事實上，可任意地放大或縮小元件的尺寸，以清楚地表現出本發明實施例的特徵。
第1圖是根據本揭露的一或多個面向，繪示出具有垂直定向的(vertical-oriented)互補式電晶體的半導體裝置的形成方法的流程圖。
第2~39圖是根據本揭露的一或多個面向，繪示出根據第1圖的方法的製造過程時的工件的局部剖面圖。
第40圖是根據本揭露的一或多個面向，繪示出半導體裝置的替代的實施例。
以下揭露提供了許多的實施例或範例，用於實施所提供的標的物之不同元件。各元件和其配置的具體範例描述如下，以簡化本發明實施例之說明。當然，這些僅僅是範例，並非用以限定本發明實施例。舉例而言，敘述中若提及第一元件形成在第二元件之上，可能包含第一和第二元件直接接觸的實施例，也可能包含額外的元件形成在第一和第二元件之間，使得它們不直接接觸的實施例。此外，本發明實施例可能在各種範例中重複參考數值以及/或字母。如此重複是為了簡明和清楚之目的，而非用以表示所討論的不同實施例及/或配置之間的關係。
再者，其中可能用到與空間相對用詞，例如「在......之下」、「下方」、「較低的」、「上方」、「較高的」等類似用詞，是為了便於描述圖式中一個(些)部件或特徵與另一個(些)部件或特徵之間的關係。空間相對用詞用以包括使用中或操作中的裝置之不同方位，以及圖式中所描述的方位。當裝置被轉向不同方位時(旋轉90度或其他方位)，其中所使用的空間相對形容詞也將依轉向後的方位來解釋。
此外，當使用「大約」、「近似」等描述一個數字或數字範圍時，此用語意圖涵蓋合理範圍內的數字，此範圍是根據本領域具有通常知識者所理解的製造過程中固有出現的變異而加以考量。例如，基於製造具有該數字相關特徵的部件的已知製造公差，數字的數量或範圍涵蓋了包括所述數字在內的合理範圍，例如所述數字的+/-10%以內。例如，本領域具有通常知識者已知與沈積材料層相關的製造公差為+/-15%，具有「約5奈米」厚度的材料層可以涵蓋4.25奈米至5.75奈米的尺寸範圍。更進一步，本揭露可以在各種範例中重複參考數字及/或字母。這樣的重複係以簡潔且清楚為目的，且本身並未指定所討論的各種 實施例及/或配置之間的關係。
由於高抗擾性及低靜態功率消耗，互補式金屬氧化物半導體場效電晶體(CMOSFET或CFET)已主導了半導體產業。習知的CFET包括並排(side-by-side)設置於同一基板上的n型FET(n-type FET，NFET)及p型FET(p-type FET，PFET)，且NFET及PFET共享相同的結構。舉例而言，在一些習知的設計中，NFET及PFET兩者皆為平面裝置、皆為FinFET、或皆為MBC電晶體。一旦裝置尺寸因為先進的技術節點而持續縮小，至少出現了兩個挑戰。第一，共平面的CFET具有比NFET或PFET更大的覆蓋區(footprint)。第二，PFETs中的電洞移動率持續落後(lag behind)於NFETs中的電子移動率。
本揭露提供了垂直定向的混合式(hybrid)CFET的製程及結構以解決以上指出的兩個挑戰。由於是垂直定向的，根據本揭露的CFET包括底電晶體以及設置於底電晶體上的頂電晶體。在一些實例中，底電晶體為p型電晶體且頂電晶體為n型電晶體。在其他實例中，底電晶體為n型電晶體且頂電晶體為p型電晶體。由於是混合式的，根據本揭露的CFET包括p型FinFET(p-type FinFET，p-FinFET)及n型MBC(n-type MBC，n-MBC)電晶體。因此本揭露的CFET包括作為底電晶體的p-FinFET及作為頂電晶體的n-MBC電晶體，或者反之亦然。在一些實施例中，頂電晶體的源極部件及汲極部件與底電晶體的源極部件及汲極部件實質上垂直對準。上述垂直對準使得藉由導電部件將底部裝置的源極/汲極部件耦合至頂部裝置的源極/汲極部件變得可能。在一些實施例中，導電部件可以垂直延伸至源極部件與汲極部件來耦合。背側源極接觸件與背側電源軌(power rail)也可以以本揭露的CFET來集成。
以下將參照圖式以更詳細地描述本揭露的各種面向。在這方面， 根據本揭露的實施例，第1圖是繪示出由工件形成半導體裝置的方法100的流程圖。方法100僅為範例且並非用以將本揭露限制為方法100中所明確繪示的內容。可以在方法100之前、期間、及之後提供額外的步驟，且所述的一些步驟可以被取代、刪除、或移動以用於上述方法的額外的實施例。為了簡化起見，並非所有的步驟皆在此詳細描述。以下與第2~39圖一起描述方法100，第2~39圖為根據方法100的實施例之製造的不同階段的工件200的部分剖面圖。為了避免疑慮，在所有圖式中，X方向與Y方向垂直，且Z方向與X方向及Y方向兩者垂直。應注意的是，因為工件200可以被製造成半導體裝置，工件200可以在上下文需要時被稱為半導體裝置200。在本揭露全文中，在本揭露中類似的參考數字標示類似的部件。
參照第1及2圖，方法100包括方框102，其中提供了工件200。工件200可以包括第一基板202。在一個實施例中，第一基板202可以是矽(Si)基板。在一些實施例中，第一基板202可以包括其他半導體，例如鍺(Ge)、矽鍺(SiGe)、或三五族半導體材料。三五族半導體材料的範例可以包括砷化鎵(GaAs)、磷化銦(InP)、磷化鎵(GaP)、氮化鎵(GaN)、磷化砷化鎵(gallium arsenide phosphide，GaAsP)、砷化鋁銦(aluminum indium arsenide，AlInAs)、砷化鋁鎵(aluminum gallium arsenide，AlGaAs)、磷化鎵銦(gallium indium phosphide，GaInP)、及砷化銦鎵(indium gallium arsenide，InGaAs)。
如第2圖所示，工件200也包括設置於基板202上的堆疊204。堆疊204包括由複數個犧牲層206交錯(interleaved)的複數個通道層208。通道層208與犧牲層206可以具有不同的半導體成分。在一個實施例中，通道層208由矽所(Si)形成，且犧牲層206由矽鍺(SiGe)所形成。在這些實施中，犧牲層206 中的額外的鍺含量可允許犧牲層之選擇性移除或凹蝕而對通道層208沒有實質上的損害。在一些替代的實施例中，通道層208可以包括鍺(Ge)、矽鍺(SiGe)、或二維(two-dimensional，2D)材料，例如二硫化鉬(MoS2)、二硒化鎢(WSe2)、或二碲化鉿(HfTe2)。在通道層208與犧牲層206由矽鍺(SiGe)所形成的實施例中，通道層208具有比犧牲層206更小的鍺含量以允許犧牲層206之選擇性凹蝕/移除。在一些實施例中，犧牲層206與通道層208為磊晶層，其可以利用磊晶製程來沉積。適合的磊晶製程包括氣相磊晶(vapor-phase epitaxy，VPE)、極高真空化學氣相沉積(ultra-high vacuum chemical vapor deposition，UHV-CVD)、分子束磊晶(molecular beam epitaxy，MBE)、及/或其他適合的製程。如第2圖所示，犧牲層206與通道層208係一個接著另一個地交替沉積以形成堆疊204。應注意的是，如第2圖所繪示，三(3)層的犧牲層206與三(3)層的通道層208交替且垂直地排列，這僅是用於說明之目的且不意圖將本揭露作出除了請求項中明確記載範圍之外的限制。可以理解的是，能夠在堆疊204中形成任何數目的犧牲層206與通道層208。膜層的數目取決於用於裝置200之所需的數目的通道構件。在一些實施例中，通道層208的數目在2與10之間。
參照第1及3圖，方法100包括方框104，其中鰭形結構210係由堆疊204所形成。在一些實施例中，圖案化堆疊204與一部分的第一基板202以形成鰭形結構210。為了圖案化之目的，可以在堆疊204上沉積硬遮罩層。硬遮罩層可以是單層或多層。在一個範例中，硬遮罩層包括氧化矽層以及氧化矽層上的氮化矽層。如第3圖所示，鰭形結構210從第一基板202沿著Z方向垂直延伸，且沿著Y方向縱向延伸。鰭形結構210可以包括由基板202形成的基部(base portion)210B以及由堆疊204形成的堆疊部210SP。鰭形結構210可以利用適合的製程來圖 案化，包括雙重圖案化或多重圖案化製程。一般來說，雙重圖案化或多重圖案化製程結合了微影製程與自對準製程，以創建出例如，比使用單一、直接微影製程所得的節距更小的圖案。例如，在一實施例中，在基板上方形成材料層，並使用微影製程對其進行圖案化。使用自對準製程在圖案化的材料層旁邊形成間隔物。之後去除材料層，然後可以使用剩餘的間隔物或心軸作為遮罩以藉由蝕刻堆疊204與第一基板202來圖案化鰭形結構210。蝕刻製程可以包括乾蝕刻、濕蝕刻、反應離子蝕刻(reactive ion etching，RIE)、及/或其他適合的製程。
參照第1、4、及5圖，方法100包括方框106，其中在鰭形結構210的通道區上形成第一虛置閘極堆疊214。在第4圖所表示的一些實施例中，在形成鰭形結構210之後，形成隔離部件212以環繞基部210B。隔離部件212也可以被稱為淺溝槽隔離(shallow trench isolation，STI)部件212。在一個範例製程中，利用CVD、次常壓CVD(sub-atmospheric CVD，SACVD)、流動式CVD、原子層沉積(atomic layer deposition，ALD)、物理氣相沉積(physical vapor deposition，PVD)、旋轉塗佈、及/或其他適合的製程以在鰭形結構210上沉積用於隔離部件212的介電材料。接著平坦化並凹蝕所沉積的介電材料直到至少鰭形結構210的堆疊部210SP高於隔離部件212。也就是說，在凹蝕隔離部件212之後，鰭形結構210的基部210B被隔離部件212環繞。用於隔離部件212的介電材料可以包括氧化矽、氮氧化矽、氟摻雜矽酸鹽玻璃(fluorine-doped silicate glass，FSG)、低介電常數介電質、前述之組合、及/或其他適合的材料。
在採用閘極替換製程(或閘極後製製程(gate-last process))的一些實施例中，在鰭形結構210上形成第一虛置閘極堆疊214以作為用於功能性閘極結構的佔位件(placeholders)。其他製程及配置也是可行的。為了形成第 一虛置閘極堆疊214，在工件200上沉積虛置介電層216、虛置閘極電極層218、及閘極頂(gate-top)硬遮罩層(未顯示)。這些膜層的沉積可以包括使用低壓CVD(low-pressure CVD，LPCVD)、CVD、電漿輔助CVD(plasma-enhanced CVD，PECVD)、PVD、ALD、熱氧化、電子束蒸鍍(e-beam evaporation)、或其他適合的沉積技術、或前述之組合。虛置介電層216可以包括氧化矽，虛置閘極電極層218可以包括多晶矽，且閘極頂硬遮罩層可以是包括氧化矽及氮化矽的多層。利用微影及蝕刻製程，可圖案化閘極頂硬遮罩層。微影製程可以包括光阻塗佈(例如，旋轉塗佈)、軟烤(soft baking)、遮罩對準、曝光、曝光後烘烤、光阻顯影、沖洗(rinsing)、乾燥(例如，旋轉乾燥(spin-drying)及/或硬烤(hard baking))、其他適合的微影技術、及/或前述之組合。蝕刻製程可以包括乾蝕刻(例如，RIE蝕刻)、濕蝕刻、及/或其他蝕刻方法。之後，將圖案化的閘極頂硬遮罩用作蝕刻遮罩，接著蝕刻虛置介電層216及虛置閘極電極層218以形成第一虛置閘極堆疊214。如第4圖所示，在隔離部件212及一部分的鰭形結構210上形成第一虛置閘極堆疊214。第一虛置閘極堆疊214沿著X方向縱向延伸以包覆在鰭形結構210上。參照第5圖，在第一虛置閘極堆疊214下方的部分的鰭形結構210為第一通道區210C。第一通道區210C及第一虛置閘極堆疊214也定義了第一源極區210S及第一汲極區210D，其中第一源極區210S及第一汲極區210D並未被第一虛置閘極堆疊214垂直重疊。第一通道區210C係沿著Y方向設置或夾在第一源極區210S與第一汲極區210D之間。
如第5圖所示，在方框106的操作可以包括在第一虛置閘極堆疊214的側壁上形成第一閘極間隔層220。在一些實施例中，第一閘極間隔層220的形成包括在工件200上順應性地沉積一或多個介電層。在一個範例製程中，上述 一或多個介電層是利用CVD、SACVD、或ALD來沉積。上述一或多個介電層可以包括氧化矽、氮化矽、碳化矽、氮氧化矽、碳氮化矽、碳氧化矽、氮碳氧化矽(silicon oxycarbonitride)、及/或前述之組合。
參照第1及5圖，方法100包括方框108，其中凹蝕了鰭形結構210的第一源極區210S與第一汲極區210D以形成第一源極凹槽222S與第一汲極凹槽222D。在一個範例製程中，在沉積第一閘極間隔層220之後，在選擇性凹蝕鰭形結構210的第一源極區210S與第一汲極區210D的蝕刻製程中蝕刻工件200。第一源極區210S與第一汲極區210D的選擇性凹蝕可形成第一源極凹槽222S與第一汲極凹槽222D。在方框108的蝕刻製程可以是乾蝕刻製程或適合的蝕刻製程。在一個範例乾蝕刻製程中，可以使用含氧氣體、氫氣、含氟氣體(例如，CF4、SF6、CH2F2、CHF3、及/或C2F6)、含氯氣體(例如，Cl2、CHCl3、CCl4、及/或BCl3)、含溴氣體(例如，HBr及/或CHBr3)、含碘氣體、其他適合的氣體及/或電漿、及/或前述之組合。如第5圖所示，犧牲層206與通道層208在第一通道區210C的側壁在第一源極凹槽222S與第一汲極凹槽222D中露出。
參照第1、6、及7圖，方法100包括方框110，其中形成了內間隔部件226。首先參照第6圖，在方框110，在第一源極凹槽222S與第一汲極凹槽222D中露出的犧牲層206被選擇性且部分地凹蝕以形成內間隔凹槽224，且實質上未蝕刻露出的通道層208。在通道層208大抵由矽(Si)組成且犧牲層206大抵由矽鍺(SiGe)組成的一個實施例中，犧牲層206之選擇性且部分凹蝕可以包括SiGe氧化製程，接著進行SiGe氧化物移除。在這個實施例中，SiGe氧化製程可以包括使用臭氧(O3)。在一些其他的實施例中，選擇性凹蝕可以是選擇性等向性蝕刻製程(例如，選擇性乾蝕刻製程或選擇性濕蝕刻製程)，且犧牲層206凹蝕 的程度可以藉由蝕刻製程的持續時間來控制。選擇性乾蝕刻製程可以包括使用一或多個基於氟的(fluorine-based)蝕刻劑，例如氟氣或氫氟碳化物(hydrofluorocarbons)。選擇性濕蝕刻製程可以包括APM蝕刻(例如，氫氧化氨-過氧化氫-水混合物)。
接著參照第7圖，在內間隔凹槽224的形成之後，在工件200上且包括在內間隔凹槽224中沉積內間隔材料層。內間隔材料層可以包括氧化矽、氮化矽、氮氧化矽、氮碳氧化矽、碳氮化矽、金屬矽化物、或適合的介電材料。接著回蝕所沉積的內間隔材料層以移除在第一閘極間隔層220上以及通道層208的側壁上之過量的內間隔材料層，藉此形成如第7圖所示的內間隔部件226。在一些實施例中，在方框110的回蝕製程可以是乾蝕刻製程，其包括使用含氧氣體、氫氣、氮氣、含氟氣體(例如，CF4、SF6、CH2F2、CHF3、及/或C2F6)、含氯氣體(例如，Cl2、CHCl3、CCl4、及/或BCl3)、含溴氣體(例如，HBr及/或CHBr3)、含碘氣體(例如，CF3I)、其他適合的氣體及/或電漿、及/或前述之組合。
參照第1及8圖，方法100包括方框112，其中在第一源極凹槽222S與第一汲極凹槽222D中形成第一源極部件228S與第一汲極部件228D。在一些實施例中，第一源極部件228S與第一汲極部件228D可以利用磊晶製程來形成，例如VPE、UHV-CVD、MBE、及/或其他適合的製程。磊晶成長製程可以使用氣體及/或液體前驅物，其與基板202以及通道層208的成分起交互作用。因此第一源極部件228S與第一汲極部件228D耦合至通道層。在一些實施例中，第一源極部件228S與第一汲極部件228D可以是n型源極/汲極部件。範例n型源極/汲極部件可以包括Si、GaAs、GaAsP、SiP、或其他適合的材料，且可以藉由在磊晶製程 時引入n型摻質來原位摻雜，上述n型摻質為例如磷(P)、砷(As)，或是利用佈植製程(即，接面佈植製程)來非原位(ex-situ)摻雜。在一個實施例中，第一源極部件228S與第一汲極部件228D包括磷摻雜矽(phosphorus-doped silicon，Si：P)。
參照第1、9、10及11圖，方法100包括方框114，其中第一虛置閘極堆疊214被第一閘極結構240取代。在方框114的操作包括：沉積第一接觸蝕刻停止層(contact etch stop layer，CESL)230(顯示於第9圖)、沉積第一層間介電(interlayer dielectric，ILD)層232(顯示於第9圖)、移除第一虛置閘極堆疊214(顯示於第10圖)、選擇性移除犧牲層206以釋放通道層208來作為通道構件2080(顯示於第10圖)、形成第一閘極結構240(顯示於第10圖)、以及平坦化工件200以移除過量的材料。第一CESL230可以包括氮化矽、氮氧化矽、及/或其他本領域中已知的材料，且可以藉由ALD、電漿輔助化學氣相沉積(PECVD)製程及/或其他適合的沉積或氧化製程來形成。如第9圖所示，第一CESL230可以被沉積在第一源極部件228S與第一汲極部件228D的頂表面上。之後，在第一CESL230上沉積第一ILD層232。第一ILD層232可以包括例如正矽酸乙脂(tetraethylorthosilicate，TEOS)氧化物、未摻雜的矽酸鹽玻璃、或摻雜的氧化矽，例如硼磷矽酸鹽玻璃(borophosphosilicate glass，BPSG)、熔融石英玻璃(fused silica glass，FSG)、磷矽酸鹽玻璃(phosphosilicate glass，PSG)、硼摻雜矽玻璃(boron doped silicon glass，BSG)、及/或其他適合的介電材料。第一ILD層232可以藉由PECVD製程或其他適合的沉積技術來沉積。在一些實施例中，在形成第一ILD層232之後，可以退火工件200以改善第一ILD層232的完整性(integrity)。為了移除過量的材料並露出第一虛置閘極堆疊214的頂表面，可以 進行例如化學機械研磨(chemical mechanical polishing，CMP)製程的平坦化製程。
在一些實施中，各個通道構件2080具有大於其厚度(沿著Z方向)的寬度(沿著X方向)，且可以被稱為奈米片。在一些實施例中，通道構件2080的寬度可以在約8nm及約60nm之間，且通道構件2080的厚度可以在約3nm及約9nm之間。對於各個通道構件2080，主表面為頂表面及底表面。當第一基板202係由矽所形成且具有在(100)面的頂表面時，通道構件2080的主表面也在(100)面上，其提供優於其他表面的電子移動率。
參照第10圖。隨著第一虛置閘極堆疊214的露出，方框114進行到移除第一虛置閘極堆疊214。移除第一虛置閘極堆疊214可以包括一或多個蝕刻製程，其對第一虛置閘極堆疊214中的材料具有選擇性。舉例而言，可以利用選擇性濕蝕刻、選擇性乾蝕刻、或前述之組合以進行第一虛置閘極堆疊214的移除。在移除第一虛置閘極堆疊214之後，通道層208與犧牲層206在第一通道區210C中的側壁是露出的。之後，選擇性移除第一通道區210C中的犧牲層206以釋放通道層208來作為通道構件2080。在此，因為通道構件2080的尺寸為奈米尺度，通道構件也可以被稱為奈米結構。犧牲層206的選擇性移除可以藉由選擇性乾蝕刻、選擇性濕蝕刻、或其他選擇性蝕刻製程來進行。在一些實施例中，選擇性濕蝕刻包括APM蝕刻(例如，氫氧化氨-過氧化氫-水混合物)。在一些實施例中，選擇性移除包括SiGe氧化，接著進行矽鍺氧化物的移除。舉例而言，可以藉由臭氧清潔(ozone clean)以提供上述氧化，且接著藉由例如NH4OH的蝕刻劑以移除矽鍺氧化物。
接著參照第11圖。隨著通道構件2080被釋放，沉積第一閘極結構 240以包繞(wrap around)第一通道區210C中的各個通道構件2080。第一閘極結構240包括第一閘極介電層236及第一閘極電極層238。第一閘極介電層236可以包括界面層及高介電常數介電層。在此，高介電常數介電層是指由介電材料所形成且具有大於二氧化矽的介電常數(約3.9)的介電常數的膜層。在一些實施例中，界面層包括氧化矽，且可以在預清潔(pre-clean)製程中形成。一個範例預清潔製程可以包括使用RCA SC-1(氨、過氧化氫及水)及/或RCA SC-2(氫氯酸、過氧化氫及水)。接著利用ALD、CVD、及/或其他適合的方法在界面層上沉積高介電常數介電層。高介電常數層介電層可以包括氧化鉿。替代地，高介電常數介電層可以包括其他高介電常數介電質，例如氧化鈦(TiO2)、氧化鉿鋯(HfZrO)、氧化鉭(Ta2O5)、氧化鉿矽(HfSiO4)、氧化鋯(ZrO2)、氧化鋯矽(ZrSiO2)、氧化鑭(La2O3)、氧化鋁(Al2O3)、氧化鋯(ZrO)、氧化釔(Y2O3)、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、氧化鉿鑭(HfLaO)、氧化鑭矽(LaSiO)、氧化鋁矽(AlSiO)、氧化鉿鉭(HfTaO)、氧化鉿鈦(HfTiO)、(Ba,Sr)TiO3(BST)、氮化矽(SiN)、氮氧化矽(SiON)、前述之組合、或其他適合的材料。
繼續參照第11圖，接著利用ALD、PVD、CVD、電子束蒸鍍、或其他適合的方法以在第一閘極介電層236上沉積第一閘極電極層238。第一閘極電極層238可以包括單層或替代地包括多層結構，例如具有選定的功函數以增進裝置效能之金屬層(功函數金屬層)、襯層、潤濕層、黏著層、金屬合金或金屬矽化物的各種組合。舉例來說，第一閘極電極層238可以包括氮化鈦(TiN)、鈦鋁(TiAl)、氮化鈦鋁(TiAlN)、氮化鉭(TaN)、鉭鋁(TaAl)、氮化鉭鋁(TaAlN)、碳化鉭鋁(TaAlC)、碳氮化鉭(TaCN)、鋁(Al)、鎢(W)、 鎳(Ni)、鈦(Ti)、釕(Ru)、鈷(Co)、鉑(Pt)、碳化鉭(TaC)、氮化鉭矽(TaSiN)、銅(Cu)、其他耐火金屬、或其他適合的金屬材料、或前述之組合。
參照第1、12、及13圖，方法100包括方框116，其中形成了下汲極接觸件244。在第12圖所示的範例製程中，使用為影製程以形成露出第一汲極部件228D的接觸件開口。為了降低接觸電阻，藉由在第一汲極部件228D上沉積金屬層並進行退火製程以在金屬層與第一汲極部件228D之間導致矽化，可以在第一汲極部件228D上形成矽化物層242。適合的金屬層可以包括鈦(Ti)、鉭(Ta)、鎳(Ni)、鈷(Co)、或鎢(W)。矽化物層242可以包括矽化鈦(TiSi)、氮化鈦矽(TiSiN)、矽化鉭(TaSi)、矽化鎢(WSi)、矽化鈷(CoSi)、或矽化鎳(NiSi)。在形成矽化物層242之後，可以將金屬填充層沉積至接觸件開口中。金屬填充層可以包括氮化鈦(TiN)、鈦(Ti)、釕(Ru)、鎳(Ni)、鈷(Co)、銅(Cu)、鉬(Mo)、鎢(W)、鉭(Ta)、或氮化鉭(TaN)。接著可以進行平坦化製程以移除過量的材料，藉此形成下汲極接觸件244。因為上述平坦化製程，下汲極接觸件244、第一CESL230、及第一ILD層232的頂表面是共平面的。
在第13圖所示的一些實施例中，下汲極接觸件244沿著X方向懸突(overhangs)在第一汲極部件228D上。在這些實施例中，下汲極接觸件244包括第一懸突部2440，其在第一汲極部件228D上懸突約2nm及約20nm。也就是說，第一懸突部2440不直接或間接地藉由矽化物層設置於第一汲極部件228D上。
在方框116的操作是可選的且可以完全被忽略。如下所述，在一些實施例中，其中導電部件延伸至第一汲極部件228D中以將第一汲極部件228D 耦合至上方的另一個汲極部件，可以不需要下汲極接觸件244並將其忽略。
參照第1、14及15圖，方法100包括方框118，其中磊晶層250接合在工件200上。在方框118的操作包括：在第一閘極結構240上沉積第一鈍化層246(顯示於第14圖)、在第二基板251上提供磊晶層250(顯示於第15圖)、在磊晶層250上沉積第二鈍化層248、以及將第二鈍化層248接合至第一鈍化層246(顯示於第15圖)。參照第14圖，在方框118，在工件200上毯覆沉積第一鈍化層246。在一個實施例中，第一鈍化層246包括氧化矽。在一些替代的實施例中，第一鈍化層246可以包括氮化矽、碳氮化矽、氮碳氧化矽、氧化鋁、或氧化鉿。如第14圖所示，可以在第一CESL230、第一ILD層232、第一閘極結構240、及第一閘極間隔層220上沉積第一鈍化層246。參照第15圖，第二基板251可以與第一基板202類似，且為了簡潔而省略其詳細描述。在一個實施例中，第一基板202與第二基板251兩者為在(100)結晶面上具有頂表面的矽基板。磊晶層250係利用氣相磊晶(VPE)、極高真空化學氣相沉積(UHV-CVD)、分子束磊晶(MBE)、及/或其他適合的製程以沉積在第二基板251上。磊晶層250是由適合作為p型裝置的通道的半導體材料所形成。在一個實施例中，磊晶層250可以包括矽鍺(SiGe)，其具有約15%及約60%之間的鍺含量。在一些替代的實施例中，磊晶層250可以包括鍺(Ge)、矽鍺(SiGe)、或二維(two-dimensional，2D)材料，例如二硫化鉬(MoS2)、二硒化鎢(WSe2)、或二碲化鉿(HfTe2)。接著在磊晶層250上沉積第二鈍化層248。在一個實施例中，第二鈍化層248包括氧化矽。在一些替代的實施例中，第二鈍化層248可以包括氮化矽、碳氮化矽、氮碳氧化矽、氧化鋁、或氧化鉿。
磊晶層250係藉由在第一鈍化層246與第二鈍化層248之間的直接 接合或熔融接合(fusion bonding)以接合至工件200。在一個範例直接接合製程中，第一鈍化層246與第二鈍化層248兩者皆使用RCA SC-1(氨、過氧化氫及水)及/或RCA SC-2(氫氯酸、過氧化氫及水)來清潔。接著在室溫下將已清潔的第一鈍化層246與第二鈍化層248配對並壓合。直接接合製程可以藉由退火製程來強化。雖然並未在第15圖明確顯示，在將第一鈍化層246與第二鈍化層248接合在一起之後，移除第二基板251以在頂表面上露出磊晶層250。此時，磊晶層250與第二鈍化層248成為工件200的一部分。
參照第1及16圖，方法100包括方框120，其中鰭片元件252係來自磊晶層250。隨著第二基板251的移除，圖案化磊晶層250以形成一或多個鰭片元件252。在半導體裝置200包括雙鰭片(dual-fin)電晶體的一些實施例中，如第16圖所示，兩鰭片元件252係形成於通道構件2080的垂直堆疊的正上方。其他配置也是可行的。為了圖案化之目的，可以在磊晶層250上沉積硬遮罩層。硬遮罩層可以是單層或多層。在一個範例中，硬遮罩層包括氧化矽層以及在氧化矽層上的氮化矽層。如第16圖所示，鰭片元件252沿著Z方向從第二鈍化層248垂直延伸且沿著Y方向縱向延伸。鰭片元件252可以利用適合的製程來圖案化，包括雙重圖案化或多重圖案化製程。一般來說，雙重圖案化或多重圖案化製程結合了微影製程與自對準製程，以創建出例如，比使用單一、直接微影製程所得的節距更小的圖案。例如，在一實施例中，在基板上方形成材料層，並使用微影製程對其進行圖案化。使用自對準製程在圖案化的材料層旁邊形成間隔物。之後去除材料層，然後可以使用剩餘的間隔物或心軸作為遮罩以藉由蝕刻磊晶層250來圖案化鰭片元件252。蝕刻製程可以包括乾蝕刻、濕蝕刻、反應離子蝕刻(RIE)、及/或其他適合的製程。
在一些實施中，鰭片元件252具有大於寬度(沿著Y方向)的高度(沿著Z方向)。在一些實施例中，鰭片元件252的高度可以在約10nm及約70nm之間，且鰭片元件252的寬度可以在約3nm及約12nm之間。當半導體裝置200包括多個鰭片元件252時，鰭片元件252包括約10nm及約50nm之間的鰭片節距。對於各個鰭片元件252，主表面為側壁。當第二基板251是由矽所形成且具有在(100)面的頂表面時，鰭片元件的主表面為(110)面，其提供了優於其他表面的電洞移動率。
參照第1、16及17圖，方法100包括方框122，其中在鰭片元件252的通道區上沉積了第二虛置閘極堆疊258。在採用了閘極替換製程(或閘極後製製程)的一些實施例中，在鰭片元件252上形成第二虛置閘極堆疊258以作為用於功能性閘極結構的佔位件。其他製程及配置也是可行的。為了形成第二虛置閘極堆疊258，在工件200上且包括在鰭片元件252上沉積虛置介電層254、虛置閘極電極層256、及閘極頂硬遮罩層(未顯示)。這些膜層的沉積可以包括使用低壓CVD(LPCVD)、CVD、電漿輔助CVD(PECVD)、PVD、ALD、熱氧化、電子束蒸鍍、或其他適合的沉積技術、或前述之組合。虛置介電層254可以包括氧化矽，虛置閘極電極層256可以包括多晶矽，且閘極頂硬遮罩層可以是包括氧化矽及氮化矽的多層。利用微影及蝕刻製程，圖案化了閘極頂硬遮罩層。微影製程可以包括光阻塗佈(例如，旋轉塗佈)、軟烤、遮罩對準、曝光、曝光後烘烤、光阻顯影、沖洗、乾燥(例如，旋轉乾燥(spin-drying)及/或硬烤(hard baking))、其他適合的微影技術、及/或前述之組合。蝕刻製程可以包括乾蝕刻(例如，RIE蝕刻)、濕蝕刻、及/或其他蝕刻方法。之後，將圖案化的閘極頂硬遮罩用作蝕刻遮罩，接著蝕刻虛置介電層254及虛置閘極電極層256以形成第 二虛置閘極堆疊258。如第16圖所示，第二虛置閘極堆疊258包覆在鰭片元件252上且設置於第二鈍化層248上。參照第17圖，在第二虛置閘極堆疊258下方的部分的鰭片元件252為第二通道區252C。第二通道區252C與第二虛置閘極堆疊258也定義了第二源極區252S與第二汲極區252D，且第二源極區252S與第二汲極區252D並未被第二虛置閘極堆疊258垂直重疊。第二通道區252C係沿著Y方向設置或夾在第二源極區252S與第二汲極區252D之間。
如第17圖所示，在方框122的操作可以包括在第二虛置閘極堆疊258的側壁上形成第二閘極間隔層260。在一些實施例中，第二閘極間隔層260的形成包括在工件200上順應性地沉積一或多個介電層。在一個範例製程中，上述一或多個介電層是利用CVD、SACVD、或ALD來沉積。上述一或多個介電層可以包括氧化矽、氮化矽、碳化矽、氮氧化矽、碳氮化矽、碳氧化矽、氮碳氧化矽、及/或前述之組合。
在第17圖所表示的一些實施例中，第二通道區252C位於第一通道區210C的正上方，第二源極區252S位於第一源極區210S的正上方，且第二汲極區252D位於第一汲極區210D的正上方。換句話說，沿著Z方向，第二通道區252C可以實質上與第一通道區210C重疊，第二源極區252S可以實質上與第一源極區210S重疊，且第二汲極區252D可以實質上與第一汲極區210D重疊。
參照第1及17圖，方法100包括方框124，其中凹蝕了鰭片元件252的源極/汲極區已形成第二源極凹槽262S與第二汲極凹槽262D。在一個範例製程中，在沉積第二閘極間隔層260之後，在選擇性凹蝕鰭片元件252的第二源極區252S與第二汲極區252D的蝕刻製程中蝕刻工件200。第二源極區252S與第二汲極區252D的選擇性凹蝕可形成第二源極凹槽262S與第二汲極凹槽262D。在方框 124的蝕刻製程可以是乾蝕刻製程或適合的蝕刻製程。在一個範例乾蝕刻製程中，可以使用含氧氣體、氫氣、含氟氣體(例如，CF4、SF6、CH2F2、CHF3、及/或C2F6)、含氯氣體(例如，Cl2、CHCl3、CCl4、及/或BCl3)、含溴氣體(例如，HBr及/或CHBr3)、含碘氣體、其他適合的氣體及/或電漿、及/或前述之組合。如第17圖所示，在第二源極區252S與第二汲極區252D中的第二鈍化層248在第二源極凹槽262S與第二汲極凹槽262D中露出。
參照第1及18圖，方法100包括方框126，其中形成了第二源極部件264S與第二汲極部件264D。在一些實施例中，第二源極部件264S與第二汲極部件264D可以利用磊晶製程來形成，例如VPE、UHV-CVD、MBE、及/或其他適合的製程。磊晶成長製程可以使用氣體及/或液體前驅物，其與鰭片元件252的成分起交互作用。因此第二源極部件264S與第二汲極部件264D耦合至鰭片元件252。在一些實施例中，第二源極部件264S與第二汲極部件264D可以是p型源極/汲極部件。範例p型源極/汲極部件可以包括Si、Ge、AlGaAs、SiGe、或其他適合的材料，且可以藉由在磊晶製程時引入p型摻質來原位摻雜，上述p型摻質為例如硼(B)，或是利用佈植製程(即，接面佈植製程)來非原位摻雜。在一個實施例中，第二源極部件264S與第二汲極部件264D包括硼摻雜矽鍺(boron-doped silicon germanium，SiGe：B)。
參照第1、19、20、21及22圖，方法100包括方框128，其中第二虛置閘極堆疊258被第二閘極結構274取代。在方框128的操作包括：沉積第二接觸蝕刻停止層(CESL)266(顯示於第19圖)、沉積第二層間介電(ILD)層268(顯示於第19圖)、移除第二虛置閘極堆疊258(顯示於第20圖)、沉積第二閘極介電層270(顯示於第20圖)、露出第一閘極結構240(顯示於第21圖)、沉 積第二閘極電極層272(顯示於第22圖)、以及平坦化工件200以移除過量的材料(顯示於第22圖)。第二CESL266可以包括氮化矽、氮氧化矽、及/或其他本領域中已知的材料，且可以藉由ALD、電漿輔助化學氣相沉積(PECVD)製程及/或其他適合的沉積或氧化製程來形成。如第19圖所示，第二CESL266可以被沉積在第二源極部件264S與第二汲極部件264D的頂表面上。之後，在第二CESL266上沉積第二ILD層268。就像是第一ILD層232，第二ILD層268可以包括例如正矽酸乙脂(TEOS)氧化物、未摻雜的矽酸鹽玻璃、或摻雜的氧化矽，例如硼磷矽酸鹽玻璃(BPSG)、熔融石英玻璃(FSG)、磷矽酸鹽玻璃(PSG)、硼摻雜矽玻璃(BSG)、及/或其他適合的介電材料。第二ILD層268可以藉由PECVD製程或其他適合的沉積技術來沉積。在一些實施例中，在形成第二ILD層268之後，可以退火工件200以改善第二ILD層268的完整性。為了移除過量的材料並且露出第二虛置閘極堆疊258的頂表面，可以進行例如化學機械研磨(CMP)製程的平坦化製程。
參照第20圖，隨著第二虛置閘極堆疊258的露出，繼續方框128以移除第二虛置閘極堆疊258。第二虛置閘極堆疊258的移除可以包括對第二虛置閘極堆疊258的材料具有選擇性的一或多個蝕刻製程，舉例而言，可以利用選擇性濕蝕刻、選擇性乾蝕刻、或前述之組合以進行第二虛置閘極堆疊258的移除。在移除第二虛置閘極堆疊258之後，在鰭片元件252的第二通道區252C上沉積第二閘極介電層270。第二閘極介電層270可以包括界面層與高介電常數介電層。在一些實施例中，界面層包括氧化矽且可以在預清潔製程中形成。一個範例預清潔製程可以包括使用RCA SC-1(氨、過氧化氫及水)及/或RCA SC-2(氫氯酸、過氧化氫及水)。接著利用ALD、CVD、及/或其他適合的方法在界面層上 沉積高介電常數介電層。高介電常數層介電層可以包括氧化鉿。替代地，高介電常數介電層可以包括其他高介電常數介電質，例如氧化鈦(TiO2)、氧化鉿鋯(HfZrO)、氧化鉭(Ta2O5)、氧化鉿矽(HfSiO4)、氧化鋯(ZrO2)、氧化鋯矽(ZrSiO2)、氧化鑭(La2O3)、氧化鋁(Al2O3)、氧化鋯(ZrO)、氧化釔(Y2O3)、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、氧化鉿鑭(HfLaO)、氧化鑭矽(LaSiO)、氧化鋁矽(AlSiO)、氧化鉿鉭(HfTaO)、氧化鉿鈦(HfTiO)、(Ba,Sr)TiO3(BST)、氮化矽(SiN)、氮氧化矽(SiON)、前述之組合、或其他適合的材料。
參照第21圖，在第二閘極介電層270的沉積之後，對工件200進行非等向性蝕刻製程以移除並未被鰭片元件252重疊的第二鈍化層248與第一鈍化層246，直到第一閘極結構240在鰭片元件252之間露出。如第21圖所示，在鰭片元件252下方的部分的第二鈍化層248與第一鈍化層246可以實質上未被蝕刻且留在原位。一部分的第二閘極介電層270設置於留下的第二鈍化層248上。之後，如第22圖所示，第二閘極電極層272係利用ALD、PVD、CVD、電子束蒸鍍、或其他適合的方法設置於第二閘極介電層270、第一閘極結構240及鰭片元件252上。第二閘極電極層272可以包括單層或替代地包括多層結構，例如具有選定的功函數以增進裝置效能之金屬層(功函數金屬層)、襯層、潤濕層、黏著層、金屬合金或金屬矽化物的各種組合。舉例來說，第二閘極電極層272可以包括氮化鈦(TiN)、鈦鋁(TiAl)、氮化鈦鋁(TiAlN)、氮化鉭(TaN)、鉭鋁(TaAl)、氮化鉭鋁(TaAlN)、碳化鉭鋁(TaAlC)、碳氮化鉭(TaCN)、鋁(Al)、鎢(W)、鎳(Ni)、鈦(Ti)、釕(Ru)、鈷(Co)、鉑(Pt)、碳化鉭(TaC)、氮化鉭矽(TaSiN)、銅(Cu)、其他耐火金屬、或其他適合的金屬材料、或前 述之組合。如第22圖所示，第二閘極介電層270與第二閘極電極層272共同構成第二閘極結構274。因為第二閘極電極層272與第一閘極電極層238直接接觸，在方框128的操作將第二閘極結構274電性耦合至第一閘極結構240。
參照第1、23~25、32、33、38、及39圖，方法100包括方框130，其中形成了上源極接觸件280與上汲極接觸件282。在第23圖所示的一個範例製程中，使用微影製程以形成露出第二源極部件264S與第二汲極部件264D的接觸件開口。為了降低接觸電阻，藉由在第二源極部件264S與第二汲極部件264D上沉積金屬層並進行退火製程以在金屬層與第二源極部件264S及第二汲極部件264D之間導致矽化，可以在第二源極部件264S與第二汲極部件264D上形成矽化物層281。適合的金屬層可以包括鈦(Ti)、鉭(Ta)、鎳(Ni)、鈷(Co)、或鎢(W)。矽化物層281可以包括矽化鈦(TiSi)、氮化鈦矽(TiSiN)、矽化鉭(TaSi)、矽化鎢(WSi)、矽化鈷(CoSi)、或矽化鎳(NiSi)。在形成矽化物層281之後，可以將金屬填充層沉積至接觸件開口中。金屬填充層可以包括氮化鈦(TiN)、鈦(Ti)、釕(Ru)、鎳(Ni)、鈷(Co)、銅(Cu)、鉬(Mo)、鎢(W)、鉭(Ta)、或氮化鉭(TaN)。接著可以進行平坦化製程以移除過量的材料，藉此在第二源極部件264S上形成上源極接觸件280且在第二汲極部件264D上形成上汲極接觸件282。因為上述平坦化製程，上源極接觸件280、上汲極接觸件282、第二CESL266、及第二ILD層268的頂表面是共平面的。
在第24圖所示的一些實施例中，上源極接觸件280設置於第二源極部件264S上且不懸突在第二源極部件264S上。相對地，如第25圖所示，上汲極接觸件282沿著X方向懸突在第二汲極部件264D上。上汲極接觸件282包括在第二汲極部件264D上懸突約2nm及約20nm之間的第二懸突部2820。在一些實施 例中，第二懸突部2820設置於第一懸突部的正上方，且這樣的配置允許形成第一導電部件284以耦合下汲極接觸件244與上汲極接觸件282。在一些實施中，在第二汲極部件264D上形成接觸件開口之後，將導孔開口形成為穿過第二ILD層268、第二鈍化層248、及第一鈍化層246以露出下汲極接觸件244。在將金屬填充層沉積至接觸件開口中之前，可以以由下而上(bottom-up)的方式沉積第一導電部件284。一個範例的由下而上的沉積可以包括使用金屬有機前驅物，其可以優先沉積在金屬表面上。如第25圖所示，第一導電部件284可以鄰近第二汲極部件264D的側壁延伸。第一導電部件284可以與第二汲極部件264D接觸，但不垂直貫穿第二汲極部件264D。
在第32及33圖所繪示的一些替代的實施例中，替代的下汲極接觸件244’不懸突在第一汲極部件228D上，且替代的上汲極接觸件282’不懸突在第二汲極部件264D上。用於替代的上汲極接觸件282’的接觸件開口進一步包括延伸穿過第二汲極部件264D、第二鈍化層248、及第一鈍化層246以露出替代的下汲極接觸件244’的第一導孔接觸件開口302。在這些替代的實施例中，當金屬填充層被沉積至接觸件開口與第一導孔接觸件開口302中時，與上源極接觸件280一起形成第二導電部件306。在一些實施例中，可以在上源極接觸件280與第二汲極部件264D之間設置矽化物層304，也可以在第二導電部件306與第二汲極部件264D之間設置矽化物層304。矽化物層304的成分與形成可以與矽化物層242類似。矽化物層304不在第二導電部件306與第二鈍化層248之間形成，也不在第二導電部件306與第一鈍化層246之間形成。第二導電部件306垂直延伸穿過第二汲極部件264D、第二鈍化層248、及第一鈍化層246。
在第32及33圖所繪示的一些替代的實施例中，替代的下汲極接觸 件244’不懸突在第一汲極部件228D上，且替代的上汲極接觸件282’不懸突在第二汲極部件264D上。用於替代的上汲極接觸件282’的接觸件開口進一步包括延伸穿過第二汲極部件264D、第二鈍化層248、及第一鈍化層246以露出替代的下汲極接觸件244’的第一導孔接觸件開口302。在這些替代的實施例中，當金屬填充層被沉積至接觸件開口與第一導孔接觸件開口302中時，與替代的上汲極接觸件282’一起形成第二導電部件306。在一些實施例中，可以在替代的上汲極接觸件282’與第二汲極部件264D之間設置矽化物層304，也可以在第二導電部件306與第二汲極部件264D之間設置矽化物層304。矽化物層304的成分與形成可以與矽化物層242類似。矽化物層304不在第二導電部件306與第二鈍化層248之間形成，也不在第二導電部件306與第一鈍化層246之間形成。第二導電部件306垂直延伸穿過第二汲極部件264D、第二鈍化層248、及第一鈍化層246。
在第38及39圖所繪示的一些進一步的替代的實施例中，省略下汲極接觸件244且替代的上汲極接觸件282’不懸突在第二汲極部件264D上。替代地，用於替代的上汲極接觸件282’的接觸件開口進一步包括第二導孔接觸件開口332，其延伸穿過第二汲極部件264D、第二鈍化層248、第一鈍化層246、第一ILD層232、第一CESL230、及第一汲極部件228D。在這些替代的實施例中，當金屬填充層被沉積至接觸件開口及第二導孔開口322中時，與替代的上汲極接觸件282’一起形成第三導電部件336。在一些實施例中，可以在替代的上汲極接觸件282’與第二汲極部件264D之間設置矽化物層334，也可以在第三導電部件336與第二汲極部件264D之間設置矽化物層334。此外，在第三導電部件336與第一汲極部件228D之間形成矽化物層338。矽化物層334及338的成分及形成可以與矽化物層242類似。第三導電部件336垂直延伸穿過第二汲極部件264D、第二鈍化層 248、第一鈍化層246、第一ILD層232、第一CESL230。第三導電部件336可以與第一基板202接觸或者不接觸。
在形成上源極接觸件280與上汲極接觸件282(或替代的上汲極接觸件282’)之後，可以在工件200上形成內連線結構275。雖然並未明確顯示於圖式中，內連線結構275可以包括複數個內連線層，各個內連線層包括埋置於介電層中的導電線路及導電導孔。介電層可以被稱為金屬間層(intermetal layer，IMD)，且可以包括的材料為例如正矽酸乙脂(TEOS)氧化物、未摻雜的矽酸鹽玻璃、或摻雜的氧化矽，例如硼磷矽酸鹽玻璃(BPSG)、熔融石英玻璃(FSG)、磷矽酸鹽玻璃(PSG)、硼摻雜矽玻璃(BSG)、及/或其他適合的介電材料。參照第23、23、及25圖，在內連線結構275上沉積第三鈍化層276以促進工件200與其他結構的接合。在一個實施例中，第三鈍化層276包括氧化矽。在一些替代的實施例中，第三鈍化層276可以包括氮化矽、碳氮化矽、氮碳氧化矽、氧化鋁、或氧化鉿。
參照第1、26~31、及34~37圖，方法100包括方框132，其中形成了背側源極接觸件296以耦合至第一源極部件228S。在方框134的操作可以包括：在承載基板288上沉積第四鈍化層286(顯示於第26圖)、將第四鈍化層286接合至第三鈍化層276(顯示於第26圖)、翻轉工件200使第一基板202向上(顯示於第27圖)、移除一部分的第一基板202、以及在第一源極部件228S上形成背側源極接觸件296(顯示於第28圖)。承載基板288可以包括矽或碳化矽。在一個實施例中，第四鈍化層286包括氧化矽。在一些替代的實施例中，第四鈍化層286可以包括氮化矽、碳氮化矽、氮碳氧化矽、氧化鋁、或氧化鉿。可以利用CVD或適合的沉積製程在承載基板288上沉積第四鈍化層286。承載基板288係藉由在 第三鈍化層276與第四鈍化層286之間的直接接合以接合至工件200。以上描述了一個範例直接接合製程且在此將不重複。在將承載基板288接合至工件200之後，翻轉工件200使第一基板向上，如第27圖所示。藉由研磨(grinding)製程及/或化學機械研磨(CMP)製程研磨及/或平坦化第一基板202直到隔離部件212、第一源極部件228S、及第一汲極部件228D在頂表面上露出。
參照第28圖，在露出的隔離部件212、第一源極部件228S、及第一汲極部件228D上沉積背側接觸蝕刻停止層(backside contact etch stop layer，BCESL)290。就像是第一CESL230與第二CESL266，BCESL290可以包括氮化矽、氮氧化矽、及/或本領域中已知的其他材料，且可以藉由ALD、電漿輔助化學氣相沉積(PECVD)製程及/或其他適合的沉積或氧化製程來形成。之後，在BCESL290上沉積背側介電層292。背側介電層292可以包括的材料為例如正矽酸乙脂(TEOS)氧化物、未摻雜的矽酸鹽玻璃、或摻雜的氧化矽，例如硼磷矽酸鹽玻璃(BPSG)、熔融石英玻璃(FSG)、磷矽酸鹽玻璃(PSG)、硼摻雜矽玻璃(BSG)、及/或其他適合的介電材料。背側介電層292可以藉由PECVD製程或其他適合的沉積技術來沉積。
繼續參照第28圖。為了形成背側源極接觸件296，形成背側接觸件開口以露出第一源極部件228S。背側矽化物層294與背側源極接觸件296形成於背側接觸件開口中。背側矽化物層294可以包括矽化鈦(TiSi)、氮化鈦矽(TiSiN)、矽化鉭(TaSi)、矽化鎢(WSi)、矽化鈷(CoSi)、或矽化鎳(NiSi)。背側源極接觸件296可以包括氮化鈦(TiN)、鈦(Ti)、釕(Ru)、鎳(Ni)、鈷(Co)、銅(Cu)、鉬(Mo)、鎢(W)、鉭(Ta)、或氮化鉭(TaN)。根據本揭露的一些實施例，第29及30圖繪示出工件200已上下翻轉之第二源極區 252S與第二汲極區252D的部分剖面圖。
背側源極接觸件296的替代的實施例顯示於第34~37圖中。在第34及35圖所繪示的第一替代實施例中，可以在形成背側接觸件開口之後形成第一導通孔開口312，且在第一導通孔開口312中沉積第四導電部件314。如第34及35圖所示，第一導通孔開口312及第四導電部件314延伸穿過第一源極部件228S、第一CESL230、第一ILD層232、第一鈍化層246、第二鈍化層248、第二源極部件264S、及矽化物層281以耦合至上源極接觸件280。在第35圖所表示的一些實施中，可以在第四導電部件314與第一源極部件228S之間形成矽化物層316，且可以在第四導電部件314與第二源極部件264S之間形成矽化物層318。矽化物層316及318的成分可以與矽化物層242類似，且為了簡潔起見而省略其詳細描述。類似地，第四導電部件314與背側源極接觸件296在材料上類似，且也為了簡潔起見而省略其詳細描述。
在第36及37圖所繪示的第二替代實施例中，可以在形成背側接觸件開口之後形成第二導孔開口322，且在第二導孔開口322中沉積第五導電部件324。與第34及35圖所示的第一替代實施例不同，省略了上源極接觸件280。如第36及37圖所示，第二導孔開口322及第五導電部件324延伸穿過第一源極部件228S、第一CESL230、第一ILD層232、第一鈍化層246、及第二鈍化層248以耦合至第二源極部件264S。在第37圖所表示的一些實施中，可以在第五導電部件324與第一源極部件228S之間形成矽化物層326，且可以在第五導電部件324與第二源極部件264S之間形成矽化物層328。矽化物層326及328的成分可以與矽化物層242類似，且也為了簡潔起見而省略其詳細描述。類似地，第五導電部件324與背側源極接觸件296在材料上類似，且也為了簡潔起見而省略其詳細描述。
參照第1圖，方法100包括方框134，其中進行了進一步的製程。這樣的進一步的製程可以包括在背側源極接觸件296上沉積第三ILD層以及在第三ILD層中形成背側電源軌。
參照第31圖。在方法100的操作結束時，半導體裝置200包括作為底電晶體的n型MBC電晶體1000以及作為頂部裝置的p型FinFET2000。在第31圖中，p型FinFET2000設置於n型MBC電晶體1000上。n型MBC電晶體1000包括沿著Z方向垂直堆疊的複數個通道構件2080。沿著Y方向，通道構件2080在第一源極部件228S與第一汲極部件228D之間延伸。第一閘極結構240包繞各個通道構件2080。p型FinFET2000包括一或多個鰭片元件252(一個顯示於第31圖中)，其從第二鈍化層248升起。沿著Y方向，鰭片元件252在第二源極部件264S與第二汲極部件264D之間延伸。第二閘極結構274包覆在鰭片元件252上。n型MBC電晶體1000的第一源極部件228S與p型FinFET2000的第二源極部件264S沿著Z方向對準。n型MBC電晶體1000的第一汲極部件228D與p型FinFET2000的第二汲極部件264D沿著Z方向對準。上述垂直對準定向(orientation)允許將導電部件形成為電性耦合第一源極部件228S與第二源極部件264S，或電性耦合第一汲極部件228D與第二汲極部件264D。
在第二基板251為具有(100)面的矽基板的實施例中，第31圖中的半導體裝置200改善了p型FinFET2000的電洞移動率。在這些實施例中，沉積在第二基板251上的磊晶層250遵循第二基板251的結晶方位。當磊晶層250被圖案化以形成鰭片元件252時，鰭片元件252的側壁在(110)面上，其中(110)面提供了比(100)面大的電洞移動率。因為鰭片元件252的側壁為鰭片元件252的主表面，鰭片元件252具有改善的電洞移動率，且p型FinFET2000具有改善的 驅動電流。
雖然本揭露的大部分描述了用於第31圖所示的半導體裝置200的製程及結構，本揭露的實施例並非限定於包括n型MBC上的p-FinFET的實施例。第40圖繪示了半導體裝置400中的替代的配置。與第31圖的半導體裝置200不同，半導體裝置400包括作為底電晶體的p型FinFET2000以及作為頂部裝置的n型MBC電晶體1000。也就是說，在半導體裝置400中，在p型FinFET2000上設置n型MBC電晶體1000。因為此時p型FinFET2000是底電晶體，省略了上源極接觸件280，且藉由矽化物層以將替代的源極接觸件245形成為耦合至第一源極部件228S。因為替代的源極接觸件245與下汲極接觸件244類似，為了簡潔起見而省略了替代的源極接觸件245的詳細描述。與第31圖的半導體裝置200類似，n型MBC電晶體1000的第一汲極部件228D以及p型FinFET2000的第二汲極部件264D沿著Z方向對準。上述垂直對準定向允許將導電部件形成為電性耦合第一源極部件228S與第二源極部件264S，或電性耦合第一汲極部件228D與第二汲極部件264D。在半導體裝置200與替代的半導體裝置400兩者中，在第二鈍化層248上設置鰭片元件252以提供較佳的閘極控制。
在一個例示性的面向中，本揭露係針對一種半導體裝置。半導體裝置包括第一電晶體及設置於第一電晶體上的第二電晶體。第一電晶體包括彼此垂直堆疊的複數個通道構件，且第一源極/汲極部件鄰接複數個通道構件。第二電晶體包括鰭片結構、以及鄰接鰭片結構的第二源極/汲極部件。半導體裝置更包括電性連接第一源極/汲極部件與第二源極/汲極部件的導電部件。
在一些實施例中，第一電晶體更包括第一閘極結構，其包繞各個通道構件。第二電晶體更包括第二閘極結構，其包覆於鰭片結構上。第一閘極 結構與第二閘極結構接觸。在一些實施例中，複數個通道構件包括矽(Si)，且鰭片結構包括矽鍺(SiGe)。在一些實施中，複數個通道構件包括矽(Si)、鍺(Ge)、矽鍺(SiGe)、二硫化鉬(MoS2)、二硒化鎢(WSe2)、或二碲化鉿(HfTe2)，且鰭片結構包括矽(Si)、鍺(Ge)、矽鍺(SiGe)、二硫化鉬(MoS2)、二硒化鎢(WSe2)、或二碲化鉿(HfTe2)。在一些實例中，導電部件延伸穿過第二源極/汲極部件。在一些實施例中，導電部件延伸穿過第一源極/汲極部件。在一些實例中，第一電晶體更包括第一源極/汲極接觸件，其設置於第一源極/汲極部件上，第二電晶體更包括第二源極/汲極接觸件，其設置於第二源極/汲極部件上，且導電部件與第一源極/汲極接觸件及第二源極/汲極接觸件直接接觸。在一些實施例中，第一電晶體更包括第三源極/汲極接觸件，其設置於第一源極/汲極部件下方，第二電晶體更包括第四源極/汲極接觸件，其設置於第二源極/汲極部件上，且導電部件與第三源極/汲極接觸件及第四源極/汲極接觸件直接接觸。
在另一個例示性的面向中，本揭露係針對一種半導體裝置。半導體裝置包括第一電晶體及在第一電晶體上的第二電晶體。第一電晶體包括第一源極部件及第一汲極部件，且複數個通道構件彼此垂直堆疊且在第一源極部件與第一汲極部件之間延伸。第二電晶體包括第二源極部件及第二汲極部件，且鰭片結構在第二源極部件與第二汲極部件之間延伸。第二源極部件位於第一源極部件正上方，且第二汲極部件位於第一汲極部件正上方。
在一些實施例中，第一電晶體更包括設置於第一汲極部件上的第一汲極接觸件，且第二電晶體更包括設置於第二汲極部件上的第二汲極接觸件。在一些實施中，第一汲極部件包括以n型摻質摻雜的矽，第二汲極部件包括以p型摻質摻雜的矽鍺，且第一汲極接觸件與第二汲極接觸件包括金屬。在一些 實施中，第一汲極接觸件懸突在第一汲極部件上，且第二汲極接觸件懸突在第二汲極部件上。在一些實施例中，半導體裝置可以更包括第一導電部件，其電性耦合第一汲極接觸件與第二汲極接觸件。在一些實例中，第一導電部件延伸穿過第二汲極部件。在一些實施中，第一電晶體可以更包括第一源極接觸件，其設置於第一汲極部件下方，且第二電晶體可以更包括第二源極接觸件，其設置於第二汲極部件上。
在又另一個例示性的面向中，本揭露係針對一種半導體裝置的形成方法。上述方法包括在第一基板上形成第一電晶體，其中第一電晶體包括第一源極部件與第一汲極部件、彼此垂直堆疊且在第一源極部件與第一汲極部件之間延伸的複數個通道構件、以及包繞各個通道構件的第一閘極結構。上述方法可以更包括在第一電晶體上沉積第一鈍化層、在第二基板上形成磊晶層、在磊晶層上沉積第二鈍化層、將第二鈍化層接合至第一鈍化層、在接合之後移除第二基板、以及形成第二閘極結構以包覆在鰭片結構上，其中第二閘極結構與第一閘極結構接觸。
在一些實施例中，磊晶層包括矽鍺。在一些實施中，上述方法可以更包括在形成第二閘極結構之前在鰭片結構的通道區上形成虛置閘極堆疊、凹蝕鰭片結構的通道區及汲極區以形成源極凹槽與汲極凹槽且源極區與汲極區夾住通道區、在源極凹槽中形成第二源極部件且在汲極凹槽中形成第二汲極部件、在第二源極部件與第二汲極部件上沉積介電層、以及移除虛置閘極堆疊。在一些實例中，上述方法可以更包括：在形成第二閘極結構之後，形成穿過第二汲極部件與第一汲極部件的汲極接觸件開口，且在汲極接觸件開口中形成導電部件。在一些實例中，上述方法可以更包括：在形成第二閘極結構之後，在 第二閘極結構上沉積第三鈍化層、在第三基板上沉積第四鈍化層、將第四鈍化層接合至第三鈍化層、移除第一基板、以及形成電性耦合至第一源極部件的背側源極接觸件。
以上概述數個實施例之特徵，以使本發明所屬技術領域中具有通常知識者可更易理解本發明實施例的觀點。本發明所屬技術領域中具有通常知識者應理解，可輕易地以本發明實施例為基礎，設計或修改其他製程和結構，以達到與在此介紹的實施例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應理解到，此類等效的製程和結構並無悖離本發明的精神與範圍，且可在不違背後附之請求項之精神和範圍之下，做各式各樣的改變、取代和替換。
200:工件(半導體裝置)
202:第一基板
228D:第一汲極部件
230:第一接觸蝕刻停止層(第一CESL)
232:第一層間介電層(第一ILD層)
242:矽化物層
244:下汲極接觸件
246:第一鈍化層
248:第二鈍化層
252D:第二汲極區
264D:第二汲極部件
266:第二接觸蝕刻停止層(第二CESL)
268:第二層間介電層(第二ILD層)
275:內連線結構
276:第三鈍化層
282:上汲極接觸件
284:第一導電部件
2440:第一懸突部
2820:第二懸突部
X,Y,Z:方向

Claims (15)

  1. 一種半導體裝置，包括：一第一電晶體，包括：複數個通道構件，彼此垂直堆疊；以及一第一源極/汲極部件，鄰接(adjoining)該些通道構件；一第二電晶體，設置於該第一電晶體上，該第二電晶體包括：一鰭片結構；以及一第二源極/汲極部件，鄰接該鰭片結構；一導電部件，電性連接該第一源極/汲極部件與該第二源極/汲極部件；以及至少一鈍化層，從該些複數個通道構件與該鰭片結構之間連續延伸到該第一源極/汲極部件與該第二源極/汲極部件之間，其中整個該至少一鈍化層設置於該鰭片結構下方。
  2. 如請求項1之半導體裝置，其中該第一電晶體更包括一第一閘極結構，該第一閘極結構包繞(wraps around)各個通道構件，其中該第二電晶體更包括一第二閘極結構，該第二閘極結構包覆(wraps over)在該鰭片結構上，其中該第一閘極結構與該第二閘極結構接觸。
  3. 如請求項1或2之半導體裝置，其中該導電部件延伸穿過該第二源極/汲極部件。
  4. 如請求項3之半導體裝置，其中該導電部件延伸穿過該第一源極/汲極部件。
  5. 如請求項1或2之半導體裝置，其中該第一電晶體更包括一第一源極/汲極接觸件，該第一源極/汲極接觸件設置於該第一源極/汲極部件上，其中該第二電晶體更包括一第二源極/汲極接觸件，該第二源極/汲極接觸件設置於該第二源極/汲極部件上，其中該導電部件與該第一源極/汲極接觸件及該第二源極/汲極接觸件直接接觸。
  6. 如請求項1或2之半導體裝置，其中該第一電晶體更包括一第三源極/汲極接觸件，該第三源極/汲極接觸件設置於該第一源極/汲極部件下方，其中該第二電晶體更包括一第四源極/汲極接觸件，該第四源極/汲極接觸件設置於該第二源極/汲極部件上，其中該導電部件與該第三源極/汲極接觸件及該第四源極/汲極接觸件直接接觸。
  7. 一種半導體裝置，包括：一第一電晶體，包括：一第一源極部件及一第一汲極部件；以及複數個通道構件，彼此垂直堆疊且在該第一源極部件與該第一汲極部件之間延伸；以及一第二電晶體，設置於該第一電晶體上，該第二電晶體包括：一第二源極部件及一第二汲極部件；以及一鰭片結構，在該第二源極部件與該第二汲極部件之間延伸， 其中該第二源極部件位於該第一源極部件正上方，其中該第二汲極部件位於該第一汲極部件正上方。
  8. 如請求項7之半導體裝置，其中該第一電晶體更包括一第一汲極接觸件，該第一汲極接觸件設置於該第一汲極部件上，其中該第二電晶體更包括一第二汲極接觸件，該第二汲極接觸件設置於該第二汲極部件上。
  9. 如請求項8之半導體裝置，其中該第一汲極接觸件懸突(overhangs)在該第一汲極部件上，其中該第二汲極接觸件懸突在該第二汲極部件上。
  10. 如請求項8或9之半導體裝置，更包括一第一導電部件，該第一導電部件電性耦合該第一汲極接觸件與該第二汲極接觸件。
  11. 如請求項10之半導體裝置，其中該第一導電部件延伸穿過該第二汲極部件。
  12. 一種半導體裝置的形成方法，包括：在一第一基板上形成一第一電晶體，其中該第一電晶體包括：一第一源極部件及一第一汲極部件；複數個通道構件，彼此垂直堆疊且在該第一源極部件與該第一汲極部件之間延伸；以及一第一閘極結構，該第一閘極結構包繞各個通道構件；在該第一電晶體上沉積一第一鈍化層；在一第二基板上形成一磊晶層； 在該磊晶層上沉積一第二鈍化層；將該第二鈍化層接合至該第一鈍化層；在該接合之後，移除該第二基板；圖案化該磊晶層以在該些通道構件上形成一鰭片結構；以及形成一第二閘極結構以包覆在該鰭片結構上，其中該第二閘極結構與該第一閘極結構接觸，其中整個該第一鈍化層及該第二鈍化層設置於該鰭片結構下方。
  13. 如請求項12之半導體裝置的形成方法，更包括：在形成該第二閘極結構之前，在該鰭片結構的一通道區上形成一虛置閘極堆疊；凹蝕該鰭片結構的一源極區及一汲極區以形成一源極凹槽及一汲極凹槽，該源極區及該汲極區夾住該通道區；在該源極凹槽中形成一第二源極部件，且在該汲極凹槽中形成一第二汲極部件；在該第二源極部件與該第二汲極部件上沉積一介電層；以及移除該虛置閘極堆疊。
  14. 如請求項13之半導體裝置的形成方法，更包括：在形成該第二閘極結構之後，形成穿過該第二汲極部件與該第一汲極部件的一汲極接觸件開口；以及在該汲極接觸件開口中形成一導電部件。
  15. 如請求項13或14之半導體裝置的形成方法，更包括：在形成該第二閘極結構之後，在該第二閘極結構上沉積一第三鈍化層； 在一第三基板上沉積一第四鈍化層；將該第四鈍化層接合至該第三鈍化層；移除該第一基板；以及形成電性耦合至該第一源極部件的一背側源極接觸件。
TW110127319A 2020-07-30 2021-07-26 半導體裝置及其形成方法 TWI815151B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US202063059011P 2020-07-30 2020-07-30
US63/059,011 2020-07-30
US17/094,904 US11735669B2 (en) 2020-07-30 2020-11-11 Vertically-oriented complementary transistor
US17/094,904 2020-11-11

Publications (2)

Publication Number Publication Date
TW202205449A TW202205449A (zh) 2022-02-01
TWI815151B true TWI815151B (zh) 2023-09-11

Family

ID=77411535

Family Applications (1)

Application Number Title Priority Date Filing Date
TW110127319A TWI815151B (zh) 2020-07-30 2021-07-26 半導體裝置及其形成方法

Country Status (7)

Country Link
US (2) US11735669B2 (zh)
EP (1) EP3945560A1 (zh)
JP (1) JP2022027654A (zh)
KR (1) KR102495803B1 (zh)
CN (1) CN113675194A (zh)
DE (1) DE102020130964A1 (zh)
TW (1) TWI815151B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210081679A (ko) * 2019-12-24 2021-07-02 삼성전자주식회사 반도체 장치
EP4199056A1 (en) * 2021-12-15 2023-06-21 IMEC vzw Vertically stacked transistor structures
US20230197800A1 (en) * 2021-12-20 2023-06-22 Intel Corporation Non-reactive epi contact for stacked transistors
US20230197569A1 (en) * 2021-12-20 2023-06-22 Intel Corporation Frontside and backside epi contact
EP4283663A1 (en) * 2022-05-24 2023-11-29 Imec VZW A method for forming a stacked transistor device
US20230411397A1 (en) * 2022-06-16 2023-12-21 International Business Machines Corporation Method and structure of forming sidewall contact for stacked fet

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201923908A (zh) * 2017-11-15 2019-06-16 台灣積體電路製造股份有限公司 鰭式場效電晶體裝置結構的製造方法
US20190319095A1 (en) * 2017-11-02 2019-10-17 International Business Machines Corporation Vertically stacked nfets and pfets with gate-all-around structure
US20200006331A1 (en) * 2018-06-29 2020-01-02 Intel Corporation Techniques for forming gate structures for transistors arranged in a stacked configuration on a single fin structure
US20200006330A1 (en) * 2018-06-29 2020-01-02 Intel Corporation Leave-behind protective layer having secondary purpose

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7214991B2 (en) * 2002-12-06 2007-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. CMOS inverters configured using multiple-gate transistors
US11923374B2 (en) * 2013-03-12 2024-03-05 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US10199502B2 (en) 2014-08-15 2019-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. Structure of S/D contact and method of making same
US9818872B2 (en) 2015-06-30 2017-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
US9899387B2 (en) 2015-11-16 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
US10032627B2 (en) 2015-11-16 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming stacked nanowire transistors
US9754840B2 (en) 2015-11-16 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Horizontal gate-all-around device having wrapped-around source and drain
US9887269B2 (en) 2015-11-30 2018-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
US9899269B2 (en) 2015-12-30 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd Multi-gate device and method of fabrication thereof
US10164032B2 (en) * 2016-06-17 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned contact and manufacturing method thereof
US9899398B1 (en) 2016-07-26 2018-02-20 Taiwan Semiconductor Manufacturing Co., Ltd. Non-volatile memory device having nanocrystal floating gate and method of fabricating same
US9711501B1 (en) 2016-09-26 2017-07-18 International Business Machines Corporation Interlayer via
US10290546B2 (en) 2016-11-29 2019-05-14 Taiwan Semiconductor Manufacturing Co., Ltd. Threshold voltage adjustment for a gate-all-around semiconductor structure
US10475902B2 (en) 2017-05-26 2019-11-12 Taiwan Semiconductor Manufacturing Co. Ltd. Spacers for nanowire-based integrated circuit device and method of fabricating same
US10535680B2 (en) * 2017-06-29 2020-01-14 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit structure and method with hybrid orientation for FinFET
KR102316293B1 (ko) * 2017-09-18 2021-10-22 삼성전자주식회사 반도체 장치
US10249538B1 (en) * 2017-10-03 2019-04-02 Globalfoundries Inc. Method of forming vertical field effect transistors with different gate lengths and a resulting structure
US10304832B1 (en) 2017-11-16 2019-05-28 Globalfoundries Inc. Integrated circuit structure incorporating stacked field effect transistors and method
US10685887B2 (en) 2017-12-04 2020-06-16 Tokyo Electron Limited Method for incorporating multiple channel materials in a complimentary field effective transistor (CFET) device
US10607892B2 (en) * 2017-12-26 2020-03-31 International Business Machines Corporation Junction formation in thick-oxide and thin-oxide vertical FETs on the same chip
US11374024B2 (en) 2017-12-27 2022-06-28 Intel Corporation Integrated circuits with stacked transistors and methods of manufacturing the same using processes which fabricate lower gate structures following completion of portions of an upper transistor
US11201152B2 (en) 2018-04-20 2021-12-14 Globalfoundries Inc. Method, apparatus, and system for fin-over-nanosheet complementary field-effect-transistor
US11374004B2 (en) 2018-06-29 2022-06-28 Intel Corporation Pedestal fin structure for stacked transistor integration
US11031395B2 (en) * 2018-07-13 2021-06-08 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming high performance MOSFETs having varying channel structures
US10748901B2 (en) * 2018-10-22 2020-08-18 International Business Machines Corporation Interlayer via contacts for monolithic three-dimensional semiconductor integrated circuit devices
US11411082B2 (en) 2018-10-31 2022-08-09 Taiwan Semiconductor Manufacturing Co., Ltd. Nanowire stack GAA device with selectable numbers of channel strips
EP3660891B1 (en) * 2018-11-27 2023-06-07 IMEC vzw A method for forming a semiconductor device
US10797061B2 (en) * 2018-12-17 2020-10-06 Sandisk Technologies Llc Three-dimensional memory device having stressed vertical semiconductor channels and method of making the same
US11676966B2 (en) * 2019-03-15 2023-06-13 Intel Corporation Stacked transistors having device strata with different channel widths

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190319095A1 (en) * 2017-11-02 2019-10-17 International Business Machines Corporation Vertically stacked nfets and pfets with gate-all-around structure
TW201923908A (zh) * 2017-11-15 2019-06-16 台灣積體電路製造股份有限公司 鰭式場效電晶體裝置結構的製造方法
US20200006331A1 (en) * 2018-06-29 2020-01-02 Intel Corporation Techniques for forming gate structures for transistors arranged in a stacked configuration on a single fin structure
US20200006330A1 (en) * 2018-06-29 2020-01-02 Intel Corporation Leave-behind protective layer having secondary purpose

Also Published As

Publication number Publication date
US20230369499A1 (en) 2023-11-16
JP2022027654A (ja) 2022-02-10
US11735669B2 (en) 2023-08-22
US20220037528A1 (en) 2022-02-03
DE102020130964A1 (de) 2022-02-03
CN113675194A (zh) 2021-11-19
TW202205449A (zh) 2022-02-01
KR102495803B1 (ko) 2023-02-07
KR20220016440A (ko) 2022-02-09
EP3945560A1 (en) 2022-02-02

Similar Documents

Publication Publication Date Title
US11862734B2 (en) Self-aligned spacers for multi-gate devices and method of fabrication thereof
TWI815151B (zh) 半導體裝置及其形成方法
US20180166551A1 (en) Multi-Gate Device and Method of Fabrication Thereof
US11532627B2 (en) Source/drain contact structure
US11699760B2 (en) Contact structure for stacked multi-gate device
TWI786608B (zh) 半導體裝置及其製造方法
US11862701B2 (en) Stacked multi-gate structure and methods of fabricating the same
TW202111947A (zh) 半導體裝置
US9865709B2 (en) Selectively deposited spacer film for metal gate sidewall protection
TWI793675B (zh) 半導體裝置及其形成方法
US11588050B2 (en) Backside contact
KR102481143B1 (ko) 소스/드레인 컨택 구조체
US20230395686A1 (en) Semiconductor device with gate isolation features and fabrication method of the same
TWI829141B (zh) 半導體結構及其製造方法
US20230010541A1 (en) Gate all around device and method of forming the same
US20230187518A1 (en) Semiconductor Device With Tunable Channel Layer Usage And Methods Of Fabrication Thereof
US11855161B2 (en) Semiconductor device contact structures and methods of fabricating thereof
US20240178302A1 (en) Semiconductor device with protective gate structure and methods of fabrication thereof
US20230019386A1 (en) Isolation Features For Semiconductor Devices And Methods Of Fabricating The Same
US20230018022A1 (en) Processing apparatus and method for forming semiconductor structure
TW202247354A (zh) 半導體裝置及其製造方法
CN115377004A (zh) 半导体结构的形成方法