CN114512442A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN114512442A
CN114512442A CN202210001471.9A CN202210001471A CN114512442A CN 114512442 A CN114512442 A CN 114512442A CN 202210001471 A CN202210001471 A CN 202210001471A CN 114512442 A CN114512442 A CN 114512442A
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China
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layer
source
drain
channel
drain feature
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Inventor
林志昌
陈仕承
张荣宏
姚茜甯
江国诚
王志豪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本公开的半导体装置包括第一通道构件的堆叠、直接设置在第一通道构件的堆叠上方的第二通道构件的堆叠、与前述第一通道构件的堆叠接触的一底部源极/漏极部件、设置在底部源极/漏极部件上方的一分隔层(separation layer)、与第二通道构件的堆叠接触并设置在分隔层上方的一顶部源极/漏极部件、以及延伸穿过顶部源极/漏极部件和分隔层而电性耦接至底部源极/漏极部件的一前侧接触件。

Description

半导体装置
技术领域
本发明实施例内容涉及一种半导体装置及其制造方法，特别涉及一种具有局部的互连结构(local interconnect structure)的半导体装置及其制造方法，以将底部晶体管的源极/漏极部件耦接到顶部晶体管的源极/漏极部件。
背景技术
半导体集成电路(ICs)工业经历了指数级的成长。集成电路材料和设计方面的技术进步已经产生了许多代的集成电路，其中每一代都比前一代具有更小、更复杂的电路。在集成电路发展过程中，通常增加了功能密度(即，每个芯片区域的互连装置的数量)，而缩减了几何尺寸(即，在工艺中可以产生的最小部件(或线))。此种按比例缩减尺寸的工艺通常可提高生产效率和降低相关成本而提供好处。此种按比例缩小还增加了处理和制造集成电路的复杂性。
例如，随着集成电路(IC)技术朝着更小的技术节点发展，已经引入了多栅极装置(multi-gate devices)，以通过增加栅极-通道耦合(gate-channel coupling)、减小关闭状态的电流和减少短通道效应(short-channel effects，SCE)来改善栅极控制。一个多栅极装置通常是指具有设置在通道区一侧以上的一栅极结构或栅极结构的一部分的一种装置。鳍式场效晶体管(FinFETs)和多桥通道(multi-bridge-channel，MBC)晶体管是多栅极装置的示例，这些装置已经成为高性能表现和低漏电流应用的受重视和有前景的候选装置。一个鳍式场效晶体管(FinFET)具有一抬升通道(elevated channel)，且此抬升通道的超过一侧被一栅极包裹(例如，栅极包裹了自一基底延伸而来的半导体材料的“鳍片”的顶部和侧壁)。一个多桥通道(MBC)晶体管具有可以部分或全部围绕着一通道区域延伸的一栅极结构，以提供对通道区域的两侧或更多侧的存取。由于多桥通道(MBC)晶体管的栅极结构围绕通道区域，因此多桥通道(MBC)晶体管也可以称为环绕式栅极晶体管(surroundinggate transistor，SGT)或全绕式栅极(gate-all-around，GAA)晶体管。多桥通道(MBC)晶体管的通道区可以由纳米线(nanowires)、纳米片(nanosheets)、其他纳米结构或其他合适结构而形成。并且由于通道区形状的原因，多桥通道(MBC)晶体管也具有其他别名，例如纳米片晶体管(nanosheet transist)或是纳米线晶体管(nanowire transistor)。
随着半导体工业进一步朝向次10纳米(nm)技术工艺节点发展以追求更高的装置密度、更高的性能和更低的成本，来自制造和设计两个议题的挑战导致了堆叠装置结构(stacked device structure)的配置，例如互补式场效晶体管(complementary fieldeffect transistors，C-FET)，互补式场效晶体管的其中一个n型多栅极晶体管和一个p型多栅极晶体管是以一个在另一个上方的方式垂直堆叠。在这样的互补式场效晶体管(C-FET)中形成局部互连部件(local interconnect feature)，可能涉及形成穿过外延源极/漏极部件(epitaxial source/drain feature)的开口或是形成穿过与外延源极/漏极部件相邻的某些介电隔离部件(dielectric isolation features)的开口。
发明内容
本发明的一些实施例提供一种半导体装置。此半导体装置包括一第一通道构件的堆叠(a stack of first channel members)以及一第二通道构件的堆叠(a stack ofsecond channel members)，此第二通道构件的堆叠直接设置在前述第一通道构件的堆叠的上方。在一些实施例中，此半导体装置还包括一底部源极/漏极部件(bottom source/drain feature)，此底部源极/漏极部件与前述第一通道构件的堆叠接触。在一些实施例中，此半导体装置还包括一分隔层(separation layer)，此分隔层设置在前述第一通道构件的堆叠的上方。在一些实施例中，此半导体装置还包括一顶部源极/漏极部件(topsource/drain feature)，此顶部源极/漏极部件与前述第二通道构件的堆叠接触，并且设置在前述分隔层的上方。在一些实施例中，此半导体装置还包括一前侧接触件(frontsidecontact)，此前侧接触件延伸穿过前述顶部源极/漏极部件和前述分隔层，并且电性耦接至前述底部源极/漏极部件。
本发明的一些实施例又提供一种半导体结构。此半导体结构包括一第一底部源极/漏极部件(first bottom source/drain feature)和一第二底部源极/漏极部件(second bottom source/drain feature)。在一些实施例中，此半导体结构还包括在前述第一底部源极/漏极部件和前述第二底部源极/漏极部件之间延伸的一第一通道构件的堆叠(a stack of first channel members)。在一些实施例中，此半导体结构还包括位于前述第一底部源极/漏极部件上方的一第一分隔层(first separation layer)。在一些实施例中，此半导体结构还包括位于前述第二底部源极/漏极部件上方的一第二分隔层(secondseparation layer)。在一些实施例中，此半导体结构还包括设置在前述第一分隔层上方的第一顶部源极/漏极部件(first top source/drain feature)，以及设置在前述第二分隔层上方的第二顶部源极/漏极部件(second top source/drain feature)。在一些实施例中，此半导体结构还包括在前述第一顶部源极/漏极部件和前述第二顶部源极/漏极部件之间延伸的一第二通道构件的堆叠(a stack of second channel members)。在一些实施例中，此半导体结构还包括设置在前述第一顶部源极/漏极部件上方的一第一前侧接触件(first frontside contact)，并且此第一前侧接触件与前述第一顶部源极/漏极部件接触。在一些实施例中，此半导体结构还包括一第二前侧接触件(second frontsidecontact)，此第二前侧接触件延伸穿过前述第二顶部源极/漏极部件和前述第二分隔层，并且此第二前侧接触件与前述第二底部源极/漏极部件接触。
本发明的一些实施例提供一种半导体装置的形成方法。此方法包括提出一工件(workpiece)，此工件包括一基底(substrate)和位于前述基底上方的一堆叠(stack)，前述堆叠包括由多个牺牲层(sacrificial layers)和多个通道层(channel layers)交错设置，前述多个通道层包括多个底部通道层(bottomchannel layer)和设置在多个底部通道层之上的多个顶部通道层(top channel layers)。在一些实施例中，此形成方法还包括将前述堆叠和前述基底的一部分图案化成一鳍状结构(fin-shaped structure)，前述鳍状结构包括一源极/漏极区(source/drain region)。在一些实施例中，此形成方法还包括使前述源极/漏极区下凹(recessing)以形成源极/漏极凹槽，暴露出前述多个通道层的侧壁。在一些实施例中，此形成方法还包括在源极/漏极凹槽中沉积一底部源极/漏极部件(bottomsource/drain feature)以与前述多个底部通道层接触。在一些实施例中，此形成方法还包括在前述底部源极/漏极部件上方沉积一分隔层(separation layer)。在一些实施例中，此形成方法还包括沉积一顶部源极/漏极部件(top source/drain feature)于前述分隔层的上方并且与前述多个顶部通道层接触，此顶部源极/漏极部件包括一间隙(gap)，此间隙暴露出前述分隔层。在一些实施例中，此形成方法还包括在前述间隙中形成一填充层(fillerlayer)。在一些实施例中，此形成方法还包括形成穿过前述填充层和前述分隔层的一接触开口(contact opening)以暴露出前述底部源极/漏极部件，并在前述接触开口中形成一接触件(contact feature)。
附图说明
通过以下的详细描述配合说明书附图，可以更加理解本发明实施例的内容。需强调的是，根据产业上的标准惯例，许多部件(feature)并未按照比例绘制。事实上，为了能清楚地讨论，各种部件的尺寸可能被任意地增加或减少。
图1是说明根据本公开的各个方面的用于形成具有一垂直的互补式场效晶体管(C-FET)结构的一半导体装置的方法的流程图。
图2至图20示出了根据本公开的一些实施例，一工件(workpiece)在处于如图1的方法提出的各种制造阶段的局部剖面示意图。
附图标记说明：
100：方法
102,104,106,108,110,112,114,116,118,120,122,124,126,128,130：步骤
200：工件(半导体装置)
202：基底
204：堆叠
204B：底面部分
204M：中间部分
204T：顶面部分
206：牺牲层
208：通道层
2080：通道构件
210：鳍状结构
210C：通道区
210SD：源极/漏极区
214：虚置栅极堆叠
216：虚置介电层
218：虚置栅极电极层
220：栅极间隔层
224-1：第一源极/漏极凹槽
224-2：第二源极/漏极凹槽
226：内部间隔物部件
228：底部源极/漏极部件
228-1：第一底部源极/漏极部件
228-2：第二底部源极/漏极部件
242：分隔层(隔离层)
248-1：第一顶部源极/漏极部件
248-2：第二顶部源极/漏极部件
249：间隙
250：第一掩膜层
252：第二掩膜层
253：填充材料
254：填充层
256：接触蚀刻停止层
258：层间介电层
260：栅极结构
262：界面层
264：栅极介电层
266P：p型电极层
266N：n型电极层
267：自对准帽盖层
268：第一前侧接触开口
270,272：第二前侧接触开口
273：第一硅化物层
274：第二硅化物层
275：第三硅化物层
276：第一前侧接触件
278：第二前侧接触件
280：背面介电层
281：第一背面接触开口
282：第二背面接触开口
283：阻挡层
284：背面硅化物层
286：第一背面接触件
288：第二背面接触件
300：底部多桥通道(MBC)晶体管
400：顶部多桥通道(MBC)晶体管
具体实施方式
以下内容提供了很多不同的实施例或范例，用于实现本发明实施例的不同部件。组件和配置的具体范例描述如下，以简化本发明实施例。当然，这些仅仅是范例，并非用以限定本发明实施例。举例来说，叙述中若提及一第一特征部件形成于一第二特征部件的上方或位于其上，可能包含上述第一和第二特征部件直接接触的实施例，也可能包含额外的特征部件形成于上述第一特征和上述第二特征部件之间，使得第一和第二特征部件不直接接触的实施例。另外，本发明实施例可能在许多范例中重复元件符号及/或字母。这些重复是为了简化和清楚的目的，其本身并非代表所讨论各种实施例及/或配置之间有特定的关系。
再者，文中可能使用空间上的相关用语，例如“在…之下”、“在…下方”、“下方的”、“在…上方”、“上方的”及其他类似的用语，以便描述如附图所示的一个元件或部件与其他的元件或部件之间的关系。此空间上的相关用语除了包含附图示出的方位外，也包含使用或操作中的装置的不同方位。装置可以被转至其他方位(旋转90度或其他方位)，则在此所使用的空间相对描述可同样依旋转后的方位来解读。
再者，当使用“约”、“大约”、或类似的用语来描述一个数值或一个数值范围时，除非有另外指明，则此用语是用于涵盖在一合理范围的数值，且此范围考量到本领域的普通技术人员所能理解的在工艺期间所产生的固有的变化。例如，基于制造与此数值相关联的部件的已知制造公差，此数值或数值范围涵盖了包括所述数值的一合理范围，例如在所述数值的+/–10％以内。例如，厚度为“约5nm”的一材料层可包含的厚度尺寸范围为4.25nm至5.75nm，其中本领域的普通技术人员已知与沉积此材料层相关的制造公差为+/–15％。再者，本公开可能在不同示例中重复元件符号及/或字母。此些重复是为了简化和清楚的目的，其本身并非代表所讨论各种实施例及/或配置之间具有特定关系。
本公开大致上涉及堆叠的多栅极装置(stacked multi-gate device)及其制造方法，特别涉及堆叠的多栅极装置的局部的接触结构(local contact structures)。
堆叠的多栅极装置是指包括一第一多栅极装置(first multi-gate device)和堆叠在第一多栅极装置上方的一第二多栅极装置(second multi-gate device)的一种半导体装置。当第一多栅极装置和第二多栅极装置的导电形态不同时，堆叠的多栅极装置可以是互补式场效晶体管(complementary field effect transistor，C-FET)。互补式场效晶体管(C-FET)中的多栅极装置可以是鳍式场效晶体管(FinFET)或多桥通道(MBC)晶体管。对于一些逻辑操作，第一多栅极装置的源极/漏极部件和第二多栅极装置的源极/漏极部件之间需要局部的电性连接(local electrical connection)。在一些现有技术中，可以通过穿过在源极/漏极部件周围的介电部件(dielectric features)而形成此种局部的电性连接。在一些其他的现有技术中，在第二多栅极装置的源极/漏极部件处蚀刻出通孔(throughopening)，这可能在工艺中导致对源极/漏极部件造成损坏。
本公开提供一种局部的接触部件(local contact feature)，其将一顶部多栅极装置(top multi-gate device)的源极/漏极部件直接的和垂直的耦接至底部多栅极装置的源极/漏极部件。局部的接触部件设置在一局部的接触开口(local contact opening)中，其中此局部的接触开口是以自对准方式而形成。在一示例的工艺中，一鳍形结构由包括多个通道层的一堆叠所形成。一底部源极/漏极部件沉积以接触位于前述堆叠的底面部分(bottomportion)的通道层。一分隔层(separation layer)沉积于底部源极/漏极部件的上方，以使前述堆叠的一中间部分(middle portion)的通道层失效(disable)。然后，一顶部源极/漏极部件沉积在分隔层的上方，以与前述堆叠的一顶面部分(top portion)的通道层接触。顶部源极/漏极部件包括一间隙(gap)，前述间隙暴露出前述分隔层。一填充层(filler layer)沉积在前述间隙中。一局部的接触开口(local contact opening)的形成穿过前述填充层和前述分隔层，此局部的接触开口并暴露出前述底部源极/漏极部件。一局部接触部件(local contact feature)形成于前述局部的接触开口中，以耦接前述底部源极/漏极部件和前述顶部源极/漏极部件。出于说明的目的，本公开的结构和制造方法的细节涉及具有堆叠的多桥通道(MBC)晶体管的互补式场效晶体管(C-FET)进行描述如下。然而，本公开不限于此，类似的结构和工艺也可适用于具有其他类型的堆叠的多栅极晶体管的互补式场效晶体管。
现在将参考附图更详细地描述本公开的各个方面。就此而言，图1是说明根据本公开的各个方面的用于形成具有一垂直的互补式场效晶体管(C-FET)结构的一半导体装置的方法100的流程图。方法100仅是一示例，并且并非旨在将本公开限制在方法100中所明确示出的内容。对于此方法的其他实施例，可以在方法100之前、期间和之后提供一些额外的步骤，并且可以替换、消除或者移动所描述的某些步骤。为了简单起见，本文并没有详细描述所有步骤。以下结合图2至图20描述方法100，其为根据方法100的实施例的处于不同制造阶段的一工件(workpiece)200的局部透视图或剖面示意图。由于在制造过程结束时会将工件200制造成一半导体装置200，所以可以根据上下文的需要，将工件200称为半导体装置200。此外，在整个申请内容中，除非另有说明，否则相同的附图标记表示相同的部件。
参照图1和图2，方法100包括步骤102，其包括提供一工件200。工件200可以包括基底(substrate)202和设置在基底202上方的一堆叠(stack)204。在一个实施例中，基底202可以是一硅(Si)基底。在一些其他实施例中，基底202可以包括其他半导体，例如锗(Ge)、硅锗(SiGe)或III-V半导体材料。III-V半导体材料的示例可以包括砷化镓(galliumarsenide，GaAs)、磷化铟(indium phosphide，InP)、磷化镓(gallium phosphide，GaP)、氮化镓(gallium nitride，GaN)、磷化砷化镓(gallium arsenide phosphide，GaAsP)、砷化铝铟(aluminum indium arsenide，AlInAs)、砷化铝镓(aluminum gallium arsenide，AlGaAs)、磷化铟镓镓(gallium indium phosphide，GaInP)和砷化铟镓(indium galliumarsenide，InGaAs)。基底202还可以包括一绝缘层，例如氧化硅层，而具有一绝缘体上覆硅(silicon-on-insulator，SOI)结构。尽管图中未明确示出，但是基底202可以包括用于制造不同导电形态的晶体管的n型井区(n-type well region)和p型井区(p-type wellregion)。当存在时，n型井区和p型井区中的各个井区形成在基底202中并且分别包括一掺杂分布。n型井区可以包括一n型掺质的掺杂分布，n型掺质例如是磷(P)或砷(As)。p型井区可以包括一p型掺质的掺杂分布，p型掺质例如是硼(B)。可以使用离子布值(ionimplantation)或热扩散(thermal diffusion)来形成n型井区和p型井区中的掺杂分布，并且可以将其视为基底202的一部分。
如图2所示，堆叠204包括交错设置的多个通道层(channel layers)208与多个牺牲层(sacrificial layers)206。通道层208和牺牲层206可具有不同的半导体组成。在一些实施方式中，通道层208由硅(Si)形成，而牺牲层206由硅锗(SiGe)形成。在这些实施方案中，牺牲层206中的额外锗含量可使得选择性去除或下凹牺牲层206时不会对通道层208造成实质性的损坏。在一些实施例中，牺牲层206和通道层208是外延层(epitaxy layers)，并且可以使用外延工艺(epitaxy process)沉积而成。合适的外延工艺包括气相外延(vapor-phase epitaxy，VPE)、超高真空化学气相沉积(ultra-high vacuumchemical vapordeposition，UHV-CVD)、分子束外延(molecular beam epitaxy，MBE)、以及/或其他合适的工艺。牺牲层206和通道层208一层接一层的交替沉积，以形成堆叠204。
如以下文中将更详细地解释，堆叠204的底面部分中的通道层208将提供一底部多桥通道晶体管(bottom MBC transistor)的通道构件，并且堆叠204的顶面部分中的通道层208将提供底部多桥通道晶体管的通道构件。“通道构件”一词在本文中用于代表具有纳米级尺寸并具有细长形状的一晶体管中的通道(多个通道)的任何材料部分，而不论此材料部分的剖面形状如何。通道构件可以是纳米线、纳米片或其他纳米结构的形式，并且可以具有圆形、椭圆形、跑道形、矩形或正方形的剖面。为了便于参照，可以垂直地将堆叠204分为一底面部分204B、在底面部分204B上方的一中间部分204M以及在中间部分204M上方的顶面部分204T。如图2所示，底面部分204B、中间部分204M和顶面部分204T中的每个部分包括一个或多个通道层208以及一个或多个牺牲层206。
应注意的是，图2中的堆叠204包括与七层牺牲层206交错的八层通道层208，此仅用于说明目的，而非旨在限制超出权利要求书中记载的具体内容的范围。可以理解的是，堆叠204中可以包括任何数量的通道层208，并且分布在底面部分204B、中间部分204M和顶面部分204T之中。层数取决于顶部多桥通道(MBC)晶体管和底部多桥通道(MBC)晶体管所需的通道构件数量。在一些实施例中，堆叠204中的通道层208的数量可以在3到12之间。通道层208和牺牲层206的厚度可以基于底部多桥通道(MBC)晶体管、顶部多桥通道(MBC)晶体管和互补式场效晶体管(C-FET)做为整体的装置性能考虑来做选择。此外，通道层208和牺牲层206可以有意地制造得更薄以形成一个或多个失去功能(disabled channel members)的通道构件。例如，比起其余的通道层208更薄的一个通道层208可能在通道释出工艺(channelrelease process)中被切断或损坏。又例如，比起其余的牺牲层206更薄的一牺牲层206可能导致通道与通道之间的间距缩减(reduced channel-channel spacing)，其中此间距可能大致上被栅极介电材料填满。在通道与通道之间缩减的间距中填满的栅极介电材料可以避免后续沉积的栅极电极材料进入缩减的通道-通道间距中。
参照图1和图3，方法100包括步骤104，其中由堆叠204形成一鳍状结构(fin-shaped structure)210。在一些实施例中，堆叠204和基底202的一部分被图案化以形成鳍状结构210。鳍状结构210。为了图案化的目的，可以在堆叠204上方沉积一硬掩膜层(hardmask layer)。硬掩膜层可以是单层或是多层。在一个示例中，硬掩膜层包括一氧化硅层和氧化硅层上方的一氮化硅层。如图3所示，鳍状结构210从基底202沿着Z方向垂直的延伸并沿着X方向纵向的延伸。鳍状结构210可以使用合适的工艺进行图案化，包括双重图案化(double-patterning)或多重图案化(multi-patterning)工艺。一般而言，双重图案化或多重图案化工艺是结合了光刻及自对准工艺，得以使形成的图案的节距(pitch)小于使用单一、直接的光刻工艺所能得到的节距。例如，在一实施例中，在一基底的上方形成一材料层，并使用一光刻工艺将此材料层图案化。使用自对准工艺在上述已图案化的材料层旁边形成间隔物(spacers)。然后移除材料层，利用留下的间隔物或芯轴(mandrels)作为一蚀刻掩膜，以对堆叠204和基底202进行蚀刻而形成鳍状结构210。蚀刻工艺可以包括干式蚀刻、湿式蚀刻、反应性离子蚀刻(reactive ion etching，RIE)以及/或其他合适的工艺。
虽然图3中未明确示出，但在形成鳍状结构210之后，形成隔离部件(isolationfeature)以将鳍状结构210与相邻的鳍状结构(未明确示出)分隔开来。隔离部件也可以称为浅沟槽隔离(shallow trench isolation，STI)部件。在一示例工艺中，用于形成隔离部件的一介电材料沉积在工件200上，包括鳍状结构210，并且可使用化学气相沉积(CVD)、次大气压化学气相沉积(subatmospheric CVD，SACVD)、流动式化学气相沉积、旋转涂布和/或其他合适的工艺进行介电材料的沉积。然后，平坦化并下凹所沉积的介电材料，直到鳍状结构210抬升到隔离部件之上。用于形成隔离部件的介电材料可以包括氧化硅、氮氧化硅、掺氟硅酸盐玻璃(fluorine-doped silicate glass，FSG)、低介电常数介电质、前述的组合以及/或其他合适的材料。
仍然参照图1和图3，方法100包括步骤106，其中在堆叠204上方形成虚置栅极堆叠(dummy gate stack)214。在一些实施例中，采用一栅极替换工艺(或一栅极后制工艺)，其中虚置栅极堆叠214做为一功能性栅极结构的占位件。也可以使用其他工艺和配置方式。为了形成虚置栅极堆叠214，在工件200上方沉积一虚置介电层(dummy dielectric layer)216、一虚置栅极电极层(dummy gate electrode layer)218和一栅极顶部硬掩膜层(gate-top hard mask layer)(未明确示出)。可以使用包括低压化学气相沉积(LPCVD)、化学气相沉积(CVD)、等离子体辅助化学气相沉积(plasma-enhanced CVD，PECVD)、物理气相沉积(physical vapor deposition，PVD)、原子层沉积(atomic layer deposition，ALD)、热氧化、电子束蒸发(e-beam evaporation)、或其他合适的沉积技术、或前述的组合来沉积这些材料层。虚置介电层216可以包括氧化硅，虚置栅极电极层218可以包括多晶硅，并且栅极顶部硬掩膜层可以是包括氧化硅和氮化硅的一多层结构。使用光刻和蚀刻工艺，以图案化栅极顶部硬掩膜层。光刻工艺可以包括光刻胶涂布(例如，旋转涂布)、软烘烤、掩膜对准、曝光、曝光后烘烤、光刻胶显影、冲洗、干燥(例如，旋转干燥以及/或硬烘烤)、其他合适的微影技术、以及/或前述方法的组合。蚀刻工艺可以包括干式蚀刻(例如反应性离子蚀刻)、湿式蚀刻和/或其他蚀刻方法。之后，使用图案化的栅极顶部硬掩膜层作为蚀刻掩膜，然后蚀刻虚置介电层216和虚置栅极电极层218，以形成虚置栅极堆叠214。虚置栅极堆叠214沿着Y方向纵向延伸以包裹于鳍状结构210上并停在隔离部件上。位于虚置栅极堆叠214下方的鳍状结构210的部分定义了通道区(channel region)210C。通道区210C和虚置栅极堆叠214还定义了漏极/源极区(source/drain regions)210SD，这些漏极/源极区210SD不与虚置栅极堆叠214垂直重叠。通道区210C沿着X方向设置在两个漏极/源极区210SD之间。
参照图1和图4，方法100包括步骤108，其中下凹鳍状结构210中的源极/漏极区210SD，以形成第一源极/漏极凹槽(source/drain recess)224-1和第二源极/漏极凹槽224-2。步骤108的操作可包括在源极/漏极区210SD凹陷之前，先在虚置栅极堆叠214的侧壁上形成栅极间隔层(gate spacer layer)220。在一些实施例中，栅极间隔层220的形成包括在工件200上方沉积一层或多层的介电层。在一示例工艺中，可以使用化学气相沉积(CVD)、次大气压化学气相沉积(SACVD)、或原子层沉积(ALD)沉积一或多层的介电层。前述一或多层的介电层可以包括氧化硅、氮化硅、碳化硅、氧氮化硅、碳氮化硅、碳氧化硅、碳氧氮化硅以及/或前述的组合。在沉积栅极间隔层220之后，在一非等向性蚀刻工艺中对工件200进行蚀刻，以形成第一源极/漏极凹槽224-1和第二源极/漏极凹槽224-2。在步骤108中的蚀刻工艺可以是干式蚀刻工艺或合适的蚀刻工艺。示例性的干式蚀刻工艺可以实施含氧气体、氢气、含氟气体(例如CF4、SF6、NF3、CH2F2、CHF3和/或C2F6)、含氯气体(例如Cl2、CHCl3、CCl4和/或BCl3)、含溴气体(例如HBr和/或CHBR3)、含碘气体、其他合适的气体以及/或等离子体、以及/或前述的组合。如图4所示，通道区210C中的牺牲层206和通道层208的侧壁暴露在第一源极/漏极凹槽224-1和第二源极/漏极凹槽224-2中。
参照图1和图5，方法100包括步骤110，其中形成内部间隔物部件(inner spacerfeatures)226。在步骤110中，暴露在第一源极/漏极凹槽224-1和第二源极/漏极凹槽224-2中的底面部分204B、中间部分204M和顶面部分204T的牺牲层206被选择性的且部分的凹陷，以形成内部间隔物凹陷(inner spacer recesses)，而暴露出的通道层208基本上未被蚀刻。在通道层208基本上由硅(Si)组成并且牺牲层206基本上由硅锗(SiGe)组成的一实施例中，选择性的和部分的凹陷牺牲层206的步骤可以包括硅锗(SiGe)氧化工艺，之后去除硅锗氧化物。在这样的实施例中，SiGe氧化工艺可以包括使用臭氧(O3)。在一些其他实施例中，选择性的下凹工艺可以是一选择性的等向性蚀刻工艺(selective isotropic etchingprocess)(例如，选择性干式蚀刻工艺、或选择性湿式蚀刻工艺)，并且牺牲层206的下凹程度是由蚀刻工艺的持续时间控制。选择性干式蚀刻工艺可以包括使用一种或多种基于氟的蚀刻剂(fluorine-based etchants)，例如含氟气体或氢氟碳化合物。选择性湿式蚀刻工艺可以包括氟化氢(HF)或氢氧化铵(NH4OH)蚀刻剂。在形成内部间隔物凹陷之后，将一内部间隔物材料层(inner spacer material layer)沉积在工件200上方，包括沉积在内部间隔物凹陷中。内部间隔物材料层可以包括氧化硅、氮化硅、碳氧化硅、碳氮氧化硅、碳氮化硅、金属氮化物、或一合适的介电材料。然后，回蚀沉积的内部间隔物材料层，以去除内部间隔物部件226上和通道层208的侧壁上多余的内部间隔物材料层，因而形成如图5所示的内部间隔物部件226。在一些实施例中，步骤110处的蚀刻工艺可以是干式蚀刻工艺，其包括使用含氧气体、氢气、氮气、含氟气体(例如，NF3、CF4、SF6、CH2F2、CHF3以及/或C2F6)、含氯气体(例如Cl2、CHCl3、CCl4以及/或BCl3)、含溴气体(例如HBr以及/或CHBR3)、含碘气体(例如CF3I)、其他合适的气体、以及/或等离子体、以及/或前述的组合。
参照图1、图6和图7，方法100包括步骤112，其中第一底部源极/漏极部件(firstbottom source/drain feature)228-1和第二底部源极/漏极部件228-2(second bottomsource/drain feature)分别形成在第一源极/漏极凹槽224-1和第二源极/漏极凹槽224-2中。为了便于参照，第一底部源极/漏极部件228-1和第二底部源极/漏极部件228-2可以一并称为底部源极/漏极部件228。首先参照图6。在一些实施例中，底部源极/漏极部件228可以使用外延工艺(epitaxial process)形成，例如气相外延(VPE)、超高真空化学气相沉积(UHV-CVD)、分子束外延(MBE)以及/或其他合适的工艺。外延生长工艺可以使用气态以及/或液态前驱物，它们可与基底202以及通道层208的成分相互反应。底部源极/漏极部件228的外延生长自基底202的顶面和通道层208暴露出的侧壁这两者开始发生。如图6所示，沉积的底部源极/漏极部件228与通道层208物理性的接触(或邻接)。虽然底部源极/漏极部件228的外延生长不太可能发生在内部间隔物部件226的表面上，但底部源极/漏极部件228的过度生长使得底部源极/漏极部件228在内部间隔物部件226之上合并。根据设计需求，底部源极/漏极部件228可以是n型或p型。在所叙述的实施例中，底部源极/漏极部件228是p型源极/漏极部件，并且可以包括掺杂有p型掺质的硅锗(SiGe)，例如硼(B)。在这些叙述的实施例中，底部源极/漏极部件228可以包括硼掺杂的硅锗(SiGe：B)。以底部源极/漏极部件228作为p型源极/漏极部件具有一些优点。例如，其硅锗(SiGe)成分可以有助于在背面接触件(backside contacts)和背面介电层(backside dielectric layers)的形成过程中选择性的去除基底202。又例如，暴露的基底202可提供更多的外延晶种表面(epitaxial seedsurfaces)以形成缺陷较少的硅锗源极/漏极晶体结构，从而在通道构件上提供所需的应变(strain)。根据观察，应变的硅通道(strained silicon channels)比起未应变的硅通道可提供更好的空穴迁移率(hole mobility)。
参照图7，沉积的底部源极/漏极部件228之后被回蚀刻/拉回(etched back/pulled back)，直到底部源极/漏极部件228仅覆盖底面部分204B中的通道层208而不覆盖中间部分204M或顶面部分204T中的通道层208。回蚀刻或拉回工艺可以包括干式蚀刻、湿式蚀刻、以及/或其他合适的工艺。由于底部源极/漏极部件228和牺牲层206均由硅锗(SiGe)形成，用来形成内部间隔物凹陷的蚀刻工艺可用来对沉积的底部源极/漏极部件228进行回蚀刻。在步骤112中，一示例的选择性干式蚀刻工艺可包括使用一种或多种氟基蚀刻剂(fluorine-based etchants)，例如氟气或氢氟碳化合物。在步骤112中，一示例的选择性湿式蚀刻工艺可包括使用氟化氢(HF)或氢氧化铵(NH4OH)。
参照图1和图8，方法100包括步骤114，其中在底部源极/漏极部件228上方形成一分隔层(separation layer)242。分隔层242也可以被称为隔离层(isolation layer)242，因为它起到了分隔或隔离底部源极/漏极部件228与顶部源极/漏极部件的作用(将在下面描述)。在一些实施例中，分隔层242可包括氧化硅或含有氧化硅的材料，例如四乙氧基硅烷(Tetra Ethyl Ortho Silicate，TEOS)氧化物、未掺杂硅酸盐玻璃、或是例如硅酸硼磷硅酸盐玻璃(BPSG)、熔融石英玻璃(FSG)、磷硅玻璃(Phospho-Silicate Glass，PSG)、硼硅玻璃(Boro-Silicate Glass，BSG)之类的掺杂硅氧化物的材料、和/或其他合适的介电材料。在一实施例中，分隔层242包括氧化硅。在一些实施方式中，分隔层242可以通过在工件200上方沉积一介电材料而形成，包括在第一底部源极/漏极部件228-1和第二底部源极/漏极部件228-2的上方，通过流动式化学气相沉积(FCVD)、化学气相沉积(CVD)、高密度等离子体化学气相沉积(HDPCVD)、或合适的沉积技术而沉积介电材料。在一实施例中，可使用流动式化学气相沉积(FCVD)以沉积用来形成分隔层242的介电材料。然后，回蚀刻沉积的介电材料，直到分隔层242仅覆盖中间部分204M中的通道层208，但暴露出顶面部分204T中的通道层208。
参照图1和图9，方法100包括步骤116，其中在第一源极/漏极凹槽224-1中形成第一顶部源极/漏极部件248-1，而第二源极/漏极凹槽224-2则被第一掩膜层(first maskinglayer)250覆盖。在步骤116中，第一掩膜层250沉积在工件200上方，然后图案化第一掩膜层250以覆盖第二源极/漏极凹槽224-2，同时暴露出第一源极/漏极凹槽224-1。在一实施例中，第一掩膜层250是一底部抗反射涂层(bottom antireflective coating，BARC)，其可以包括聚砜(polysulfones)、聚脲(polyureas)、聚脲砜(polyurea sulfones)、聚丙烯酸酯(polyacrylates)、聚(乙烯基吡啶)(poly(vinyl pyridine))、或含硅聚合物。在另一实施例中，第一掩膜层250是可以是单层或多层的硬掩膜层。例如，当第一掩膜层250为硬掩膜层时，第一掩膜层250可以包括氧化硅、氮化硅、碳化硅、碳氧化硅、氮氧化硅或碳氧氮化硅。可以使用光刻工艺和蚀刻工艺来图案化图9所示的第一掩膜层250。光刻工艺可以包括光刻胶涂布(例如，旋转涂布)、软烘烤、掩膜对准、曝光、曝光后烘烤、光刻胶显影、冲洗、干燥(例如，旋转干燥以及/或硬烘烤)、其他合适的微影技术、以及/或前述方法的组合。然后，将所得的图案化光刻胶层做为一蚀刻掩膜，以图案化第一掩膜层250。
有第一掩膜层250覆盖第二源极/漏极凹槽224-2，第一顶部源极/漏极部件248-1沉积在第一源极/漏极凹槽224-1中的分隔层242的上方。类似于第一底部源极/漏极部件228-1和第二底部源极/漏极部件228-2的形成，可以使用外延工艺例如气相外延(VPE)、超高真空化学气相沉积(UHV-CVD)、分子束外延(MBE)以及/或其他合适的工艺，而形成第一顶部源极/漏极部件248-1。外延生长工艺可以使用气态和/或液态前驱物，其与顶面部分204T中的通道层208相互反应。因此，第一顶部源极/漏极部件248-1的外延生长可以从顶面部分204T中的通道层208的暴露侧壁发生，而不是从顶面部分204T中的内部间隔部件226和分隔层242的表面发生。如图9所示，第一顶部源极/漏极部件248-1的过度生长(overgrowth)可以在内部间隔部件226和分隔层242之上合并。在图9所示的实施例中，第一顶部源极/漏极部件248-1的沉积进行一段时间，以大致上填充两个相邻通道区210C的两个相邻顶面部分204T之间的空间。根据设计，第一顶部源极/漏极部件248-1可以是n型或p型。在所描述的实施例中，第一顶部源极/漏极部件248-1是n型源极/漏极部件，并且可以包括掺杂有n型掺质的硅(Si)，n型掺质例如是磷(P)或砷(As)。在这些描述的实施例中，第一顶部源极/漏极部件248-1可以包括磷掺杂的硅(Si：P)。在形成第一顶部源极/漏极部件248-1之后，通过例如灰化(ashing)、剥除(stripping)或选择性蚀刻以去除第一掩膜层250。
参照图1和图10，方法100包括步骤118，其中在第二源极/漏极凹槽224-2中形成第二顶部源极/漏极部件248-2，而第一源极/漏极凹槽224-1则被第二掩膜层(secondmasking layer)252覆盖。在步骤118中，第二掩膜层252沉积在工件200上方，然后被图案化以覆盖第一顶部源极/漏极部件248-1，同时暴露出第二源极/漏极凹槽224-2。在一实施例中，第二掩膜层252是一底部抗反射涂层(BARC)层，其可以包括聚砜(polysulfones)、聚脲(polyureas)、聚脲砜(polyurea sulfones)、聚丙烯酸酯(polyacrylates)、聚(乙烯基吡啶)(poly(vinyl pyridine))、或含硅聚合物。在另一实施例中，第二掩膜层252为硬掩膜层，其可为单层或多层。例如，当第二掩膜层252为硬掩膜层时，第二掩膜层252可以包括氧化硅、氮化硅、碳化硅、碳氧化硅、氮氧化硅或碳氧氮化硅。可以使用光刻工艺和蚀刻工艺来图案化图10所示的第二掩膜层252。光刻工艺可以包括光刻胶涂布(例如，旋转涂布)、软烘烤、掩膜对准、曝光、曝光后烘烤、光刻胶显影、冲洗、干燥(例如，旋转干燥以及/或硬烘烤)、其他合适的微影技术、以及/或前述方法的组合。然后，将所得图案化光刻胶层做为一蚀刻掩膜，以图案化第二掩膜层252。
有第二掩膜层252覆盖第一顶部源极/漏极部件248-1，第二顶部源极/漏极部件248-2沉积在第二源极/漏极凹槽224-2中。第二顶部源极/漏极部件248-2可以使用外延工艺形成，例如气相外延(VPE)、超高真空化学气相沉积(UHV-CVD)、分子束外延(MBE)以及/或其他合适的工艺。外延生长工艺可以使用气态和/或液态前驱物，其与暴露在第二源极/漏极凹槽224-2中的顶面部分204T中的通道层208相互反应。因此，第二顶部源极/漏极部件248-2的外延生长可以从顶面部分204T中的通道层208的暴露侧壁发生，而不是从顶面部分204T中的内部间隔部件226和分隔层242的表面发生。如图10所示，第二顶部源极/漏极部件248-2的过度生长可以在内部间隔物部件226之上合并。与第一顶部源极/漏极部件248-1不同，第二顶部源极/漏极部件的沉积248-2持续较短的持续时间，使得第二顶部源极/漏极部件248-2可在分隔层242的上方合并。在一些情况下，第二顶部源极/漏极部件248-2可以具有在2nm至约10nm之间沿着X方向的厚度。即，第二顶部源极/漏极部件248-2可以沿着Z方向在内部间隔部件226上方合并，但不会增加厚度以沿着X方向在分隔层242上方合并。如图10所示，在步骤118中完全形成第二顶部源极/漏极部件248-2之后，第二顶部源极/漏极部件248-2中保留有一间隙(gap)249，并且在此间隙249中暴露出分隔层242。根据设计，第二顶部源极/漏极部件248-2可以是n型或p型。在所描述的实施例中，类似于第一顶部源极/漏极部件248-1，第二顶部源极/漏极部件248-2是一n型源极/漏极部件，并且可以包括掺杂有n型掺质的硅，n型掺质例如是磷(P)或砷(As)。在这些描述的实施例中，第二顶部源极/漏极部件248-2可以包括磷掺杂的硅(Si：P)。在形成第二顶部源极/漏极部件248-2之后，通过例如灰化(ashing)、剥除(stripping)或选择性蚀刻以去除第二掩膜层252。
参照图1、图11和图12，方法100包括步骤120，其中在第二顶部源极/漏极部件248-2中的间隙249中形成一填充层(filler layer)254。步骤120可以包括在工件200上方沉积一填充材料(filler material)253(如图11所示)，并且回蚀填充材料253以在间隙249中形成填充层254(如图12所示)。在一些实施例中，可以使用原子层沉积(ALD)、流动式化学气相沉积(FCVD)或高密度等离子体化学气相沉积(HDPCVD)来沉积填充材料253。在一实施例中，填充材料253可使用原子层沉积(ALD)。以原子层沉积方式所沉积的填充材料253可以有效的填充间隙249，并且只需很少的回蚀来形成填充层254。如图11所示，沉积的填充材料253不仅填充间隙249，而且沉积在第一顶部源极/漏极部件248-1和栅极间隔层220的侧壁上。填充材料253可以包括介电材料。在一些实施方式中，填充材料253的成分可以类似于分隔层242的成分。在一些情况下，填充材料253可以包括氧化硅或含有氧化硅的材料，例如四乙氧基硅烷(Tetra Ethyl Ortho Silicate，TEOS)氧化物、未掺杂硅酸盐玻璃、或是例如硅酸硼磷硅酸盐玻璃(BPSG)、熔融石英玻璃(FSG)、磷硅玻璃(Phospho-Silicate Glass，PSG)、硼硅玻璃(Boro-Silicate Glass，BSG)之类的掺杂硅氧化物的材料、和/或其他合适的介电材料。在一实施例中，填充材料253可包括氧化硅。在一些实施例中，填充材料253被回蚀刻，直到第一顶部源极/漏极部件248-1和第二顶部源极/漏极部件248-2暴露在第一源极/漏极凹槽224-1和第二源极/漏极凹槽224-2中。在步骤120的操作结束时，形成填充层254，如图12所示。填充层254可作为一插塞(plug)以塞住图10中所示的间隙249。
参照图1和图13，方法100包括步骤122，其中在第一顶部源极/漏极部件248-1和第二顶部源极/漏极部件248-2上沉积一接触蚀刻停止层(contact etch stop layer，CESL)256和层间介电(ILD)层258。接触蚀刻停止层256可以包括氮化硅、氮氧化硅以及/或本领域已知的其他材料，并且可以通过化学气相沉积(CVD)、原子层沉积(ALD)、等离子体辅助化学气相沉积(PECVD)工艺、以及/或其他合适的沉积工艺或氧化工艺来形成。在一些实施例中，接触蚀刻停止层256先顺应性的沉积在工件200上，且层间介电(ILD)层258通过旋转涂布、流动式化学气相沉积(FCVD)、化学气相沉积(CVD)、或其他合适的沉积技术沉积在接触蚀刻停止层256上。层间介电(ILD)层258可以包括例如四乙氧基硅烷(Tetra Ethyl OrthoSilicate，TEOS)氧化物、未掺杂硅酸盐玻璃、或是例如硅酸硼磷硅酸盐玻璃(BPSG)、熔融石英玻璃(FSG)、磷硅玻璃(Phospho-Silicate Glass，PSG)、硼硅玻璃(Boro-SilicateGlass，BSG)之类的掺杂硅氧化物的材料、和/或其他合适的介电材料。在一些实施例中，在形成层间介电(ILD)层258之后，可以对工件200进行退火，以提高层间介电层258的完整性。为了去除多余的材料并暴露出虚置栅极堆叠214的顶面，可以进行一平坦化工艺，例如化学机械研磨(chemical mechanical polishing，CMP)工艺。
参照图1和图14，方法100包括步骤124，其中以一栅极结构(gate structure)260替代虚置栅极堆叠214。步骤124的操作可以包括去除虚置栅极堆叠214、释出作为通道构件2080的通道层208、形成栅极结构260以环绕通道构件2080，并在栅极结构260的上方形成自对准帽盖(self-aligned capping，SAC)层267。虚置栅极叠层214的去除可以包括一个或多个蚀刻工艺，此些蚀刻工艺是对虚置栅极堆叠214中的材料具有选择性。例如，可以使用一选择性湿式蚀刻、选择性干式蚀刻、或前述蚀刻工艺的组合，以进行虚置栅极堆叠214的去除。在去除虚置栅极堆叠214之后，是暴露出通道区210C中的通道层208和牺牲层206的侧壁。之后，选择性的去除通道区210C中的牺牲层206，以释出通道层208作为通道构件2080。在此，由于通道构件2080的尺寸是纳米级的，通道构件2080也可以被称为纳米结构。选择性的去除牺牲层206可以通过选择性干式蚀刻、选择性湿式蚀刻、或其他的选择性蚀刻工艺来实现。在一些实施例中，选择性湿式蚀刻包括APM蚀刻(例如，氨水-过氧化氢-水的混合物)。在一些其他实施例中，选择性去除包括硅锗(SiGe)的氧化，接着是硅锗氧化物的去除。例如，可以通过臭氧清洁来提供氧化，然后可通过例如NH4OH之类的蚀刻剂而去除氧化硅锗。
随着通道构件2080被释出，栅极结构260被沉积以环绕各个通道构件2080，从而形成底部多桥通道(MBC)晶体管300和设置在底部多桥通道(MBC)晶体管300上方的顶部多桥通道(MBC)晶体管400。在一些情况下，栅极结构260可以是一个共同栅极结构(common gatestructure)，以接合底部多桥通道晶体管300和顶部多桥通道晶体管400的通道构件2080。在一些其他情况下，栅极结构260可以包括一底部栅极部分(bottom gate portion)以与底部多桥通道晶体管300的通道构件2080接合，和包括一顶部栅极部分(top gate portion)以与顶部多桥通道晶体管400的通道构件2080接合。在那些其他的情况下，底部栅极部分与顶部栅极部分电性隔离。每个栅极结构260包括与通道构件2080交界的一界面层262(interfacial layer)、一栅极介电层(gate dielectric layer)264、一p型电极层(p-typeelectrode layer)266P和一n型电极层(n-type electrode layer)266N。在一些实施例中，界面层262包括氧化硅，并且可以在一预清洗工艺(pre-clean process)中形成。一示例性的预清洗过程可以包括使用RCA SC-1(氨、过氧化氢和水)和/或RCA SC-2(盐酸、过氧化氢和水)。然后使用原子层沉积(ALD)、化学气相沉积(CVD)以及/或其他合适的方法在界面层262上方沉积栅极介电层264。栅极介电层264由高介电常数的介电材料所形成。如本文所使用和描述的，高介电常数的介电材料包括具有高介电常数的介电材料，例如大于热氧化硅的介电常数(～3.9)。栅极介电层264可以包括氧化铪(hafnium oxide)。或者在其他示例中，栅极介电层264可以包括其他高介电常数的介电质，例如二氧化钛(TiO2)、氧化锆铪(HfZrO)、氧化钽(Ta2O5)、氧化硅铪(HfSiO4)、二氧化锆(ZrO2)、氧化硅锆(ZrSiO2)、氧化镧(La2O3)、氧化铝(Al2O3)、氧化锆(ZrO)、氧化钇(Y2O3)、钛酸锶(SrTiO3；STO)、钛酸钡(BaTiO3；BTO)、锆钡氧化物(BaZrO)、铪镧铪氧化物(HfLaO)、镧硅氧化物(LaSiO)、铝硅氧化物(AlSiO)、铪钽氧化物(HfTaO)、铪钛氧化物(HfTiO)、钛酸锶钡((Ba，Sr)TiO3；BST)、氮化硅(SiN)、氮氧化硅(SiON)、前述的组合、或其他合适的材料。在图14所示的一些实施例中，由较薄的牺牲层引起的小的通道和通道之间的间距(small channel-channel spacing)可能导致栅极介电层264完全填满间距，而选择性的使某些通道构件失效，以作为将底部多桥通道晶体管300与顶部多桥通道晶体管400隔离开来的一种措施。
在沉积栅极介电层264之后，p型电极层266P和n型电极层266N依序的沉积在通道区210C的上方。p型电极层266P和n型电极层266N可以包括一单层或者是多层结构，例如是具有选定功函数的金属层(功函数金属层)、一衬里层(liner layer)、一润湿层(wettinglayer)、一附着层、一金属合金、或一金属硅化物的各种组合，以增强装置的性能。举例来说，p型电极层266P可以包括氮化钛(TiN)、氮化钽(TaN)、钌(Ru)、钼(Mo)、铝(Al)、氮化钨(WN)、硅化锆(ZrSi2)、硅化钼(MoSi2)、硅化钽(TaSi2)、硅化镍(NiSi2)、其他p型功函数材料、或前述的组合。n型电极层266N可以包括钛(Ti)、铝(Al)、银(Ag)、锰(Mn)、锆(Zr)、钛铝(TiAl)、碳化钛铝(TiAlC)、碳化钽(TaC)、碳氮化钽(TaCN)、氮化硅钽(TaSiN)、钽铝(TaAl)、碳化钽铝(TaAlC)、氮化钛铝(TiAlN)、其他n型功函数材料，或前述的组合。为了在p型电极层266P上方形成n型电极层266N，首先沉积p型电极层266P，之后选择性的回蚀以暴露出顶面部分204T中的通道构件2080。然后，沉积n型电极层266N以环绕顶面部分204T中的每个通道构件2080。
步骤124处的操作还可包括在栅极结构260上方形成自对准帽盖(self-alignedcapping，SAC)层267。在一些实施例中，自对准帽盖层267可包括氮化硅(SiN)、碳化硅(SiC)、碳氮化硅(SiCN)、碳氮氧化硅(SiOCN)、碳氧化硅(SiOC)、氮化锆(ZrN)、氮氧化铝(AlON)、碳氮化钽(TaCN)、硅化锆(ZrSi)或金属氧化物。金属氧化物的示例可包括氧化镧(La2O3)、氧化铝(Al2O3)、氧化锌(ZnO)、氧化锌铝(Zr2Al3O9)、氧化钛(TiO2)、氧化钽(TaO2)、氧化锆(ZrO2)、氧化铪(HfO2)、氧化钇(Y2O3)。自对准帽盖层267可以保护栅极结构260以避免用来蚀刻前侧源极/漏极接触开口(frontside source/drain contact openings)(例如下面将描述的第一前侧接触开口268和第二前侧接触开口270)的蚀刻工艺。可以通过使栅极结构凹陷、在凹陷的栅极结构上方沉积一种或多种的介电材料、并且对此一种或多种的介电材料进行化学机械研磨(CMP)工艺来形成自对准帽盖层267。
参照图1、图15和图16，方法100包括步骤126，其中形成第一前侧接触开口(firstfrontside contact opening)268和第二前侧接触开口(second frontside contactopening)270和272。如图15和图16所示，第一前侧接触开口268以及第二前侧接触开口270和272的形成可以包括多个步骤。例如，可以先通过选择性的蚀刻以去除层间介电(ILD)层258。因为层间介电(ILD)层258包括氧化硅，而栅极间隔层220、接触蚀刻停止层256和自对准帽盖(SAC)层267由其他介电材料形成，所以可以使用对氧化硅有选择性的湿式蚀刻工艺或干式蚀刻工艺以选择性的蚀刻层间介电层258。示例性的湿式蚀刻工艺可以包括使用稀释的氢氟酸(diluted hydrofluoric acid，DHF)、缓冲氢氟酸(buffered hydrofluoricacid，BHF)(包括氟化铵和氢氟酸)。示例性的干式蚀刻工艺可以包括使用四氟化碳(CF4)、六氟化硫(SF6)或三氟化氮(NF3)。然后，可以使用非等向性蚀刻工艺来破坏接触蚀刻停止层256，以暴露出第一顶部源极/漏极部件248-1、第二顶部源极/漏极部件248-2以及填充层254。接触蚀刻停止层256可以是包括使用四氟化碳(CF4)、六氟化硫(SF6)、三氟化氮(NF3)或三氟甲烷(CHF3)的干式蚀刻工艺。此时，第一前侧接触开口268形成于第一顶部源极/漏极部件248-1的上方，如图15所示。之后，选择性蚀刻填充层254，以暴露出位于第二顶部源极/漏极部件248-2下方的分隔层242。填充层254的蚀刻工艺可以是非等向性蚀刻工艺，包括使用氧气(O2)、含氟气体(例如CF4、SF6、NF3、CH2F2、CHF3以及/或C2F6)、含氯气体(例如Cl2、CHCl3、CCl4以及/或BCl3)、含溴气体(例如HBr以及/或CHBR3)、含碘气体、其他合适的气体、以及/或等离子体、以及/或前述的组合。应注意的是，由于填充层254的蚀刻工艺对于填充层254是选择性的，所以对于第一顶部源极/漏极部件248-1和第二顶部源极/漏极部件248-2可以保持基本上未蚀刻或未损坏的状态。由于填充层254的成分可以类似于分隔层242的成分，填充层254的干式蚀刻工艺可以将开口延伸穿过分隔层242并进入第二底部源极/漏极部件228-2，从而形成第二前侧接触开口272。如图16所示，第一前侧接触开口268暴露出第一顶部源极/漏极部件248-1。而第二前侧接触开口272不仅暴露出第二顶部源极/漏极部件248-2的侧壁，而且暴露出第二底部源极/漏极部件228-2的顶面。
参照图1和图17，方法100包括步骤128，其中在第一前侧接触开口268中形成一第一前侧接触件(first frontside contact)276，并且在第二前侧接触开口272中形成一第二前侧接触件(second frontside contact)278。在一些实施例中，在步骤128处的操作可以包括形成硅化物层(silicide layers)和沉积一金属填充层(metal fill layer)。在一示例性的工艺中，在工件200之上，包括在第一前侧接触开口268和第二前侧接触开口272之上，沉积金属前驱物。此金属前驱物可以包括钛(Ti)、钽(Ta)、镍(Ni)、钴(Co)或钨(W)。然后进行退火工艺(anneal process)，使金属前驱物与半导体材料(例如第一顶部源极/漏极部件248-1、第二底部源极/漏极部件228-2和第二顶部源极/漏极部件248-2)之间产生硅化反应(silicidation)，从而形成第一硅化物层(first silicide layer)273、第二硅化物层(second silicide layer)274和第三硅化物层(third silicide layer)275。前述硅化物层可以包括钛硅化物(titanium silicide)、钽硅化物(tantalum silicide)、镍硅化物(nickel silicide)、钴硅化物(cobalt silicide)或钨硅化物(tungsten silicide)。可以去除没有变成硅化物的金属前驱物。在形成前述硅化物层之后，金属填充层可以包括钨(W)、钌(Ru)、钴(Co)、镍(Ni)或铜(Cu)。在金属填充层的沉积之后，可以进行化学机械研磨(CMP)工艺以去除多余的材料，并且定义出第一前侧接触件276和第二前侧接触件278。如图17所示，第一前侧接触件276通过第一硅化物层273电性耦接至第一顶部源极/漏极部件248-1；第二前侧接触件278通过第二硅化物层274电性耦接至第二顶部源极/漏极部件248-2；并且第二前侧接触件278通过第三硅化物层275电性耦接至第二底部源极/漏极部件228-2。从附图可以看出，第二前侧接触件278电性耦接底部多桥通道(MBC)晶体管300的第二底部源极/漏极部件228-2，以及电性耦接顶部多桥通道(MBC)晶体管400的第二顶部源极/漏极部件248-2。在此实施例的叙述中，底部多桥通道(MBC)晶体管300是p型，顶部多桥通道(MBC)晶体管400是n型。
参照图1、图18、图19和图20，方法100包括步骤130，其中形成第一背面接触件(first backside contact)286和第二背面接触件(second backside contact)288。可以在工件200的背面朝上的情况下进行步骤130。在一些实施例中，步骤130可以包括减薄基底202，以一背面介电层(backside dielectric layer)280替换基底202(如图18所示)，形成第一背面接触开口(first backside contact opening)281和第二背面接触开口(secondbackside contact opening)282(如图19所示)，以及形成第一背面接触件286和第二背面接触件288(如图20所示)。在一示例性的工艺中，基底202的更换从基底202的减薄开始。在一些情况下，可以使用抛光或化学机械抛光研磨来进行基底减薄。在一些实施例中，基底202被减薄直到隔离部件(未示出)自工件200的背面暴露出为止。在基底202被减薄之后，通过选择性蚀刻工艺选择性地将其去除。一示例性的选择性湿式蚀刻工艺可以包括使用氨(NH3)或合适的湿式蚀刻剂。由于选择性蚀刻的性质，基底202的去除基本上并不会蚀刻第一底部源极/漏极部件228-1、第二底部源极/漏极部件228-2、栅极结构260和最底部的内部间隔物部件226。
在去除基底202之后，可以通过流动式化学气相沉积(FCVD)、化学气相沉积(CVD)、等离子体辅助化学气相沉积(PECVD)、旋转涂布、或合适的工艺在工件200的背面上方沉积背面介电层280，如图18所示。参照图19，形成第一背面接触开口281和第二背面接触开口282，以分别暴露出第一底部源极/漏极部件228-1和第二底部源极/漏极部件228-2的底面。然后，在第一背面接触开口281和第二背面接触开口282中分别形成第一背面接触件286和第二背面接触件288。第一背面接触件286和第二背面接触件288中的各个接触件可以包括一阻挡层(barrier layer)283和背面硅化物层(backside silicide layer)284。在形成第一背面接触件286和第二背面接触件288的示例性工艺中，使用物理气相沉积(PVD)或化学气相沉积(CVD)将金属层沉积在第一底部源极/漏极部件228-1、第二底部源极/漏极部件228-2、第一背面接触开口281的侧壁和第二背面接触开口282的侧壁之上。然后，将金属层氮化形成金属氮化物层(metal nitride layer)。然后，非等向性蚀刻前述的金属氮化物层，以暴露出第一底部源极/漏极部件228-1和第二底部源极/漏极部件228-2，从而形成阻挡层283。在一些实施例中，阻挡层283可以包括氮化钛或氮化钽。然后，在阻挡层283、第一底部源极/漏极部件228-1和第二底部源极/漏极部件228-2上方沉积金属前驱物。进行退火工艺，使金属前驱物与第一底部源极/漏极部件228-1或与第二底部源极/漏极部件228-2之间发生硅化反应，以形成背面硅化物层284。之后，沉积一金属填充层于背面硅化物层284上。在以一化学机械研磨(CMP)工艺去除多余材料之后，形成第一背面接触件286和第二背面接触件288，如图20所示。在一些实施例中，背面硅化物层284可以包括钛硅化物(titanium silicide)、钽硅化物(tantalum silicide)、镍硅化物(nickel silicide)、钴硅化物(cobalt silicide)或钨硅化物(tungsten silicide)。用来形成前述第一背面接触件286和第二背面接触件288的金属填充层可以包括钨(W)、钌(Ru)、钴(Co)、镍(Ni)或铜(Cu)。
本公开的实施例提供了许多优点。本公开提供一种局部的互连结构(localinterconnect structure)，以将一底部多桥通道(MBC)晶体管的一源极/漏极部件耦接到堆叠在底部多桥通道(MBC)晶体管上方的一顶部多桥通道(MBC)晶体管的一源极/漏极部件。虽然本公开的局部的互连结构延伸穿过顶部源极/漏极部件中的间隙(gap)，但是此局部互连结构的形成不包括蚀刻穿过该源极/漏极部件。根据本公开的实施例，是以自对准(self-aligned)的方式形成局部互连结构的开口。
在一个示例性方面，本公开涉及一种半导体装置。此半导体装置包括第一通道构件的堆叠(a stack of first channel members)、直接设置在前述第一通道构件的堆叠上方的第二通道构件的堆叠(a stack of second channel members)、与前述第一通道构件的堆叠接触的一底部源极/漏极部件(bottom source/drain feature)、设置在前述第一通道构件的堆叠上方的一分隔层(separation layer)、与前述第二通道构件的堆叠接触并设置在前述分隔层上方的一顶部源极/漏极部件(top source/drain feature)、以及延伸穿过前述顶部源极/漏极部件和前述分隔层而电性耦接至前述底部源极/漏极部件的一前侧接触件(frontside contact)。
在一些实施例中，前述的前侧接触件与前述第二通道构件的堆叠通过前述顶部源极/漏极部件而相隔开来。在一些实施方式中，半导体装置还可以包括设置在前述的前侧接触件和底部源极/漏极部件之间的第一硅化物部件(first silicide feature)。在一些情况下，半导体装置还可以包括设置在前述的前侧接触和前述顶部源极/漏极部件之间的一第二硅化物部件(second silicide feature)。在一些实施方式中，前述第一通道构件的堆叠设置在一背面介电层(backside dielectric layer)的上方。在一些实施例中，半导体装置还包括设置在前述背面介电层中的一背面接触件(backside contact)，并且前述背面接触件设置在前述底部源极/漏极部件下方并与前述底部源极/漏极部件电性接触。在一些实施方式中，前述底部源极/漏极部件包括硅锗和一p型掺质(p-type dopant)，而前述顶部源极/漏极部件包括硅和一n型掺杂质(n-type dopant)。在一些实施例中，前述分隔层包括氧化硅。在一些实施例中，半导体装置还包括围绕着第一通道构件的堆叠中的每一个通道构件和第二通道构件的堆叠中的每一个通道构件的一栅极结构(gate structure)。
在另一个示例性方面，本公开涉及一种半导体结构。此半导体结构包括一第一底部源极/漏极部件(first bottom source/drain feature)和一第二底部源极/漏极部件(second bottom source/drain feature)、在前述第一底部源极/漏极部件和前述第二底部源极/漏极部件之间延伸的第一通道构件的堆叠(astack of first channel members)、位于前述第一底部源极/漏极部件上方的一第一分隔层(first separation layer)、位于前述第二底部源极/漏极部件上方的一第二分隔层(second separation layer)、设置在前述第一分隔层上方的第一顶部源极/漏极部件(first top source/drain feature)、设置在前述第二分隔层上方的第二顶部源极/漏极部件(second top source/drain feature)、在前述第一顶部源极/漏极部件和前述第二顶部源极/漏极部件之间延伸的第二通道构件的堆叠(a stack of second channel members)、设置在前述第一顶部源极/漏极部件上方并与前述第一顶部源极/漏极部件接触的一第一前侧接触件(first frontside contact)、以及一第二前侧接触件(second frontside contact)，此第二前侧接触件延伸穿过前述第二顶部源极/漏极部件和前述第二分隔层并且与前述第二底部源极/漏极部件接触。
在一些实施例中，前述第一通道构件的堆叠设置在一背面介电层(backsidedielectric layer)的上方。在一些实施方式中，此半导体结构还可以包括一第一背面接触件(first backside contact)和一第二背面接触件(second backside contact)，前述第一背面接触件位于前述第一底部源极/漏极部件的下方并且与前述第一底部源极/漏极部件接触，前述第二背面接触件位于前述第二底部源极/漏极部件的下方并且与前述第二底部源极/漏极部件接触。前述第一背面接触件以及前述第二背面接触件设置在前述背面介电层中。在一些实施方式中，前述第二前侧接触件通过前述第二顶部源极/漏极部件而与前述第二通道构件的堆叠相互间隔开来。在一些情况下，前述第二底部源极/漏极部件包括硅锗和一p型掺质(p-type dopant)，而前述第二顶部源极/漏极部件包括硅和一n型掺质(n-type dopant)。在一些情况下，前述第一分隔层和前述第二分隔层包括氧化硅。
在又一个示例性方面，本公开涉及一种方法。此方法包括提出一工件(workpiece)，此工件包括一基底(substrate)和位于前述基底上方的一堆叠(stack)，前述堆叠包括由多个牺牲层(sacrificial layers)和多个通道层(channel layers)交错设置，前述多个通道层包括多个底部通道层(bottom channel layer)和设置在多个底部通道层之上的多个顶部通道层(top channel layers)。将前述堆叠和前述基底的一部分图案化成一鳍状结构(fin-shaped structure)，前述鳍状结构包括一源极/漏极区(source/drainregion)，使前述源极/漏极区下凹(recessing)以形成源极/漏极凹槽，暴露出前述多个通道层的侧壁，在源极/漏极凹槽中沉积一底部源极/漏极部件(bottom source/drainfeature)以与前述多个底部通道层接触，在前述底部源极/漏极部件上方沉积一分隔层(separation layer)，沉积一顶部源极/漏极部件(top source/drain feature)于前述分隔层的上方并且与前述多个顶部通道层接触，此顶部源极/漏极部件包括一间隙(gap)，此间隙暴露出前述分隔层，在前述间隙中形成一填充层(filler layer)，形成穿过前述填充层和前述分隔层的一接触开口(contact opening)以暴露出前述底部源极/漏极部件，并在前述接触开口中形成一接触件(contact feature)。在一些实施例中，前述填充层的形成包括使用原子层沉积(ALD)来沉积一填充材料(filler material)，并且在前述填充材料的沉积之后，回蚀(etching back)沉积的此填充材料。在一些情况下，前述填充材料包括氧化硅。在一些情况下，前述底部源极/漏极部件包括硅锗和一p型掺质(p-type dopant)，而前述顶部源极/漏极部件包括硅和一n型掺质(n-type dopant)。在一些实施例中，前述接触开口的形成包括使用一选择性蚀刻工艺(selective etch process)来蚀刻前述填充层，而基本上不蚀刻前述顶部源极/漏极部件。
以上概述数个实施例的部件，以便在本发明所属技术领域中技术人员可以更加理解本发明实施例的观点。在本发明所属技术领域中技术人员应理解，他们能轻易地以本发明实施例为基础，设计或修改其他工艺和结构，以达到与在此介绍的实施例相同的目的及/或优势。在本发明所属技术领域中技术人员也应理解，此类等效的结构并无悖离本发明的构思与范围，且他们能在不违背本发明的构思和范围下，做各式各样的改变、取代和替换。因此，本发明的保护范围当视权利要求所界定为准。

Claims (1)

1.一种半导体装置，包括：
一第一通道构件的堆叠；
一第二通道构件的堆叠，该第二通道构件的堆叠直接设置在该第一通道构件的堆叠的上方；
一底部源极/漏极部件，该底部源极/漏极部件与该第一通道构件的堆叠接触；
一分隔层，该分隔层设置在该底部源极/漏极部件的上方；
一顶部源极/漏极部件，该顶部源极/漏极部件与该第二通道构件的堆叠接触并设置在该分隔层的上方；以及
一前侧接触件，该前侧接触件延伸穿过该顶部源极/漏极部件和该分隔层而电性耦接至该底部源极/漏极部件。
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