CN109216428A - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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Publication number
CN109216428A
CN109216428A CN201711344639.1A CN201711344639A CN109216428A CN 109216428 A CN109216428 A CN 109216428A CN 201711344639 A CN201711344639 A CN 201711344639A CN 109216428 A CN109216428 A CN 109216428A
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semiconductor
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fin
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CN109216428B (zh
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沈泽民
吴志强
吴忠政
蔡庆威
程冠伦
王志豪
曹敏
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了一种半导体结构。该半导体结构包括：半导体衬底，具有第一区域和第二区域；第一半导体材料的第一鳍式有源区域，设置在第一区域内，定向为第一方向，其中，第一鳍式有源区域具有沿着第一方向的<100>晶体方向；以及第二半导体材料的第二鳍式有源区域，设置在第二区域内，并且定向为第一方向，其中，第二鳍式有源区域具有沿着第一方向的<110>晶体方向。本发明还提供了半导体结构的制造方法。

Description

半导体结构及其制造方法
技术领域
本发明的实施例一般地涉及半导体技术领域，更具体地，涉及半导体结构及其制造方法。
背景技术
半导体集成电路(IC)工业经历了快速增长。IC材料和设计的技术进步产生了多代IC，其中，每一代都具有比先前一代更小且更复杂的电路。在IC演进过程中，功能密度(即，单位芯片面积中的互连器件的数量)通常在增加，同时几何尺寸(即，可使用制造工艺创建的最小组件(或线))减小。这种规模缩小工艺通常通过增加生产效率和降低相关成本来提供很多益处。
这样的按比例缩小还增加了IC的处理和制造的复杂度，并且要实现的这些进步。需要IC加工和制造方面的类似发展。例如，已经引入诸如鳍式场效应晶体管(FinFET)的三维晶体管以代替平面晶体管。此外，对于器件速度和性能，期望增加载流子迁移率。然而，现有的结构和相关方法不适用于包括FinFET的3D结构。
尽管现有的FINFET器件和制造FINFET器件的方法通常已满足它们的期望目的，但是它们还不能完全满足所有方面的要求。例如，对于包括FinFET的3D结构，特别是对于高迁移率沟道，现有结构和相关方法是不适当的或未被优化。因此，需要一种集成电路结构及其制造方法来解决上述问题。
发明内容
根据本发明的一方面，提供了一种半导体结构，包括：半导体衬底，具有第一区域和第二区域；第一半导体材料的第一鳍式有源区域，设置在所述第一区域内，定向为第一方向，其中，所述第一鳍式有源区域具有沿着所述第一方向的&lt;100&gt;晶体方向；以及第二半导体材料的第二鳍式有源区域，设置在所述第二区域内，并且定向为所述第一方向，其中，所述第二鳍式有源区域具有沿着所述第一方向的&lt;110&gt;晶体方向。
根据本发明的另一方面，提供了一种用于制造半导体结构的方法，包括：接合第一半导体衬底和第二半导体衬底，使得对应的晶体方向&lt;001&gt;具有45度旋转；在所述第二半导体衬底上形成图案化的掩模以覆盖第一区域并且暴露第二区域；蚀刻所述第二区域内的第二半导体衬底以暴露所述第一半导体衬底；在所述第二区域内的第一半导体衬底上外延生长第二半导体材料；以及图案化所述第二半导体衬底和所述第二半导体材料以在所述第一区域中形成第一鳍式有源区域并且在所述第二区域中形成第二鳍式有源区域，其中，所述第一鳍式有源区域定向为第一方向并且具有沿着所述第一方向的晶体方向&lt;100&gt;，其中，所述第二鳍式有源区域定向为所述第一方向并且具有沿着所述第一方向的晶体方向&lt;110&gt;。
根据本发明的又一方面，提供了一种半导体结构，包括：半导体衬底，具有第一区域和第二区域；第一半导体材料的第一鳍式有源区域，设置在所述第一区域内，定向为第一方向，并且通过介电部件与所述半导体衬底隔离，其中，所述第一鳍式有源区域具有沿着所述第一方向的&lt;100&gt;晶体方向；第二半导体材料的第二鳍式有源区域，设置在所述第二区域内，并且定向为所述第一方向，其中，所述第二鳍式有源区域具有沿着所述第一方向的&lt;110&gt;晶体方向；n型鳍式场效应晶体管(NFinFET)，形成在所述第一鳍式有源区域上；以及p型鳍式场效应晶体管(PFinFET)，形成在所述第二鳍式有源区域上。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以最佳地理解本发明的各个方面。应该注意，根据工业中的标准实践，各种部件没有被按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增加或减少。
图1是根据一些实施例的集成电路制造方法的流程图。
图2是根据一些实施例构造的待接合以形成半导体结构的两个半导体衬底的俯视图。
图3是根据一些实施例构造的待接合以形成半导体结构的两个半导体衬底的立体图。
图4是根据一些实施例构造的处于制造阶段中的半导体结构的俯视图。
图5、图6、图7、图8、图9、图10和图11A是根据一些实施例构造的处于各个制造阶段中的半导体结构的截面图。
图11B是根据其他实施例构造的半导体结构的截面图。
图12A是根据一些实施例的半导体结构的部分的俯视图。
图12B是根据一些实施例的半导体结构的部分的立体图。
图13A和图13B是示出根据一些示例构造的半导体结构的实验数据的示图。
具体实施方式
以下公开内容提供了多种不同实施例或实例，以实现本发明的不同特征。以下将描述组件和布置的具体实例以简化本发明。当然，这些仅是示例并且不意欲限制本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例，也可以包括形成在第一部件和第二部件之间的附加部件使得第一部件和第二部件不直接接触的实施例。而且，本发明在各个示例中可以重复参考数字和/或字母。这种重复仅是为了简明和清楚，其自身并不表示所论述的各个实施例和/或配置之间的关系。
此外，为了便于描述，本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等的空间关系术语，以描述如图中所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外，空间关系术语旨在包括器件在使用或操作过程中的不同方位。例如，如果将附图中的器件翻过来，则描述为在其他元件或部件“下部”或“之下”的元件将被定位于在其他元件或部件“上方”。因此，示例性术语“在...下方”可以包括“在...上方”和“在...下方”的方位。装置可以以其他方式定位(旋转90度或在其他方位)，并且在本文中使用的空间关系描述符可以同样地作相应地解释。
本发明涉及但不以其他方式限制于鳍式场效应晶体管(FinFET)器件。例如，FinFET器件可以是包括P型金属氧化物半导体(PMOS)FinFET器件和N型金属氧化物半导体(NMOS)FinFET器件的互补金属氧化物半导体(CMOS)器件。以下公开内容将继续以FinFET实例来说明本发明的各个实施例。然而，应该理解，除了权利要求中特别声明，本申请不应限制于特定类型的器件。
图1是根据一些实施例构造的用于制造半导体结构(具体包括具有一个或多个FinFET器件的FinFET结构)200的方法100的流程图。根据一些实施例，图2是待接合以形成半导体结构200的两个半导体衬底的俯视图；图3是待接合的两个半导体衬底的立体图。图4是制造阶段中的半导体结构200的俯视图。图5至图11B是处于各个制造阶段的半导体结构200的截面图。图12A是半导体结构200的部分的俯视图。图12B是半导体结构200的部分的立体图。图13A和图13B是示出根据一些示例的半导体结构200的实验数据的示图。应该理解，可以在该方法之前、期间和之后实施附加步骤，并且对于该方法的其他实施例，可以替换或删除所描述的一些步骤。参考图1至图13B共同描述半导体结构200及其制造方法100。
如图2中的俯视图所示，方法100开始于两个半导体衬底202和204。特别地，第一半导体衬底202和第二半导体衬底204在晶体结构和平面取向方面相同。在本实施例中，第一半导体衬底202和第二半导体衬底204均为硅衬底，诸如硅晶圆。在本发明的又一实施例中，第一半导体衬底202和第二半导体衬底204是在晶体结构上具有相同平面取向(在本示例中，诸如(100))的硅晶圆。这里(xyz)是表示晶体硅晶圆的顶面的平面取向的米勒指数。因此，如图2所示，半导体衬底202和204的晶体方向&lt;100&gt;分别被定向在相应衬底的顶面中，并被标记为206和208。这里&lt;100&gt;是表示晶体半导体衬底的晶体方向族的另一米勒指数。
尽管在本实施例中两个半导体衬底是硅衬底。然而，所公开的结构和方法不是限制性的，并且可以扩展到其他合适的半导体衬底和其他合适的取向。例如，衬底210可以包括：元素半导体，诸如晶体结构的锗；化合物半导体，诸如硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；或它们的组合。在进一步的实施例中，可以在硅晶圆上外延生长那些半导体材料膜。
参考图1，方法100包括操作102，其中，接合具有取向偏移的两个半导体衬底202和204。在本实施例中，两个衬底202和204以使两个衬底202和204的相同晶体方向(例如&lt;100&gt;)具有45度角的方式接合在一起。下面进一步详细描述操作102。
如图3所示，第一衬底202和第二衬底204旋转并且配置为使得对应的&lt;100&gt;晶体方向在其间具有角度302的偏移。角度302为45度。在本实施例中，如图3所示，第一衬底202的顶面304和第二衬底204的顶面306以两者都面向同一方向的方式进行配置。
通过诸如直接接合、共晶接合、熔融接合、扩散接合、阳极接合或其他合适的接合方法的适当接合技术，两个衬底202和204通过这种配置来将接合在一起。在一个实施例中，衬底通过直接硅接合(DSB)而接合在一起。例如，直接硅接合工艺可以包括预处理、较低温度下的预接合和较高温度下的退火。当两个衬底接合在一起时，可以实施掩埋氧化硅层(BOX)。在一些示例中，通过热氧化在一个接合表面(或两个接合表面：第一衬底202的顶面和第二衬底204的底面)上形成热氧化硅膜。然后将接合表面定位成如以上图3中所述的取向和配置。通过热加热和机械压力将接合表面放置在一起并且接合。热加热可以具有等于或高于1000℃的温度。在接合工艺期间，热加热和机械压力可以具有不同的情形，以优化接合效果。例如，接合工艺可以包括两个步骤：室温下具有机械压力的第一步骤和具有大于1000℃的热退火的第二步骤。在一些示例中，半导体衬底202和204中的至少一个可以在接合之前或之后诸如通过研磨或抛光而减薄至适当厚度。在替代实施例中，可以以使硅表面直接接合在一起的方式来去除掩埋氧化物层。在另一实施例中，热退火温度可以降低至相对较低的温度，诸如介于400℃和450℃之间的温度。
图4中的俯视图示出接合的两个衬底。X和Y方向是笛卡尔坐标并且定义在(100)平面上。第二衬底204的&lt;100&gt;晶体方向208沿Y轴，而第一衬底202的&lt;100&gt;晶体方向206沿X和Y轴之间的对角线方向，其中角度302与Y轴成45度。特别地，第一衬底202具有沿Y轴的晶体方向&lt;110&gt;。
图5是具有接合在一起的第一衬底202和第二衬底204的半导体结构200的截面图。在本实施例中，氧化硅膜502插入在两个衬底之间。同样地，衬底的顶面是(100)取向的，但是第一衬底202相对于第二衬底204具有45°的旋转，使得第一衬底202具有沿Y轴的晶体方向&lt;110&gt;，并且第二衬底204具有沿Y轴的晶体方向&lt;100&gt;。
参考图1和图6，方法100进行到操作104，其中，在半导体结构200的第二衬底204上形成图案化的掩模。半导体结构200包括用于n型场效应晶体管(NFET)的第一区域602和用于p型场效应晶体管(PFET)的第二区域604。图案化的掩模覆盖第一区域602并且包括暴露第二区域604的开口。图案化的掩模可以是软掩模(诸如图案化的抗蚀剂层)或硬掩模(诸如介电材料层)。在本实施例中，使用硬掩模。硬掩模608设置在第二衬底204的顶面上；通过光刻工艺在硬掩模608上形成图案化的抗蚀剂层610；以及刻蚀硬掩模608以将开口从图案化的抗蚀剂层610转移至硬掩模608。在一些示例中，硬掩模608包括随后沉积在半导体结构200上的氧化硅和氮化硅。可以通过热氧化、化学汽相沉积(CVD)、原子层沉积(ALD)、任何其他适当的方法或它们的组合来形成硬掩模608。示例性的光刻工艺可以包括形成抗蚀剂层、通过光刻曝光工艺曝光该抗蚀剂层、进行曝光后烘焙工艺以及显影光刻胶层以形成图案化的光刻胶层。光刻工艺可以替代地替换为其他技术，诸如电子束写入、离子束写入、无掩模图案化或分子印刷。在一些其他实施例中，图案化的抗蚀剂层可以直接用作随后蚀刻工艺的蚀刻掩模。在形成硬掩模608之后，可以通过诸如湿剥离或等离子体灰化的合适的工艺去除图案化的抗蚀剂层610。
参考图1和图7，方法100包括操作106，其中，蚀刻第二区域604中的第二半导体衬底204，直到暴露第二区域604内的第一衬底202，以得到沟槽702。蚀刻工艺被设计为使用硬掩模608作为蚀刻掩模来选择性地去除第二区域604中的半导体材料。蚀刻工艺还可以继续使第一半导体衬底202凹进或确保第二区域604内的第一半导体衬底202暴露。蚀刻工艺可以包括干蚀刻、湿蚀刻或它们的组合。图案化的掩模608保护第一区域602内的第二衬底204以避免蚀刻。在各种示例中，蚀刻工艺包括利用合适的蚀刻剂(诸如含氟蚀刻气体或含氯蚀刻气体，诸如Cl2、CCl2F2、CF4、SF6、NF3、CH2F2或其他合适的蚀刻气体)的干蚀刻。在一些其他示例中，蚀刻工艺包括利用合适的蚀刻剂(诸如KOH溶液)的湿蚀刻。蚀刻工艺可以包括多个步骤。例如，蚀刻工艺可以包括蚀刻第二衬底204的硅材料的第一蚀刻步骤和蚀刻氧化硅层502的第二蚀刻步骤。在进一步的示例中，蚀刻工艺包括干蚀刻步骤(使用含氟蚀刻气体或含氯蚀刻气体)以蚀刻硅以及包括湿蚀刻步骤(使用氢氟酸溶液)以蚀刻氧化硅。在一些实施例中，间隔件704可以形成在沟槽702的侧壁上。间隔件704可以包括沟槽702的侧壁上的介电材料使得沟槽702中随后外延生长的半导体材料可以获得第一半导体衬底202的晶体取向，而不受第二衬底204的影响。此外，间隔件704提供第一区域602与第二区域604之间的隔离。可以通过包括沉积(诸如CVD或PVD)和各向异性蚀刻(诸如干蚀刻)的过程来形成间隔件704。在一些示例中，间隔件704包括氮化硅、氧化硅、氮化钛或它们的组合。
参考图1和图8，方法100进行到操作108，其中，从第二区域604内的第一半导体衬底202外延生长半导体材料802。半导体材料802填充在沟槽702中。在一个实施例中，半导体材料802不同于第二半导体衬底204的半导体材料以实现用于增强的迁移率的应变效应。例如，第二半导体材料802是硅锗(SiGe)。在其他示例中，第二半导体材料802可以是硅(Si)、锗(Ge)或其他合适的元素半导体材料或化合物半导体材料。在一些实施例中，操作108中的外延生长可以包括生长具有不同的半导体材料的多个半导体层的多个步骤，以用于增强的器件性能和其他考虑。在本实施例中，操作108包括硅的第一外延生长以形成硅层804和SiGe的第二外延生长以形成SiGe层802。
参考图1和图9，方法100可以进行到操作110，其中，进行抛光工艺(诸如化学机械抛光(CMP))以平坦化顶面。硬掩模608可以在CMP工艺期间用作抛光停止层，并且在CMP之后通过蚀刻来去除该硬掩模。替代地，可以通过CMP工艺来去除硬掩模608。
半导体层802从半导体层804竖直生长并且基本填充在沟槽702中。在本实施例中，由于存在间隔件704，所以在半导体层802与间隔件704之间可以存在间隙。在这种情况下，操作110中的抛光工艺附加地消除或减小这种间隙。
由于通过从相对于第二半导体衬底204具有旋转的第一半导体衬底202外延生长而形成半导体材料802，所以该半导体材料802具有晶体结构并且获得与第一半导体衬底202的相同晶体取向。例如，第二区域604内的第二半导体材料802的顶面仍处于(100)晶体平面内，而第一区域602内的第二半导体衬底204的顶面也具有(100)晶体平面。然而，由于旋转，这两个区域的晶体方向不同。特别地，第一区域602内的第二半导体衬底204具有沿X和Y轴这两者的&lt;100&gt;晶体方向，而第二区域604内的第二半导体材料802具有沿X和Y轴之间的对角线方向的&lt;100&gt;晶体方向。此外，第二区域604内的第二半导体材料802具有沿X和Y轴定向的晶体方向&lt;110&gt;。
参考图1和图10，方法100可以进行到操作112，其中，在第一区域602内形成鳍式有源区域1002，并且在第二区域604内形成鳍式有源区域1004。鳍式有源区域(或者简称为鳍或鳍部件)是三维(3D)半导体部件，其中，其上形成诸如FET的各种器件。
在一些实施例中，通过包括沉积、光刻和/或蚀刻工艺的任何合适的工艺来形成鳍1002和1004。在一个实施例中，通过图案化半导体结构200(第一区域602中的第二衬底204和第二区域604中的半导体材料802)来形成鳍1002和1004，以形成沟槽。在进一步的实施例中，半导体结构200的图案化可以包括形成硬掩模；以及通过硬掩模的开口将蚀刻工艺应用于半导体结构200以在半导体结构200中形成沟槽。可以通过包括沉积硬掩模材料层和蚀刻硬掩模材料层的过程来形成硬掩模。在一些示例中，硬掩模材料层包括随后沉积在半导体结构200上的氧化硅层和氮化硅层。可以通过热氧化、化学汽相沉积(CVD)、原子层沉积(ALD)或任何其他适当的方法来形成硬掩模材料层。形成图案化的硬掩模的过程还包括通过光刻工艺形成图案化的光刻胶(抗蚀剂)层和通过图案化的抗蚀剂层的开口蚀刻硬掩模材料层以将开口转移至硬掩模材料层。在一些其他的实施例中，图案化的抗蚀剂层可以直接用作蚀刻工艺的蚀刻掩模以形成沟槽。如图10所示，蚀刻工艺可以包括多个步骤，并且可以继续蚀刻穿过第一区域602内的氧化硅层502和第二区域604内的硅层802，从而到达第一半导体衬底202。
第一区域602内的鳍1002可以被称为n型鳍，这是因为其中的半导体材料被适当地掺杂以形成NFET。具体地，半导体材料掺杂有诸如硼的p型掺杂剂。类似地，第二区域604内的鳍1004可以被称为p型鳍部件，这是因为它们最终将被适当地掺杂以形成p型晶体管。具体地，它们将被掺杂有诸如磷的n型掺杂剂。可以通过离子注入或原位掺杂将掺杂剂引入相应的区域。
鳍具有纵长的形状并且在Y方向上定向。特别地，由于上述旋转，所以n型鳍1002具有在Y方向上的晶体方向&lt;100&gt;，而p型鳍1004具有在Y方向上的晶体方向&lt;110&gt;。此外，n型鳍1002的X方向和Y方向都具有晶体方向&lt;100&gt;，并且p型鳍1004的X方向和Y方向都具有晶体方向&lt;110&gt;。另外，如图10所示，n型鳍1002和p型鳍的侧壁表面取向分别为(001)和(110)。
参考图1和图11A，方法100可以进行到操作116，其中，形成浅沟槽隔离(STI)部件1102以隔离各个鳍式有源区域。STI部件1102的形成还可以包括第一操作122，利用一种或多种介电材料填充鳍之间的沟槽；第二操作124，抛光半导体结构200以去除过量的介电材料并平坦化顶面；以及第三操作126，通过选择性蚀刻使STI部件1102凹进。利用介电材料填充沟槽的第二操作124可以包括利用相应介电材料进行填充的一个或多个步骤。例如，利用热氧化工艺在沟槽中形成热氧化硅层，并且通过包括CVD(诸如高密度等离子体CVD(HDPCVD)或可流动CVD(FCVD))的合适的技术在沟槽中填充另一介电材料(诸如氧化硅)。使介电材料凹进的第三操作126可以包括蚀刻工艺(诸如湿蚀刻、干蚀刻、它们的组合)以选择性地回蚀刻介电材料，以得到STI部件1102。
替代地，半导体结构200可以具有不同的结构，例如图11B所示的结构。在图11B的半导体结构200中，鳍式有源区域1004被多个堆叠的纳米线1106取代，因此在纳米线1106中限定多个沟道。根据一些示例，在此进一步描述纳米线1106的形成。在操作108中，外延生长包括外延生长替代半导体材料，诸如Si/SiGe/Si/SiGe。在操作112中，鳍式有源区域的形成包括半导体材料的图案化(如上所述)并且还包括选择性蚀刻工艺以选择性地仅去除一种半导体材料而保留另一种半导体材料，诸如选择性地去除Si(或在替代示例中选择性去除SiGe)，从而形成纳米线1106。因此，诸如FET的各种器件可以形成在图11A的鳍1002/1004上，或替代地，可以形成在图11B的鳍1002和纳米线1106上。
再次参考图1，方法100可以进行到操作118，其中，在第一区域602内的n型鳍1002上形成NFET，而在第二区域604内的p型鳍1004(或纳米线1106)上形成PFET。替代地，在鳍上形成各种半导体器件，诸如FET、偶极子晶体管、二极管、无源器件(电阻器、电感器、电容器或它们的组合)或它们的组合。在图12A和图12B所示的本实施例中，示例性NFET 1202和PFET 1204分别形成在鳍1002和1004上，并且因此被称为鳍式FET(FinFET)。图12A是根据一些实施例的半导体结构200的俯视图并且图12B是其示意图。在图12A和图12B中，为了说明，仅提供第一区域602内的一个n型鳍式FET(NFinFET)1202和第二区域604内的一个p型鳍式PFET(PFinFET)1204。
具体地，NFinFET 1202形成在第一区域602内的鳍1002上。NFinFET 1202包括形成在鳍1002上的源极1206和漏极1208以及置于源极1206与漏极1208之间的栅极1212。类似地，PFinFET 1204形成在第二区域604内的鳍1004上。PFinFET 1204包括位于鳍1004上的源极1222和漏极1224以及置于源极1222与漏极1224之间的栅极1226。
特别地，用于每个FinFET的沟道被限定在置于源极与漏极之间并且在栅极下面的对应鳍的部分中。在本实施例中，NFinFET 1202在鳍1202中具有第一沟道1232，并且PFinFET 1204在鳍1204中具有第二沟道1234。对于NFinFET 1202，载流子(电子)沿着作为晶体方向&lt;100&gt;的方向1236从源极1206通过沟道1232流至漏极1208。对于PFinFET 1204，载流子(空穴)沿着作为晶体方向&lt;110&gt;的方向1238从源极1222通过沟道1234流至漏极1224。通过提供具有带有用于沟道的相应晶体方向的NFinFET和PFinFET的半导体结构200，增强了载流子迁移率和器件性能。
以下进一步描述FinFET的结构和形成。第一区域602中的栅极1212包括设置在沟道上的栅极介电部件和设置在栅极介电部件上的栅电极。栅极还可以包括设置在栅电极的侧壁上的栅极间隔件。栅极介电部件包括栅极介电材料，诸如氧化硅或具有较高介电常数的合适的介电材料(高k介电材料)。在本实施例中，栅极介电部件包括多个介电材料层。例如，栅极介电部件包括诸如氧化硅的界面介电层以及位于界面层上的高k介电材料层。
栅电极包括导电材料层，诸如掺杂的多晶硅、金属、金属合金、金属硅化物或它们的组合。在一些实施例中，栅电极包括多个导电材料层。例如，栅电极包括具有合适的功函的位于栅极介电部件上的第一导电层和位于第一导电层上的第二导电层。在n型FinFET的一个示例中，第一导电层包括钛或钛铝。在另一示例中，第二导电层包括铝、钨、铜、掺杂的多晶硅或它们的组合。
类似地，第二区域604中的栅极1226也包括栅极介电层和栅电极。第二区域604中的栅电极可以具有与第一区域602中的栅极1212类似的结构。然而，导电材料可以不同。例如，在第二区域604中，栅电极包括第一导电材料层(诸如氮化钽或氮化钛)以及第二导电材料层(诸如铝、钨、铜、掺杂多晶硅或它们的组合)。用于NFET和PFET的第一导电层被设计为具有用于优化的阈值电压的不同的功函数。
通过包括各个沉积工艺和图案化的过程来形成栅极(1212或1226)。根据一些实施例还描述了栅极的形成。在一个实施例中，界面层形成在半导体衬底上(特别地，形成在沟道上)。界面层可以包括通过诸如原子层沉积(ALD)、热氧化或紫外线-臭氧氧化的合适的技术所形成的氧化硅。界面层可以具有小于10埃的厚度。高k介电材料层形成在界面层上。高k介电层包括具有介电常数高于热氧化硅的介电常数(约3.9)的介电材料。通过诸如ALD的合适的工艺或其他合适的技术形成高k介电材料层。形成高k介电材料层的其他方法包括金属有机化学汽相沉积(MOCVD)、物理汽相沉积(PVD)、UV-臭氧氧化或分子束外延(MBE)。在一个实施例中，高k介电材料包括HfO2。替代地，高k介电材料层包括金属氮化物、金属硅酸盐或其他金属氧化物。界面层和高k介电材料层组成栅极介电层。
在一些实施例中，栅电极包括多晶硅。通过诸如CVD的合适的技术在栅极介电层上形成多晶硅层。在一个实例中，还可以通过诸如PVD的合适的技术在高k介电材料层和多晶硅层之间形成覆盖层。在一些实例中，覆盖层可以包括氮化钛(TiN)、氮化钽(TaN)或它们的组合。覆盖层可以提供一个或多个功能，诸如阻挡扩散、蚀刻停止和/或保护。
在沉积之后，图案化栅极材料层以形成栅极堆叠件(或多个栅极堆叠件)。栅极堆叠件的图案化包括光刻工艺和蚀刻。光刻工艺形成图案化的光刻胶层。在一个实例中，光刻工艺包括光刻胶涂覆、软烘烤、曝光、曝光后烘烤(PEB)、显影以及硬烘烤。此后，通过使用图案化的光刻胶层作为蚀刻掩模的蚀刻来图案化栅极堆叠件材料层。蚀刻工艺可以包括一个或多个蚀刻步骤。例如，利用不同蚀刻剂的多个蚀刻步骤可以用于蚀刻相应的栅极堆叠件材料层。
在其他实施例中，栅极堆叠件材料层的图案化可以替代地使用硬掩模作为蚀刻掩模。硬掩模可以包括氮化硅、氮氧化硅、氧化硅、其他合适的材料或它们的组合。在栅极堆叠件材料层上沉积硬掩模层。通过光刻工艺在硬掩模层上形成图案化的光刻胶层。然后，穿过图案化的光刻胶层的开口蚀刻硬掩模，从而形成图案化的硬掩模。此后，可以使用诸如湿削离或等离子体灰化的合适的工艺去除图案化的光刻胶层。
栅极间隔件包括介电材料以及可以具有一个或多个膜。在一些实施例中，栅极间隔件包括氧化硅、氮化硅、氮氧化硅、其他合适的介电材料或它们的组合。通过沉积和各向异性蚀刻(诸如干蚀刻)形成栅极间隔件。
在一些实施例中，源极和漏极部件还可以包括通过合适的工艺(诸如离子注入)在鳍部件中形成的轻掺杂的漏极(LDD)部件。LDD部件的掺杂类型与沟道的掺杂类型相反。例如，对于nFET，沟道是p型而LDD部件是n型。在另一示例中，对于pFET，沟道是n型而LDD部件是p型。可以在共同的过程中形成LDD部件和栅极堆叠件。例如，沉积和图案化栅极堆叠件材料层以形成栅极介电层和栅电极层；通过离子注入形成LDD部件，其中，使用伪栅极堆叠件(和STI部件)约束LDD部件；以及然后形成间隔件。在其他实施例中，LDD部件是可选的并且可从半导体结构200去除该LDD部件。
在一些替代实施例中，可以通过栅极替换工艺来形成栅极堆叠件。栅极替换工艺包括形成伪栅极；形成源极和漏极部件；去除伪栅极；之后形成包括高k介电材料的栅极介电层和金属栅电极的最终栅极。在各个实施例中，栅极替换工艺可以是后高k工艺，其中，伪栅极中的栅极介电层和栅电极这两者都被去除并被最终的栅极堆叠件代替。
在一些替代实施例中，源极和漏极部件具有用于应变效应的不同半导体材料，并且可以通过包括以下步骤的过程来形成该源极和漏极部件：通过蚀刻使源极和漏极区域凹进；和通过外延生长利用不同的半导体(不同于沟道材料)填充凹槽。在一些实施例中，选择半导体材料以用于沟道区中的适合的应变效应，使得增强相应的载流子迁移率。例如，用于源极和漏极部件的半导体材料包括碳化硅或硅锗。
可以通过一个或多个离子注入来形成源极和漏极部件。下面以NMOS晶体管为例进行说明，MMOS晶体管的源极和漏极部件的形成是相似的。在一些实施例中，通过离子注入过程来形成用于NMOS晶体管的源极和漏极部件，其中，离子注入过程包括形成LDD部件的第一离子注入和形成S/D部件的第二离子注入。在其他实施例中，栅极堆叠件的形成以及源极和漏极部件的形成被集成在总的过程中。在进一步的实施例中，栅极堆叠件被沉积并被图案化；将第一离子注入应用于鳍式有源区域以形成LDD部件；通过合适的工艺(诸如电介质沉积和干刻蚀)在栅极堆叠件的侧壁上形成栅极间隔件；以及将第二离子注入应用于鳍式有源区域以形成S/D部件。
方法100还包括在上述操作之前、期间和/或之后的其他操作。例如，方法100还包括在半导体结构200上形成层间介电材料(ILD)的操作。ILD包括一种或多种介电材料，诸如氧化硅、低k介电材料或它们的组合。在一些实施例中，ILD的形成包括沉积和CMP。
方法100包括形成多层互连结构以耦合各种器件来形成功能电路的操作。多层互连结构包括竖直互连件(诸如通孔部件或接触部件)以及水平互连件(诸如金属线)。各个互连部件可以实施各种导电材料，包括铜、钨和/或硅化物。在一个实例中，镶嵌和/或双镶嵌工艺用于形成铜相关的多层互连结构。
本发明提供了半导体结构及其制造方法。半导体结构包括用于NFinFET的第一鳍式有源区域和用于PFinFET的第二鳍式有源区域。第一鳍式有源区域和第二鳍式有源区域具有带有不同晶体方向的沟道，特别地，NFinFET的沟道沿晶体方向&lt;100&gt;，PFinFET的沟道沿晶体方向&lt;110&gt;，以用于增强迁移率和器件性能。方法包括接合具有旋转的两个半导体衬底，从而实现上述晶体方向。此外，通过使用用于沟道的硅锗，PFinFET的沟道也产生应变以用于增强的迁移率。
本发明的实施例提供了优于现有技术的优势，但是应当理解，其他实施例可以提供不同的优势，不是所有的优势都必须在本文中进行论述，并且没有特定的优势是所有的实施例都需要的。根据一些示例，如图13A和图13B所示，通过利用所公开的方法和结构，增强了NFinFET的电子迁移率和PFinFET的电子迁移率这两者。图13A示出NFinFET 1202的电子迁移率与对应鳍1202的宽度的实验数据1302。图13B示出PFinFET 1204的电子迁移率与对应鳍1204的宽度的实验数据1304。数据1306是来自具有沿&lt;110&gt;晶体方向的沟道的NFinFET的参考数据，而数据1308是来自不具有硅锗应变的PFinFET的参考数据。从上面的实验数据可以清楚地看出，NFinFET 1202和PFinFET 1204的迁移率都得到增强。特别地，鳍可以被图案化以在部件之间产生相对紧密的间隔，对此，上述公开内容非常适合。另外，根据上面的公开内容，可以处理用于形成FinFET的鳍(也称为芯轴)的间隔件。相反，平面器件的现有方法和结构不能提供优化和增强NFET和PFET这两者的组合。
因此，根据一些实施例，本发明提供了一种半导体结构。该半导体结构包括：半导体衬底，具有第一区域和第二区域；第一鳍式有源区域，具有第一半导体材料，设置在第一区域内，定向为第一方向，其中，第一鳍式有源区域具有沿第一方向的&lt;100&gt;晶体方向；以及第二鳍式有源区域，具有第二半导体材料，设置在第二区域内，并且定向为第一方向，其中，第二鳍式有源区域具有沿第一方向的&lt;110&gt;晶体方向。
在实施例中，半导体结构还包括：n型场效应晶体管(nFET)，形成在所述第一区域内的第一鳍式有源区域上；和p型场效应晶体管(pFET)，形成在所述第二区域内的第二鳍式有源区域上。
在实施例中，所述第一半导体材料是硅，并且所述第二半导体材料是硅锗。
在实施例中，所述第二鳍式有源区域包括具有与介电部件的顶面共面的顶面的硅层。
在实施例中，半导体结构还包括：介电材料层，配置为使所述第一鳍式有源区域与所述半导体衬底隔离，其中，所述介电部件是氧化硅部件。
在实施例中，半导体结构还包括：浅沟槽隔离(STI)部件，形成在半导体衬底中，其中，所述浅沟槽隔离部件具有与所述介电部件的侧壁直接接触的侧壁。
在实施例中，所述浅沟槽隔离部件具有与所述介电部件的顶面共面的顶面，并且所述浅沟槽隔离部件具有位于所述介电部件的底面下方的底面。
在实施例中，所述第一鳍式有源区域和所述第二鳍式有源区域中的每一个都是具有位于(100)晶体平面上的顶面的晶体结构。
在实施例中，所述半导体衬底是具有沿着所述第一方向的晶体取向&lt;001&gt;的硅衬底。
在实施例中，所述半导体衬底是具有沿着所述第一方向的晶体取向&lt;110&gt;的硅衬底。
根据一些实施例，本发明也提供了一种制造半导体结构的方法。该方法包括：接合第一半导体衬底和第二半导体衬底，使得对应的晶体取向&lt;001&gt;具有45度旋转；在第二半导体衬底上形成图案化的掩模以覆盖第一区域并且暴露第二区域；蚀刻第二区域内的第二半导体衬底以暴露第一半导体衬底；在第二区域内的第一半导体衬底上外延生长第二半导体材料；以及图案化第二半导体衬底和第二半导体材料以在第一区域中形成第一鳍式有源区域并且在第二区域中形成第二鳍式有源区域。第一鳍式有源区域定向为第一方向并且具有沿第一方向的晶体取向&lt;100&gt;。第二鳍式有源区域定向为第一方向并且具有沿第一方向的晶体取向&lt;110&gt;。
在实施例中，接合所述第一半导体衬底和所述第二半导体衬底包括通过氧化硅层接合所述第一半导体衬底和所述第二半导体衬底。
在实施例中，蚀刻所述第二区域内的第二半导体衬底包括：进一步蚀刻穿过所述氧化硅层，直到暴露所述第二区域内的第一半导体衬底。
在实施例中，蚀刻所述第二区域内的第二半导体衬底包括：进一步使所述第二区域内的第一半导体衬底凹进。
在实施例中，所述第一半导体衬底和所述第二半导体衬底是硅衬底；并且所述第二区域内的第一半导体衬底上外延生长半导体材料包括外延生长硅锗。
在实施例中，用于制造半导体结构的方法还包括：对所述第二半导体衬底进行第一抛光工艺以形成平坦化的顶面。
在实施例中，图案化所述第二半导体衬底和所述半导体材料包括：在所述第二半导体衬底和所述半导体材料中形成沟槽；利用介电材料填充所述沟槽；进行第二抛光工艺；以及使所述介电材料凹进以形成所述第一鳍式有源区域和所述第二鳍式有源区域。
在实施例中，用于制造半导体结构的方法还包括：在所述第一区域中的第一鳍式有源区域上形成具有负导电性的第一场效应晶体管(FET)，并且在所述第二区域中的第二鳍式有源区域上形成具有正导电性的第二场效应晶体管。
根据一些实施例，本发明提供了一种半导体结构。该半导体结构包括：半导体衬底，具有第一区域和第二区域；第一鳍式有源区域，具有第一半导体材料，设置在第一区域内，定向为第一方向，并且通过介电部件与半导体衬底隔离，其中，第一鳍式有源区域具有沿第一方向的&lt;100&gt;晶体方向；第二鳍式有源区域，具有第二半导体材料，设置在第二区域内，并且定向为第一方向，其中，第二鳍式有源区域具有沿第一方向的&lt;110&gt;晶体方向；n型鳍式场效应晶体管(NFinFET)，形成在第一鳍式有源区域上；以及p型鳍式场效应晶体管(PFinFET)，形成在第二鳍式有源区域上。
在实施例中，所述第一半导体材料是硅，并且所述第二半导体材料是硅锗。
以上论述了若干实施例的部件，使得本领域的技术人员可以更好地理解本发明的各个实施例。本领域技术人员应该理解，可以很容易地使用本发明作为基础来设计或更改其他的处理和结构以用于达到与本发明所介绍实施例相同的目的和/或实现相同优点。本领域技术人员也应该意识到，这些等效结构并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (10)

1.一种半导体结构，包括：
半导体衬底，具有第一区域和第二区域；
第一半导体材料的第一鳍式有源区域，设置在所述第一区域内，定向为第一方向，其中，所述第一鳍式有源区域具有沿着所述第一方向的&lt;100&gt;晶体方向；以及
第二半导体材料的第二鳍式有源区域，设置在所述第二区域内，并且定向为所述第一方向，其中，所述第二鳍式有源区域具有沿着所述第一方向的&lt;110&gt;晶体方向。
2.根据权利要求1所述的半导体结构，还包括：
n型场效应晶体管(nFET)，形成在所述第一区域内的第一鳍式有源区域上；和
p型场效应晶体管(pFET)，形成在所述第二区域内的第二鳍式有源区域上。
3.根据权利要求2所述的半导体结构，其中，所述第一半导体材料是硅，并且所述第二半导体材料是硅锗。
4.根据权利要求3所述的半导体结构，其中，所述第二鳍式有源区域包括具有与介电部件的顶面共面的顶面的硅层。
5.根据权利要求1所述的半导体结构，还包括：介电材料层，配置为使所述第一鳍式有源区域与所述半导体衬底隔离，其中，所述介电部件是氧化硅部件。
6.根据权利要求5所述的半导体结构，还包括：浅沟槽隔离(STI)部件，形成在半导体衬底中，其中，所述浅沟槽隔离部件具有与所述介电部件的侧壁直接接触的侧壁。
7.根据权利要求6所述的半导体结构，其中，所述浅沟槽隔离部件具有与所述介电部件的顶面共面的顶面，并且所述浅沟槽隔离部件具有位于所述介电部件的底面下方的底面。
8.根据权利要求1所述的半导体结构，其中，所述第一鳍式有源区域和所述第二鳍式有源区域中的每一个都是具有位于(100)晶体平面上的顶面的晶体结构。
9.一种用于制造半导体结构的方法，包括：
接合第一半导体衬底和第二半导体衬底，使得对应的晶体方向&lt;001&gt;具有45度旋转；
在所述第二半导体衬底上形成图案化的掩模以覆盖第一区域并且暴露第二区域；
蚀刻所述第二区域内的第二半导体衬底以暴露所述第一半导体衬底；
在所述第二区域内的第一半导体衬底上外延生长第二半导体材料；以及
图案化所述第二半导体衬底和所述第二半导体材料以在所述第一区域中形成第一鳍式有源区域并且在所述第二区域中形成第二鳍式有源区域，其中，所述第一鳍式有源区域定向为第一方向并且具有沿着所述第一方向的晶体方向&lt;100&gt;，其中，所述第二鳍式有源区域定向为所述第一方向并且具有沿着所述第一方向的晶体方向&lt;110&gt;。
10.一种半导体结构，包括：
半导体衬底，具有第一区域和第二区域；
第一半导体材料的第一鳍式有源区域，设置在所述第一区域内，定向为第一方向，并且通过介电部件与所述半导体衬底隔离，其中，所述第一鳍式有源区域具有沿着所述第一方向的&lt;100&gt;晶体方向；
第二半导体材料的第二鳍式有源区域，设置在所述第二区域内，并且定向为所述第一方向，其中，所述第二鳍式有源区域具有沿着所述第一方向的&lt;110&gt;晶体方向；
n型鳍式场效应晶体管(NFinFET)，形成在所述第一鳍式有源区域上；以及
p型鳍式场效应晶体管(PFinFET)，形成在所述第二鳍式有源区域上。
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