WO2005022637A1 - フィン型電界効果トランジスタを有する半導体装置 - Google Patents
フィン型電界効果トランジスタを有する半導体装置 Download PDFInfo
- Publication number
- WO2005022637A1 WO2005022637A1 PCT/JP2004/012385 JP2004012385W WO2005022637A1 WO 2005022637 A1 WO2005022637 A1 WO 2005022637A1 JP 2004012385 W JP2004012385 W JP 2004012385W WO 2005022637 A1 WO2005022637 A1 WO 2005022637A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- effect transistor
- type field
- plane
- field effect
- semiconductor region
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 317
- 230000005669 field effect Effects 0.000 title claims abstract description 148
- 239000013078 crystal Substances 0.000 claims abstract description 220
- 239000000758 substrate Substances 0.000 claims abstract description 175
- 238000000034 method Methods 0.000 claims description 14
- 239000010408 film Substances 0.000 description 98
- 230000037230 mobility Effects 0.000 description 82
- 239000010410 layer Substances 0.000 description 37
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 18
- 229910052710 silicon Inorganic materials 0.000 description 18
- 239000010703 silicon Substances 0.000 description 18
- 238000012546 transfer Methods 0.000 description 18
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 16
- 238000004519 manufacturing process Methods 0.000 description 13
- 238000010586 diagram Methods 0.000 description 9
- 239000012535 impurity Substances 0.000 description 9
- 238000005530 etching Methods 0.000 description 6
- 238000013461 design Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 1
- 241000652704 Balta Species 0.000 description 1
- 229910052691 Erbium Inorganic materials 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- UYAHIZSMUZPPFV-UHFFFAOYSA-N erbium Chemical compound [Er] UYAHIZSMUZPPFV-UHFFFAOYSA-N 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910021339 platinum silicide Inorganic materials 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910052702 rhenium Inorganic materials 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 235000015170 shellfish Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000011029 spinel Substances 0.000 description 1
- 229910052596 spinel Inorganic materials 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- -1 〇 film Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/82385—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
- H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
- H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
- H01L29/7854—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection with rounded corners
Definitions
- the present invention relates to a semiconductor device having a fin-type field-effect transistor having high carrier mobility.
- a fin-type MISFET that has a projection in a semiconductor region and forms a main channel on a plane substantially perpendicular to the substrate (projection side surface) has been used for the purpose of suppressing a short channel effect caused by miniaturization.
- Japanese Patent Application Laid-Open No. 64-8670 discloses a fin-type MISFET in which a part of the protrusion is a part of a silicon wafer substrate and a fin-type MISFET in which a part of the protrusion is a part of a single crystal silicon layer of an SOI substrate.
- a MISFET is disclosed. The former structure will be described with reference to FIG. 12 (a), and the latter structure will be described with reference to FIG. 12 (b).
- a part of the silicon wafer substrate 101 becomes a protrusion 103, and the gate electrode 105 extends on both sides beyond the top of the protrusion 103.
- a channel is formed in a portion below the insulating film 104 below the gate electrode.
- the channel width corresponds to twice the height h of the protrusion 103
- the gate length corresponds to the width L of the gate electrode 105.
- the gate electrode 105 is provided on the insulating film 102 formed in the groove so as to straddle the protrusion 103.
- an S ⁇ I substrate composed of a silicon wafer substrate 111, an insulating film 112 and a silicon single crystal layer is prepared, and the silicon single crystal layer is patterned to form projections 113.
- a gate electrode 115 is provided on the exposed insulating layer 112 so as to straddle the protrusion 113.
- a source region and a drain region are formed in portions on both sides of the gate electrode, and a channel is formed in a portion (the upper surface and side surfaces of the protrusion 113) below the insulating film 114 below the gate electrode.
- the channel width corresponds to the sum of twice the height a of the protrusion 113 and its width b
- the gate length corresponds to the width L of the gate electrode 115.
- a fin-type MISFET is a MISFET having a gate on both sides of a semiconductor region where a channel is formed, and is generally excellent in suppressing a short channel effect. have.
- Japanese Patent Application Laid-Open No. 2002-118255 discloses a fin-type MOSFET having a plurality of semiconductor protrusions (semiconductor layers 213), for example, as shown in FIGS. FIG. 13 (b) is a sectional view taken along line BB of FIG. 13 (a), and FIG. 13 (c) is a sectional view taken along line CC of FIG. 13 (a).
- This fin-type MOSFET has a plurality of semiconductor layers 213 each of which is a part of a metal layer 211 of a silicon substrate 210. These semiconductor layers 213 are arranged in parallel with each other, and straddle the central portion of these protruding semiconductor layers.
- a gate electrode 216 is provided.
- the gate electrode 216 is formed along the side surface of each semiconductor layer 213 from the upper surface of the insulating film 214.
- An insulating film 218 is interposed between each protruding semiconductor layer and the gate electrode, and a channel 215 is formed in the protruding semiconductor layer below the gate electrode.
- a source / drain region is formed in each protruding semiconductor layer, and a high-concentration impurity layer (a punch-through stopper layer) is provided in a region 212 below the source / drain region 217.
- upper wirings 229 and 230 are provided via an interlayer insulating film 226, and each upper wiring is connected to the source / drain region 217 and the gate electrode 216 by each contact plug 228.
- Japanese Patent Application Laid-Open No. 2001-298194 discloses, for example, a fin-type MOSFET as shown in FIGS. 14 (a) and 14 (b).
- This fin-type MOSFET is formed using an SOI substrate including a silicon substrate 301, an insulating layer 302, and a semiconductor layer (single-crystal silicon layer) 303, and a patterned semiconductor layer 303 is provided on the insulating layer 302. Have been.
- a plurality of openings 310 are provided in the semiconductor layer 303 so as to cross the semiconductor layer 303 in a row. These openings 310 are formed so that the insulating layer 302 is exposed when the semiconductor layer 303 is patterned.
- an insulating film is interposed between the semiconductor layers (conduction paths) 332 between the openings 310 along the arrangement direction of the openings 310, and a channel is formed in a conduction path below the gate electrode. It is formed.
- the insulating film on the upper surface of the conduction path 332 is a gate insulating film as thin as the insulating film on the side surface, a channel is formed on both sides and the upper surface of the semiconductor layer 332 under the gate electrode.
- both sides of the row of the opening 310 form source / drain regions 304.
- FIG. 2 shows a view of a semiconductor device in which an n-type MISFET 2001 and a p-type MISFET 2002 having a (001) crystal orientation parallel to the substrate are arranged as viewed from ⁇ 00_1>.
- these MISFETs are placed so that the protruding sides of the n-type MISFET and the p-type MISFET are orthogonal (Fig. 2 (a)) or parallel (Fig. 2 (b)). Let's do it.
- the crystal orientation of the side surface of the n-type MISFET is (-110)
- the crystal orientation of the side surface of the p-type MISFET is (110).
- both the n-type MISFET and the p-type MISFET have a (110) crystal orientation on the side surface of the protrusion.
- an object of one embodiment of the present invention is to optimize carrier transfer characteristics and increase the speed of CMIS.
- Another object of the present invention is to optimize both of the CMIS in consideration of speeding-up and layout requirements.
- the present invention has the following configurations. That is, according to the present invention, a protruding semiconductor region forming a channel on a side surface, a gate electrode provided at least on the side surface via an insulating film, and a semiconductor region formed in the semiconductor region so as to sandwich the gate electrode are formed.
- a semiconductor device comprising an n-type field effect transistor and a p-type field effect transistor having a source region and a drain region,
- the crystal orientation of the protruding semiconductor region constituting the n-type field effect transistor is such that a plane parallel to the substrate is substantially a ⁇ 100 ⁇ plane and a side surface thereof is substantially perpendicular to the ⁇ 100 ⁇ plane. 00 ⁇ plane,
- the crystal orientation of the protruding semiconductor region constituting the p-type field-effect transistor is such that a plane parallel to the substrate is substantially a ⁇ 100 ⁇ plane.
- the present invention provides a semiconductor device, comprising: a protruding semiconductor region forming a channel on a side surface; An n-type field effect transistor and a p-type field effect transistor each including a gate electrode provided with an insulating film interposed therebetween, and a source region and a drain region formed in the semiconductor region so as to sandwich the gate electrode.
- a semiconductor device comprising:
- the crystal orientation of the protruding semiconductor region constituting the P-type field-effect transistor is such that a plane parallel to the substrate is substantially a ⁇ 100 ⁇ plane and a side surface thereof is substantially perpendicular to the ⁇ 100 ⁇ plane. 10 ⁇ plane,
- the crystal orientation of the protruding semiconductor region constituting the n-type field effect transistor is such that a plane parallel to the substrate is substantially a ⁇ 100 ⁇ plane and a side surface thereof is substantially perpendicular to the ⁇ 100 ⁇ plane. 10 ⁇ different from the plane,
- a projecting semiconductor region forming a channel on a side surface, a gate electrode provided at least on the side surface via an insulating film, and a semiconductor region formed in the semiconductor region so as to sandwich the gate electrode are formed.
- a semiconductor device comprising an n-type field effect transistor and a p-type field effect transistor having a source region and a drain region,
- the crystal orientation of the protruding semiconductor region constituting the n-type field effect transistor is such that a plane parallel to the substrate is substantially a ⁇ 100 ⁇ plane and a side surface thereof is substantially perpendicular to the ⁇ 100 ⁇ plane. 00 ⁇ plane,
- the crystal orientation of the protruding semiconductor region constituting the p-type field-effect transistor is such that a plane parallel to the substrate is substantially a ⁇ 100 ⁇ plane, and a side surface thereof is substantially perpendicular to the ⁇ 100 ⁇ plane. 10 ⁇ plane,
- the present invention is directed to a semiconductor device having a protruding semiconductor region forming a channel on a side surface, a gate electrode provided on at least the side surface via an insulating film, and a semiconductor region formed in the semiconductor region so as to sandwich the gate electrode.
- a semiconductor device comprising an n-type field effect transistor and a p-type field effect transistor having a source region and a drain region,
- the side surface of the protruding semiconductor region constituting the P-type field-effect transistor is substantially (10) 0 ⁇ plane
- a projection-shaped semiconductor region forming a channel on a side surface, a gate electrode provided at least on the side surface via an insulating film, and a semiconductor region formed in the semiconductor region so as to sandwich the gate electrode.
- a semiconductor device comprising an n-type field effect transistor and a p-type field effect transistor having a source region and a drain region,
- its side surface is substantially a ⁇ 110 ⁇ plane
- a side surface of the protruding semiconductor region constituting the n-type field effect transistor is substantially orthogonal to the ⁇ 110 ⁇ plane, and a crystal orientation of the side surface is substantially different from the ⁇ 110 ⁇ plane;
- a projecting semiconductor region forming a channel on a side surface, a gate electrode provided on at least the side surface via an insulating film, and a semiconductor region formed in the semiconductor region so as to sandwich the gate electrode.
- a semiconductor device comprising an n-type field effect transistor and a p-type field effect transistor having a source region and a drain region,
- the crystal orientation of the protruding semiconductor region constituting the n-type field effect transistor is such that a plane parallel to the substrate is substantially a ⁇ 110 ⁇ plane and a side surface thereof is substantially perpendicular to the ⁇ 110 ⁇ plane. 00 ⁇ plane,
- the crystal orientation of the protruding semiconductor region forming the p-type field effect transistor is such that a plane parallel to the substrate is substantially a ⁇ 110 ⁇ plane and a side surface thereof is substantially perpendicular to the ⁇ 110 ⁇ plane. 10 ⁇ plane,
- a projecting semiconductor region forming a channel on a side surface, a gate electrode provided on at least the side surface via an insulating film, and a semiconductor region formed in the semiconductor region so as to sandwich the gate electrode are formed.
- a semiconductor device comprising an n-type field effect transistor and a p-type field effect transistor having a source region and a drain region,
- the crystal orientation of the protruding semiconductor region constituting the n-type field effect transistor is such that a plane parallel to the substrate is substantially a ⁇ 100 ⁇ plane, and a side surface thereof is substantially orthogonal to the ⁇ 100 ⁇ plane. Unlike the ⁇ 110 ⁇ face,
- the crystal orientation of the protruding semiconductor region forming the p-type field-effect transistor is such that a plane parallel to the substrate is substantially a ⁇ 100 ⁇ plane, and a side surface thereof is a protruding shape forming the n-type field-effect transistor. Substantially parallel or orthogonal to the side surface of the semiconductor region,
- At least one protruding semiconductor having a ⁇ 100 ⁇ plane (including a plane having an off angle of 10 ° or less) having a crystal orientation of a plane parallel to the substrate and having a channel formed on a side surface.
- a semiconductor device having an n-type field effect transistor and a p-type field effect transistor comprising:
- the projection side surfaces of the n-type field effect transistor and the p-type field effect transistor in the reference state are independently formed by the substrate method. Fixed or rotated at an angle of 0 ° or more and 90 ° or less with the line as the rotation center (except when the rotation angles of the n-type field effect transistor and the p-type field effect transistor are both 0 ° and 90 °)
- the present invention relates to a semiconductor device having a different crystal orientation.
- the present invention provides at least one protruding semiconductor region forming a channel on a side surface, a gate electrode provided via an insulating film so as to straddle a central portion of the semiconductor region, and the semiconductor region A source / drain region electrically connected to at least one of the gate electrode and the source / drain region with the gate electrode interposed therebetween, comprising: an n-type field-effect transistor and a p-type field-effect transistor.
- the crystal orientation of the plane parallel to the substrate of the n-type field-effect transistor and the p-type field-effect transistor (including the plane having an off angle of 10 ° or less) and the crystal orientation of the side surface of the projection are orthogonal to each other.
- the normal state of the projection side surface of the n-type field-effect transistor is used as the center of rotation, and It has a crystal orientation in which the plane parallel to the substrate of the n-type and p-type field-effect transistors and the side surface of the protrusion of the p-type field-effect transistor are fixed or rotated by the same angle within the range of 45 ° to 45 °.
- the present invention relates to a semiconductor device characterized by the above-mentioned.
- the present invention provides at least one protruding semiconductor region forming a channel on a side surface, a gate electrode provided via an insulating film so as to straddle a central portion of the semiconductor region, and the semiconductor region.
- a source / drain region electrically connected to at least one of the gate electrodes and provided with the gate electrode interposed therebetween;
- the crystal orientation of the plane parallel to the substrate of the n-type field-effect transistor and the p-type field-effect transistor (including the plane with an off angle of 10 ° or less) is the ⁇ 100 ⁇ plane, and the crystal orientation of the side face of the projection is the When the ⁇ 100 ⁇ plane and the ⁇ 100 ⁇ plane are perpendicular to each other, respectively, as a reference state,
- the plane parallel to the substrate of the n-type field effect transistor and the p-type field effect transistor in the reference state and the side surface of the projection of the n-type field effect transistor are defined around the normal of the side surface of the projection of the p-type field effect transistor as the rotation center.
- the present invention relates to a semiconductor device having a crystal orientation rotated by the same angle within a range of 90 ° or less.
- the present invention provides a semiconductor region having a protruding shape for forming a channel on a side surface, a gate electrode provided at least on the side surface with an insulating film interposed therebetween, and a semiconductor region formed so as to sandwich the gate electrode.
- a semiconductor device comprising an n-type field effect transistor and a p-type field effect transistor having a source region and a drain region formed,
- the side surface of the protruding semiconductor region constituting the P-type field effect transistor is substantially parallel to the ⁇ 100 ⁇ plane.
- the n-type MISFET and the p-type MISFET have By independently fixing or rotating the normal line of the substrate around the center of rotation, it is possible to optimize the CMIS delay index and the layout of the MISFETs in consideration of the layout. Furthermore, the layout is made easier by rotating the protrusion side surfaces of the n-type MISFET and the p-type MISFET by the same angle while maintaining the arrangement in which the protrusion side surfaces are perpendicular or parallel to each other. At the same time, the CMIS delay index can be reduced.
- the projection side surface of the n-type MISFET, the projection side surface of the p-type MISFET, and the plane parallel to the substrate of these MISFETs are ⁇ 100 ⁇ planes orthogonal to each other. From the reference state, the surface parallel to the substrate of the n-type MISFET and p-type MISFET and the protrusion side of the p-type MISFET are fixed or By rotating the MISFET, the layout of the MISFET can be optimized and high carrier transfer characteristics can be achieved.
- the crystal orientation of the plane parallel to the substrate of the n-type MISFET and the p-type MISFET is the ⁇ 100 ⁇ plane
- the side faces of the protrusions of the n-type MISFET and the p-type MISFET are From the reference state where the crystal orientation of the projection side is the ⁇ 110 ⁇ plane, and these three planes are orthogonal to each other, the n-type Ml SFET and p
- the ⁇ 100 ⁇ plane parallel to the substrate of the n-type MISFET and the p-type MISFET, and the crystal orientation of the projection side surface of the n-type MISFET and the p-type MISFET are From the reference state where they are the same and are arranged so that they are ⁇ 100 ⁇ planes perpendicular to the substrate, the n-type MISFET and p-type MISFET Even if the plane parallel to the MISFET substrate is rotated, a low CMIS delay index and high carrier transfer characteristics can be maintained.
- FIG. 1 (a) is a perspective view showing a semiconductor region according to the present invention and a conventional example.
- FIG. 1B is a perspective view showing a MOS transistor according to the present invention and a conventional example.
- FIG. 2 (a) is a diagram of a conventional orthogonally arranged semiconductor device.
- Figure 2 (b) shows the conventional parallel It is a top view showing the arrangement
- FIG. 3 (a) is a top view illustrating a semiconductor device having an orthogonal arrangement according to the present invention.
- FIG. 3B is a top view illustrating a semiconductor device having a parallel arrangement according to the present invention.
- FIG. 4 (a) is a top view illustrating a semiconductor device having an orthogonal arrangement according to the present invention.
- FIG. 4B is a top view illustrating a semiconductor device having a parallel arrangement according to the present invention.
- FIG. 5 (a) is a top view illustrating a semiconductor device having an orthogonal arrangement according to the present invention.
- FIG. 5B is a top view illustrating a semiconductor device having a parallel arrangement according to the present invention.
- FIG. 6 is a top view illustrating a semiconductor device according to a second embodiment of the present invention.
- FIG. 7 is a top view illustrating a semiconductor device according to a third embodiment of the present invention.
- FIG. 8 (a) is a diagram showing the relationship between the carrier mobility of an n-type MISFET and the crystal orientation of the side surface of the protrusion.
- FIG. 8 (b) is a diagram showing the relationship between the carrier mobility of the p-type MISFET and the crystal orientation on the side surface of the protrusion.
- FIG. 8 (c) is a diagram showing the relationship between the carrier mobility of the p-type MISFET and the crystal orientation of the side surface of the protrusion.
- FIG. 8D is a diagram showing the relationship between the carrier mobility of the n-type MISFET and the crystal orientation on the side surface of the protrusion.
- FIG. 9 is a diagram showing a relationship between a CMIS delay index and a crystal orientation of a protrusion side surface.
- FIG. 10 is a diagram showing a manufacturing process of the semiconductor device according to the present invention.
- FIG. 11 is a view illustrating a process of manufacturing a semiconductor device according to the present invention.
- FIG. 12 (a) is a perspective view showing a conventional MISFET.
- FIG. 12 (b) is a perspective view showing a MISFET of the related art.
- FIG. 13 (a) is a cross-sectional view illustrating a MISFET having a multi-structure.
- FIG. 13B is a cross-sectional view illustrating a multi-structure MISFET.
- FIG. 13C is a cross-sectional view illustrating a MISFET having a multi-structure.
- FIG. 14 (a) is a perspective view showing a MISFET having a multi-structure.
- FIG. 14B is a perspective view showing a multi-structure MISFET.
- FIG. 15 is a sectional view showing a tri-gate type MISFET of the present invention.
- FIG. 16 is a cross-sectional view illustrating a double-gate MISFET of the present invention.
- FIG. 17 is a cross-sectional view of a semiconductor device in which an MISFET of the present invention and a planar MISFET are mixed.
- FIG. 18 is a diagram illustrating crystal orientation and rotation.
- FIG. 19 is a top view showing a multi-structure MISFET of the present invention.
- a channel is formed on the side surface of the semiconductor region. Therefore, it is possible to change the carrier mobility by rotating the crystal orientation of the protruding side surface.
- a fin-type MISFET is formed using a gate insulating film such as SiO
- the interface state can be made smaller by setting the crystal orientation of the side surface of the protruding semiconductor region to the (100) plane than to the (110) plane.
- fin-type MISFETs whose side faces have a (100) crystal orientation can have the same characteristics as conventional planar-type FETs that use a (100) -plane formed substrate. There are advantages such as compatibility and design easiness among them.
- CMIS typically used one by one as a pair has a high carrier mobility.
- CMIS there is also a method of constructing a logic circuit using mainly n-type MISFETs (for example, domino circuits). In this case, it is more advantageous to use n-type MISFETs with high mobility. .
- the present inventors have studied the relationship between the carrier mobility and the crystal orientation of the side surface of the protrusion in the semiconductor region in the fin-type MISFET, and have reached the present invention.
- the present invention changes the crystal orientation of the semiconductor that forms the protruding semiconductor region (the plane parallel to the substrate and / or the side surface of the protuberance), thereby increasing the speed of the n-type MISFET or CMIS. It is intended to make it. It also aims to speed up CMIS and optimize layout requirements.
- a channel is formed on at least a part of the side surface of the protrusion directly below the gate electrode, and the channel forming portion forms a channel region.
- Channel current The flowing direction is parallel to the side surface of the protrusion and parallel to the substrate. Therefore, if the crystal orientation parallel to the substrate and the crystal orientation of the side surface of the protrusion are defined, the direction of the current is uniquely determined except for the direction (positive or negative).
- the side surface of the protrusion is formed so as to be mainly perpendicular to the substrate, but may have a tapered shape in which the width w of the semiconductor region changes from the upper portion to the lower portion of the protrusion.
- the angle between the normal line of the substrate and the side surface of the protrusion is preferably 10 ° or less.
- the angle formed by the side surface of the protrusion and the normal line of the substrate is within this range, it can be regarded as having the same characteristics as when the side surface of the protrusion is perpendicular to the substrate.
- the term “having a substantially predetermined crystal orientation” regarding the crystal orientation of the side surface of the protrusion refers to not only the case where the side surface of the protrusion is perpendicular to the substrate but also the above-described case. It also includes the case where it has a tapered shape within 10 °.
- the "projecting semiconductor region” may have any shape as a whole as long as a surface substantially perpendicular to the substrate surface can be used as a channel region.
- the crystal orientation is defined by the orientation (including the crystal orientation on the side surface of the projection), particularly in the channel region in the projection-like semiconductor region. Therefore, the source and drain regions may have any shape and may have any crystal orientation. Therefore, in the present invention, the “projection side surface” means only the side surface on which the channel is formed in the protruding semiconductor region.
- the protruding semiconductor region may be protruded from the substrate so as to have a side surface on which a channel can be formed.
- the protruded semiconductor region protrudes above an insulating film separating the semiconductor layer forming an element from the substrate. I have.
- a main channel is formed on the side surface of the protruding semiconductor region.
- a channel may or may not be formed on the upper surface (the surface parallel to the substrate) of the protruding semiconductor region.
- FIG. 15 shows an example of a cross-sectional shape of a protruding semiconductor region in which a channel is formed on the upper surface
- FIG. 16 shows an example of a cross-sectional shape of a protruding semiconductor region in which a channel is not formed on the upper surface.
- FIGS. 15 (b)-(d) and 16 (b)-(d) show examples of a Fin-type MISFET having a gate electrode having a structure different from the above-described embodiment.
- FIGS. 15 and 16 correspond to the cross-sectional view of FIG. 1 (b).
- FIGS. 15 and 16 correspond to the cross-sectional view of FIG. 1 (b).
- 15B and 16B show a structure in which the lower end of the gate electrode 1005 is located below the lower end of the semiconductor region 1003. This structure is similar to the Greek letter “ ⁇ ”, and is therefore called the “ ⁇ gate structure”.
- the gate electrode extends to a position lower than the protruding semiconductor region, the control of the channel by the gate electrode is strengthened, the sharpness of the on / off transition (subthreshold characteristic) is improved, and the off current is suppressed. be able to.
- FIGS. 15 (c) and 16 (c) show a structure in which a gate electrode 1005 is partly provided on the lower surface side of the semiconductor region 1003 (the gate electrode covers a part of the lower surface of the protruding semiconductor region).
- the structure extends like this.
- This structure is called the “0 gate structure” because the gate electrode resembles the Greek letter “ ⁇ ”.
- the control of the channel by the gate electrode is further strengthened, and the lower surface of the semiconductor region can be used as the channel, so that the driving capability can be improved.
- FIGS. 15D and 16D show a structure in which the gate electrode 1005 completely extends to the lower surface side of the semiconductor region 1003.
- This structure is such that the semiconductor region floats in the air below the gate with respect to the plane of the base under the gate, and is called a “gate-all-around” (GAA) structure.
- GAA gate-all-around
- the lower surface of the semiconductor region can also be used as a channel, so that driving capability can be improved and short channel characteristics can be improved.
- single crystal silicon can be preferably used, and, in addition, silicon'germanium and germanium can be preferably used.
- a multilayer film of the above materials can be used as necessary.
- a silicon substrate was used as the substrate under the base insulating film.
- the present invention can be implemented if there is an insulating film below the semiconductor region.
- a structure in which the insulator itself under the semiconductor region serves as a support substrate such as S ⁇ S (silicon-on-sapphire, silicon-on-spinel), can be mentioned.
- the insulating support substrate include quartz and A1N substrates in addition to the above SOS.
- a conductor having desired conductivity and work function can be used as a material for the gate electrode.
- a conductor having desired conductivity and work function can be used.
- Silicide compounds As the structure of the gate electrode, a stacked structure of a stacked film of a semiconductor and a metal film, a stacked film of metal films, a stacked film of a semiconductor and a silicide film, and the like can be used in addition to a single crystal film.
- the gate insulating film an SiO film or a Si ⁇ ⁇ ⁇ N film can be used.
- a body insulating film may be used.
- the High-K film for example, TaO film, A1
- Metal oxides such as ⁇ film, La O film, Hf ⁇ film, Zr ⁇ film, HfSi ⁇ , ZrSi ⁇ , HfAl ⁇ , Zr
- a composite metal oxide represented by a composition formula such as Al ⁇ can be given.
- the gate insulating film may have a laminated structure.
- the present invention relates to selection of a crystal orientation of a protruding semiconductor region.
- the crystal orientation of a semiconductor region forming Fin is expressed as the orientation of a Fin arranged in a crystal coordinate system. This may be interpreted as that the Fin is cut out of the crystal in such a direction.
- the normal of the plane parallel to the substrate is drawn as shown in Fig. 18 (a).
- the fins are arranged in the crystal coordinate system so that the 001> direction and the normal of the plane parallel to the channel are 110> directions, which corresponds to the state where the Fin is placed in the crystal coordinate system (the hatched surface is parallel to the substrate).
- “rotate” means to change the crystal orientation of Fin based on the above-described expression method by rotating Fin in a crystal coordinate system that is not the rotation of the entity in real space. For example, turning from the state of Fig. 18 (a) by 45 degrees clockwise around the 001> axis is the transition from Fig. 18 (a) to the state of 18 (b) in the figure. However, this means that the plane parallel to the substrate does not change from (001), and the plane parallel to the channel changes to (010).
- the upper portion of the protrusion forms a plane parallel to the substrate.
- the source region other than the channel region In the Z drain region, the width may be wide due to a contact or the like.
- the channel may be further formed above the protrusion. In this case, since the channel is formed on the three sides of the projection side and the top, the controllability by the gate is improved.
- FIG. 1A is a perspective view showing a protruding semiconductor region provided on an insulator
- FIG. 1B is a perspective view showing a MISFET.
- an insulator 1002 which also has Si force is provided on a semiconductor substrate 1001, and a projection-like half is further provided on the insulator 1002.
- a conductor region 1003 is provided.
- the semiconductor region 1003 has a channel region (projection side surface) 1008.
- the semiconductor region has a rectangular parallelepiped shape.
- a channel region and a source / drain region are formed.
- a gate insulating film 1004 is provided on the top and side surfaces of the semiconductor region 1003, and a gate electrode 1005 is provided across the semiconductor region 1003 where the gate insulating film 1004 is formed on the surface.
- a main channel region 1008 is formed in a part of the protruding semiconductor region 1003.
- the portions of the semiconductor region 1003 on both sides of the gate electrode 1005 constitute a source region 1006 / drain region 1007 into which a high concentration impurity is introduced.
- the MISFET may have a multi-structure having a plurality of independent channel regions.
- a semiconductor layer 213, a channel 215, and a source Z drain region 217 projecting above the insulating film 214 are formed.
- the gate is common to a plurality of channels, and the source and drain regions are connected to each other by wiring.
- a channel region and a source Z drain region (304, 332) are formed in a semiconductor layer 303 projecting above the insulating film 302.
- the source / drain region 304 is a region provided in common for a plurality of channel regions.
- FIG. 3 is a simplified top view of FIG.
- a pair of source / drain regions 401 shared by each semiconductor layer is provided.
- a pair of source / drain regions 401 are provided independently in each semiconductor layer.
- the fin-type MISFET of the present invention has the same structure as a conventional fin-type MISFET in that a protruding semiconductor region is provided on a substrate and a channel is formed on a side surface of the semiconductor region. However, it differs from the conventional fin-type MISFET in that the crystal orientation of the protruding semiconductor region is different and the carrier transfer characteristics are improved.
- the semiconductor region is a part of the semiconductor substrate 1001 as shown in FIG. 12 (a)
- the silicon single crystal layer of the S ⁇ I substrate as shown in FIG. 12 (b) Even good. In either case, it protrudes above the insulating layer (insulating film 102 in FIG. 12 (a) and insulating film 112 in FIG. 12 (b)) that separates the region where the substrate and the element are formed. And a side surface on which a channel can be formed.
- a part of the semiconductor substrate 1001 and a part of the silicon single crystal layer of the SOI substrate may be mixed on the same semiconductor substrate.
- the crystal orientation of the protruding semiconductor region 1003 affects the carrier mobility, but the crystal orientation of the substrate 1001 is independent of the carrier mobility. Therefore, the crystal orientation of the protruding semiconductor region 1003 does not have to match the crystal orientation of the substrate 1001.
- the plane parallel to the substrate in the semiconductor area may be different from the crystal orientation of the substrate.
- the “plane parallel to the substrate” refers to the crystal orientation of the semiconductor crystal forming the protruding semiconductor region 1003, or more strictly, the channel region 1008, and does not mean the crystal orientation of the substrate 1001. Absent.
- a plurality of protruding semiconductor regions are formed as a part of a semiconductor single crystal substrate or by processing a silicon single crystal layer of an SOI substrate.
- the crystal orientation is uniform between the regions.
- Such a protruding semiconductor region is When used to construct a CMIS, p-type MISFETs and n-type MISFETs are formed in a projecting crystal with a uniform orientation. Therefore, in the p-type MISFET and the n-type MISFET, the crystal orientation of the plane parallel to each substrate is the same plane.
- the width of the semiconductor region (representing the length of the protruding semiconductor region in the direction parallel to the substrate) is such that the entire protruding region where the channel is formed is depleted. If b in FIGS. 1 and 12 (b) and t in FIG. 12 (a) are reduced, a fully depleted MIS FET can be obtained. Finned MISFETs may or may not be fully depleted. Further, the semiconductor region may or may not be appropriately doped with impurities.
- the n-type field effect transistor and the p-type field effect transistor included in the semiconductor device of the present invention are typically used as a CMIS circuit in pairs each having substantially the same number. It is also possible to use a field effect transistor of one conductivity type (eg, n-type) mainly and a field effect transistor of the other conductivity type (eg, p-type) in a circuit which is used as an auxiliary. Further, the present invention includes a CMIS and other circuits having the above-described crystal orientation relationship in at least a part of a semiconductor device (chip).
- the semiconductor device of the present invention may have two or more CMISs.
- the MISFETs can be arranged at orthogonal and / or parallel positions, so that the layout is easy, and a large number of MISFETs can be arranged with a small area. Therefore, high integration of the semiconductor device can be achieved.
- the plane parallel to the substrate of the n-type MISFET and the p-type MISFET is a ⁇ 100 ⁇ plane (including a plane having an off angle of 10 ° or less).
- the n-type MISFET and the p-type The ET is fixed or rotated independently at an angle of 0 ° or more and 90 ° or less with respect to the normal line of the substrate, with the side surfaces of the MISFET in the standard state fixed with the surface parallel to the substrate fixed.
- rotate the side surface of the protrusion means in the real space. It does not mean substantial rotation in the MISFET.
- the fins arranged in the crystal coordinate system are rotated in the crystal coordinate system while the crystal orientation of the plane parallel to the substrate of the MISFET is fixed. Indicates that the crystal orientation is changed. That is, it means that the protruding semiconductor region is formed so as to have a side surface having such a current direction.
- the mobility data used in the present invention was measured using a commercially available semiconductor parameter analyzer.
- the measurement conditions were a drain voltage of 0.05 V and a substrate voltage of 0 V based on the source voltage.
- the gate voltage was finely adjusted for each sample so that the vertical effective electric field Eeff applied to the channel was 10 MV / cm, and was set to approximately 1.35 V.
- Eeff vertical effective electric field
- E e f f (V gs + V th) / 6 T O x.
- Vgs gate voltage
- Vth threshold voltage
- Tox gate oxide film thickness.
- the delay index is an index for evaluating the carrier transfer characteristic of CMIS, and was calculated by the following equation.
- the delay index is a unitless number obtained by standardizing all the mobilities measured by the above method with the mobility (240 cm 2 ZV * s) of an n-type MISFET in which the side surfaces of the protruding semiconductor region are ⁇ 100 ⁇ planes.
- the plane parallel to the MISFET substrate may be any of the (100), (010), and (001) planes.
- the side surface of the protrusion of the MISF ET is perpendicular to the substrate, and the n-type MISFET and p-type MISFET When the rotation angles of the side surfaces of the protrusion are the same, the mobility becomes the same due to the symmetry of the silicon crystal.
- the crystal orientation of the plane parallel to the substrate of the MISFET is the (100) plane
- the crystal orientation of the projection side surface of the n-type MISF ET and the p-type MISFET is changed to the (0-11) plane and the Z or ( 011)
- the arrangement as a plane is in a reference state, and the protrusion side surface of the MISFET is rotated around ⁇ 100> as a rotation center.
- the crystal orientation of the plane parallel to the substrate of the MISFET is the (010) plane
- the crystal orientation of the projection side surface of the n-type Ml SFET and the p-type MISFET is the (10_1) plane and / or the (101) plane.
- the arrangement is in the reference state, and the MISFET is rotated about the protrusion side face 010> as the center of rotation.
- the n-type Ml SFET and p-type MISFET have the (110) and / or (110) plane crystal orientations on the side surfaces of the protrusions.
- the MISFET is rotated around the protrusion side surface 001> as the center of rotation.
- the crystal orientation of the plane parallel to the substrate of the MISFET is not changed by the rotation of the projection side.
- the projection side surface of the MISFET has a normal line of the substrate as a four-fold symmetry axis. Therefore, when the rotation angle of the side surface of the projection of the MISFET becomes 90 °, the mobility becomes the same as that in the reference state. When the rotation angle is further increased from 90 °, the mobility decreases from 0 ° to a force of 90 °. It shows the same behavior as when it is increased. Therefore, when the rotation angle of the projection side surface of the MISFET is 0 ° or more and 90 ° or less, movement of all the rotation angles (0-360 °) can be represented.
- Figure 2 (a) shows the reference state when n-type MISFETs and p-type MISFETs are vertically arranged with the crystal orientation of the plane parallel to the substrate being the (001) plane and the case where they are arranged in parallel.
- the reference state is shown in Fig. 2 (b).
- FIGS. 2 (a) and 2 (b) are views of these MISFETs as viewed from the top.
- the projection side surfaces of the n-type MISFET 2001 and the p-type MISFET 2002 are changed from the reference state of FIGS. 2 (a) and 2 (b) as shown in FIGS. 3 (a) and 3 (b).
- ⁇ 001> as the rotation center, fix or rotate independently at an angle of 0 ° or more and 90 ° or less.
- FIGS. Fig. 8 (a) shows the relationship between the carrier mobility and the crystal orientation of the n-type MISFET
- Fig. 8 (b) shows the relationship between the carrier mobility and the crystal orientation of the p-type MISFET
- Fig. 9 shows the delay characteristic of the CMIS. It shows the relationship between the target and the crystal orientation.
- FIG. 2 (a) and 2 (b) The mobility of the arrangement (conventional CMIS) in Figs. 2 (a) and 2 (b) is represented by a point (A) in Fig. 8 (a) and a point (D) in Fig. 8 (b). .
- the measured CMIS delay index is 8.8 from Fig. 9.
- Figs. 3 (a) and 3 (b) when the projecting sides of the n-type MISFET and the p-type MISFET are rotated up to 90 °, the mobility of the n-type MISFET becomes After a monotonous increase from point (a) to point (B), it reaches point (C).
- the mobility of the p-type MISFET is from point (D) to point (E) in Fig. 8 (b). After a monotonous decrease, it reaches point (F), where points (A) and (D) are the mobility in the reference state, and points (C) and (F) are the movement when the rotation angle of the side of the protrusion is 90 °.
- the mobility of points (A) and (C) and the mobility of points (D) and (F) are the same due to crystal symmetry.
- the rotation angles of the projection side surfaces of the n-type MISFET and the p-type MISFET may be the same or different. Alternatively, only one of the side surfaces of the n-type MISFET and the p-type MISFET may be rotated, and the other side surface may be fixed. However, this does not include the case where both the n-type MISFET and the p-type MISFET are fixed at the reference state and the case where both sides are rotated 90 ° from the reference state. In this case, because of the symmetry of the silicon crystal, the mobility is the same as that of the conventional MISFET corresponding to the arrangement of FIGS. 2 (a) and 2 (b).
- the projection side surfaces of the n-type MISFET and the p-type MISFET are rotated by the same angle while maintaining the orthogonal or parallel arrangement of the projection side surfaces.
- the layout of these MISFETs is easy and the delay index of the CMIS can be reduced.
- FIGS. 4 (a) and 4 (b) show views of the semiconductor device from the perspective of FIG.
- the crystal orientation on the side surface of the n-type MISFET 2001 is (010)
- the crystal orientation on the side surface of the p-type MISFET 2002 is (100).
- the crystal orientations of the side surfaces of the protrusions of the n-type MISFET 2001 and the p-type Ml SFET 2002 are both (010) planes.
- the mobilities of the n-type MISFET and the p-type MISFET are represented by a point (B) in FIG. 8A and a point (E) in FIG. 8B.
- the state at point (B) shows that the mobility of the n-type MISFET is higher than in the reference state (point (A)), and the measured CMIS delay index From Fig. 9 decreased from 8.8 (standard condition) to 8.5. Therefore, the carrier transfer characteristics of the CMIS are improved as compared with the conventional CMIS. Further, since the n-type MISFET and the p-type MISFET are arranged so that the side surfaces of the protrusions are perpendicular or parallel to each other, the layout of the MISFET becomes easy and the layout of the MISFET can be optimized.
- the mobility of the p-type MISFET becomes as shown in FIG. It is fixed to the point (D) in the middle or exists near the point (D), and shows high mobility.
- the projection side of the n-type MISFET is rotated at an angle of 90 ° or less while keeping the projection side of the p-type MISFET in this way, the mobility passes from point (A) to point (B) in Fig. 8 (a).
- point (C) Therefore, the mobility of the n-type MISFET can be increased as compared with the reference state.
- the delay index of the CMIS can be made smaller than that of the reference state, and the carrier transfer characteristic of the CMIS is improved as compared with the conventional CMIS.
- the protrusion side surfaces of the n-type MISFET and the p-type MISFET are rotated at an angle at which the mobility of the n-type MISFET and the p-type MISFET is in a preferable range.
- the protrusion side surface of the p-type MISFET is fixed or rotated at an angle of 0 ° or more and 10 ° or less from the reference state, and the rotation angle of the protrusion side surface of the n-type MISFET is 45 °.
- FIG. 2A The semiconductor device having this arrangement in which the arrangement shown in FIGS. 2A and 2B is set as a reference state is shown in FIG. 2B
- Figures 5 (a) and 5 (b) show the side view of the projection of the p-type MISFET. Fixed).
- the crystal orientation of the side surface of the protrusion of the n-type MISFET 2001 is a (010) plane
- the crystal orientation of the side surface of the protrusion of the p-type MISFET 2002 is a (110) plane.
- the crystal orientation of the side surface of the n-type MISFET 2001 is (010)
- the crystal orientation of the side surface of the p-type MISFET 2002 is (110).
- the mobility of the n-type MISFET is represented by point (B) in FIG. 8 (a)
- the mobility of the p-type MISFET is represented by point (D) in FIG. 8 (b).
- the mobility of the n-type MISFET is higher than that in the reference state (point (A)), and the mobility of the p-type MISFET is the same as that of the point (D). is there. Therefore, the measured CMIS delay index decreases from 8.8 (reference state) to 4.7 in Fig. 9, and the carrier transfer characteristics of the CMIS are improved compared to the conventional CMIS.
- the arrangement shown in FIGS. 5 (a) and 5 (b) can be obtained from the arrangement shown in FIGS. 2 (a) and 2 (b) by one or more rotations of the projecting side surface.
- FIGS. 2 (a) and (b) only the protrusion side surfaces of the n-type MISFET are rotated by 45 °, so that the arrangements of FIGS. 5 (a) and (b) can be obtained.
- the mobility of the n-type MISFET moves from point (A) to point (B) through FIG. 8 (a).
- the mobility of the p-type MISFET does not move from the point (D) in Fig. 8 (b).
- FIGS. 4 (a) and 4 (b) After the arrangement of FIGS. 4 (a) and 4 (b) is made by rotating the projection side from the arrangement of FIGS. 2 (a) and 2 (b), the projection side of the p-type MISFET is further rotated by 45 °. By doing so, the arrangement shown in Figs. 5 (a) and 5 (b) can be adopted. In this case, the mobility of the n-type MISFET moves from point (A) to point (B) on Fig. 8 (a). On the other hand, for example, when obtaining the state shown in FIG. 5 (b), the mobility of the p-type MISFET moves from point (D) to point (E) on FIG. 8 (b) (see FIG. 2 to FIG. 2).
- the crystal orientation of the plane parallel to the substrate of the n-type and p-type MISFETs is the ⁇ 100 ⁇ plane.
- the crystal orientation of the protruding semiconductor region of the n-type MISFET is a ⁇ 100 ⁇ plane whose side surface is substantially orthogonal to a plane substantially parallel to the substrate.
- Fig. 8 (a) The mobility of the n-type MISFET is maximized. Therefore, regardless of the crystal orientation on the side of the projecting semiconductor region of the p-type MISFET, the crystal orientation on the side of the projecting semiconductor region of the n-type MISFET and the p-type MISFET is substantially ⁇ 110 ⁇ .
- the CMIS delay index is lower than in the case of ⁇ . Therefore, it is possible to obtain a CMIS having excellent carrier transfer characteristics.
- the crystal orientation of the protruding semiconductor region of the p-type MISFET is a ⁇ 110 ⁇ plane whose side surface is substantially orthogonal to a plane substantially parallel to the substrate, and that of the protruding semiconductor region of the n-type MISFET.
- the crystal orientation should be different from this ⁇ 110 ⁇ plane.
- the mobility of the p-type MISF ET becomes the maximum value from FIG. 8 (b).
- the mobility of the n-type MISFET is not the lowest value (points (A) and (C) in FIG. 8A).
- the delay index of the CMIS is lower than in the case where the crystal orientations of both sides of the protruding semiconductor region of the n-type MISFET and the p-type Ml SFET are substantially ⁇ 110 ⁇ planes. Therefore, it is possible to obtain CMIS with excellent carrier transfer characteristics.
- the crystal orientation of the side surface of the protruding semiconductor region of the n-type MISFET is a ⁇ 100 ⁇ plane that is substantially orthogonal to a plane parallel to the substrate, and the protruding semiconductor region of the p-type MISFET is The crystal orientation of the side surface is preferably a ⁇ 110 ⁇ plane orthogonal to a plane substantially parallel to the substrate.
- the mobility of the n-type MISFET and the p-type MISFET has the maximum value from FIGS. 8 (a) and 8 (b), so the CMIS delay index is low, and a CMIS with excellent carrier mobility is obtained. That can be S.
- FIG. 17 shows an example of a structure in which a fin transistor and a planar transistor are mixed.
- the n-type MISFET and the p-type MISFET have a crystal orientation of a plane parallel to the substrate (including a plane having an off angle of 10 ° or less) and an n-type MISFET.
- the reference state is a state in which the crystal orientation of the side surface of the protrusion of T and the crystal orientation of the side surface of the protrusion of the ⁇ -type MISFET are ⁇ 100 ⁇ planes perpendicular to each other.
- the surface parallel to the ⁇ -type MISFET and the ⁇ -type MISFET substrate and the side surface of the p-type MISFET are more than 45 ° and less than 45 ° It is equivalent to one fixed or rotated at an angle of.
- ⁇ rotate '' refers to rotating Fin in the crystal coordinate system while keeping the relative crystal orientation of the n-type MISFET and p-type MISFET fixed, rather than the rotation of the entity in the real space. This means changing the crystal orientation of the Fin. That is, it means that the protruding semiconductor region is formed to have such a side surface in the current direction.
- CMIS can have a high carrier mobility characteristic.
- the n-type MISFET and the p-type MISFET are arranged such that the side surfaces of the protrusions are orthogonal to each other, it is possible to design an optimal arrangement that facilitates the layout of the MISFET.
- the plane parallel to the substrate of the MISFET in the reference state may be any of the (100) plane, the (010) plane, and the (001) plane. Regardless of the plane parallel to the substrate, the crystal orientation of the plane parallel to the substrate of the n-type MISFET and p-type MISFET (including planes with an off angle of 10 ° or less). Also, the crystal orientations of the side surfaces of the protrusions are ⁇ 100 ⁇ planes orthogonal to each other, and these planes are equivalent due to crystal symmetry.
- the crystal orientation of the plane parallel to the MISFET substrate is the (100) plane
- the crystal orientation of the projection side surface of the n-type MISFET is the (001) plane
- the crystal orientation of the projection side surface of the p-type MISFET is (010).
- 001> is the center of rotation.
- the crystal orientation of the plane parallel to the MISFET substrate is the (010) plane
- the crystal orientation of the n-type MISFET projection side is the (100) plane
- the crystal orientation of the p-type MISF ET projection side is the (001) plane.
- 100> is the center of rotation.
- the crystal orientation of the plane parallel to the MISFET substrate is the (001) plane
- the crystal orientation of the projection side of the n-type MISFET is the (010) plane
- the crystal orientation of the projection side of the p-type MISFET is the (100) plane.
- 010> becomes the center of rotation.
- the projection side surface of the p-type MISFET has the normal line of the projection side surface of the n-type MISFET as a four-fold symmetry axis. Therefore, when the rotation angle of the side surface of the protrusion of the p-type MISFET becomes 45 °, the p-type The mobility of the MISFET is the same as that at 1 45 °, and when the rotation angle is further increased from 45 °, the mobility shows the same behavior as when the force angle is increased by 1 45 °. Therefore, the rotation angle of the side surface of the protrusion of the p-type MISFET can represent the mobility of all the rotation angles (180-180 °) in the range of ⁇ 45 ° or more and 45 ° or less.
- the rotation center is the normal to the side surface of the protrusion of the n-type MISFET
- the crystal orientation of the plane parallel to the side surface of the protrusion of the p-type MISFET and the substrate of the MISFET is caused by the rotation.
- the “plane orientation” changes, but the crystal orientation on the side surface of the protrusion of the n-type MISFET does not change.
- the side surface of the protrusion is fixed to the reference state.
- Figure 4 shows the view from ⁇ 00_1>. The change in carrier movement characteristics when the side surface of the protrusion is rotated from this reference state will be described.
- Figure 8 (c) shows the relationship between the mobility and the crystal orientation of the p-type MISFET. Fig.
- FIG. 8 (b) rotates the projection side of the p-type MISFET about the normal line of the substrate as the center of rotation
- Fig. 8 (c) shows the projection side of the n-type MISFET.
- the projection side is rotated as the center of rotation, and the rotation center of the projection side is different between Fig. 8 (b) and Fig. 8 (c).
- the mobility of the n-type MISFET is represented by point (B) in FIG. 8A
- the mobility of the p-type MISFET is represented by point (H) in FIG. 8 (c).
- the measured CMIS delay index is 8.5 from Fig. 9.
- the planes corresponding to point (E) in Fig. 8 (b) and point (H) in Fig. 8 (c) are equivalent.
- the crystal orientation on the side surface of the n-type MISFET does not change, so the mobility does not move from the point (B) in FIG. 8A.
- the carrier mobility of the p-type MISFET reaches (G) in FIG. 8 (c).
- a point (G) represents the mobility of the p-type MISFET in the reference state when the projection side surface is rotated by 45 degrees.
- the carrier mobility of the p-type MISFET reaches the point (I) starting from the point (H) in FIG. 8 (c).
- Point (I) is the crystal symmetry representing the mobility of the p-type MISFET when the projection side is rotated by 45 °. From the nature, the mobility of the point (G) is the same as the mobility of the point (I).
- Point (I) represents the mobility of the p-type MISFET when the side surface of the protrusion is rotated by 45 °.
- FIG. 6 shows a semiconductor device in which the protrusion side surfaces are rotated by 45 ° when the arrangement in FIG. 4 is set as a reference state.
- FIG. 6 is a view of this arrangement.
- the crystal orientation of the side surface of the n-type MISFET2001 is (010) plane
- the crystal orientation of the side surface of the p-type MISFET2002 is (10-1) plane
- the crystal orientation of the plane parallel to the MISFET substrate is ( 1 01) face.
- the mobility of the n-type MISFET is represented by point (B) in Fig.
- the mobility of the p-type MISFET is represented by point (I) in Fig. 8 (c).
- the measured CMIS delay index is 6.1 from Fig. 9, which is lower than the conventional CMIS delay index corresponding to the arrangement in Fig. 2. Therefore, the carrier transfer characteristics of the CMIS are improved as compared with the conventional CMIS. The same result can be obtained even when the rotation angle is -45 °.
- the crystal orientation of the protruding semiconductor region of the n-type MISFET is such that the side surface is substantially a ⁇ 100 ⁇ plane, and the side surfaces of the protruding semiconductor region of the n-type MISFET are orthogonal. Is good.
- the crystal orientation of the plane parallel to the substrate of the MISFET and the side face of the protrusion of the p-type MISFET can be both ⁇ 100 ⁇ planes or both ⁇ 110 ⁇ planes.
- the mobility of the n-type MISFET becomes the maximum value from FIG. 8A, so that the delay index of the CMIS becomes a low value, and a CMIS having excellent carrier transfer characteristics can be obtained.
- the crystal orientation of the protruding semiconductor region of the n-type MISFET is such that a plane parallel to the substrate is substantially a ⁇ 110 ⁇ plane, and a side surface thereof is substantially perpendicular to the ⁇ 110 ⁇ plane.
- the crystal orientation of the protruding semiconductor region of the p-type MISFET is a ⁇ 110 ⁇ plane substantially parallel to the substrate and a ⁇ 110 ⁇ plane substantially parallel to the ⁇ 110 ⁇ plane. It's good, At this time, the mobility of the n-type MISFET and the p-type MISFET becomes the maximum value from FIGS. 8 (a) and 8 (c), so that the delay index of the CMIS becomes a low value, and the CMIS having excellent carrier mobility characteristics is obtained. Obtainable.
- the crystal orientation of the plane parallel to the substrate of the n-type MISFET and the p-type MISFET is ⁇ 100 ⁇ plane.
- n-type The crystal orientation of the projection side surface of the field-effect transistor and the p-type field-effect transistor is defined as a ⁇ 110 ⁇ plane, and a state where these three planes are orthogonal to each other is defined as a reference state.
- the surface parallel to the n-type MISFET and the p-type MISFET substrate and the n-type MISFET protrusion side surface were rotated at an angle of 90 ° or less around the normal of the side surface of the protrusion of the ⁇ -type MISFET as the rotation center. Equivalent to something.
- Rotate refers to the rotation of the n-type MISFET and the p-type MISFET, which is different from the rotation of the entity in the real space.
- Rotating the Fin means changing the crystal orientation of the Fin. That is, it means that the protruding semiconductor region is formed so as to have a side surface in such a current direction. Due to this rotation, the crystal orientation of the plane parallel to the substrate and the side surface of the n-type MISFET protrusion of the MISFET of this embodiment has a different crystal orientation from the reference state.
- CMIS can have high carrier movement characteristics.
- the n-type MISFET and the p-type MISFET are arranged so that the projection side surfaces are orthogonal to each other, it is possible to design an optimal arrangement that facilitates the layout of the MISFET.
- the plane parallel to the substrate of the MISFET in the reference state may be any of the (100) plane, the (010) plane, and the (001) plane. Regardless of which of these planes is parallel to the substrate, the n-type MISFET and the p-type MISFET have a ⁇ 110 ⁇ plane crystal orientation on the projection side surface, and these planes are orthogonal. When the rotation angles of these MISFETs are the same, the mobility becomes the same due to the symmetry of the silicon crystal.
- the crystal orientation of the plane parallel to the MISFET substrate is the (100) plane
- the crystal orientation of the n-type MISFET projection side is the (0-11) plane
- the crystal orientation of the p-type MISFET projection side is In the reference state of the (01 1) plane, 011> is the center of rotation.
- the crystal orientation of the plane parallel to the MISFET substrate is the (010) plane
- the crystal orientation of the n-type MISFET projection side is the (10_1) plane
- the crystal orientation of the p-type MISFET projection side is the (101) plane.
- 101> becomes the center of rotation.
- the crystal orientation of the plane parallel to the substrate of the MISFET is the (001) plane
- the crystal orientation of the projection side of the n-type MISFET is the (110) plane
- the crystal orientation of the projection side of the p-type MISFET is (110)
- 110> is the center of rotation.
- FIG. 8D corresponds to a case where the rotation angle of the n-type MISFET is 0 to 45 ° when rotated about the substrate normal of FIG. 8A as the center of rotation.
- the mobility of the n-type MISFET is represented by point (A) in Fig. 8 (d)
- the mobility of the p-type MISFET is represented by point (D) in Fig. 8 (b).
- the measured CMIS delay index is 8.8 from Fig. 9.
- FIG. 7 shows a semiconductor device in which the protrusion side surfaces of the n-type MISFET and the p-type MISFET are rotated by 90 ° when the arrangement in FIG. 2 is used as a reference state.
- Fig. 7 is a view of this arrangement.
- the crystal orientation of the side surface of the n-type MISFET2001 is (001) plane
- the crystal orientation of the side surface of the p-type MISFET2002 is (110) plane
- the plane parallel to the MISFET substrate is the (-110) plane.
- the mobility of the n-type MISFET is represented by a point (B) in FIG. 8D
- the mobility of the p-type MISFET is represented by a point (G) in FIG. 8B.
- the measured CMIS delay index is 6.1 (corresponding to the result in Fig. 6) from Fig. 9, which is lower than the conventional CMIS delay index corresponding to the arrangement in Fig. 2. Therefore, the carrier transfer characteristics of the CMIS are improved as compared with the conventional CMIS.
- the crystal orientation of the protruding semiconductor region of the p-type MISFET is substantially
- the ⁇ 110 ⁇ plane, the side surface of the protruding semiconductor region of the n-type MISFET is substantially orthogonal to the ⁇ 110 ⁇ plane, and the crystal orientation of the side surface is substantially different from the ⁇ 110 ⁇ plane.
- the crystal orientation of the plane parallel to the substrate of the MISFET can be the ⁇ 110 ⁇ plane
- the crystal orientation of the side surface of the protrusion of the p-type MISFET can be the ⁇ 100 ⁇ plane.
- the mobility of the p-type MISFET becomes the maximum value from FIG. 8 (c), so that the delay index of the CMIS becomes a low value, and a CMIS having excellent carrier mobility characteristics can be obtained.
- the same effect as when the projection side surfaces of these MISFETs are rotated by the same 45 degrees while maintaining the parallel arrangement of the projection side surfaces of the n-type MISFET and the p-type MISFET. Can be obtained as follows.
- the n-type MISFET and the p-type MISFET have a ⁇ 100 ⁇ plane parallel to the substrate (however, also include a plane with an off angle of 10 ° or less), and the n-type MISFET and the p-type MISFET
- the crystal orientations of the side surfaces of the protrusions are the same (the side surfaces of the protrusions are parallel to each other), and the crystal orientation of the side surfaces of the protrusions of the parentheses MISFET is the ⁇ 100 ⁇ plane perpendicular to the substrate.
- the plane parallel to the substrate of the n-type MISFET and the p-type MISFET is set to 0 ° or more with respect to the normal state of the projection side surface of the n-type and the p-type MISFET from the reference state. Equivalent to an object fixed or rotated at an angle of 90 ° or less.
- rotating a plane parallel to the substrate means that the rotation of the body in the real space is different from that of the body.
- rotating Fin it means changing the crystal orientation of Fin.
- both the n-type MISFET and the p-type MISFET as channel surfaces are fixed to the ⁇ 100 ⁇ plane, and the direction of current flow changes only within the ⁇ 100 ⁇ plane. ⁇ 100 ⁇
- the in-plane mobility has no dependence on the current direction due to the four-fold symmetry of the crystal. Therefore, this embodiment is different from the first embodiment in that the projection side surfaces of the n-type MISFET and the p-type MISFET are rotated by the same 45 ° while maintaining the parallel arrangement of the projection side surfaces. The same effect as in the case can be obtained.
- the semiconductor device according to the present invention can be manufactured using a conventional semiconductor device manufacturing method. However, they differ from the conventional manufacturing method in that substrates having different crystal orientations are used, and a resist mask is formed in an arrangement rotated by a predetermined angle during photolithography.
- FIG. 10 shows a manufacturing process of a semiconductor device including a fin-type MISFET in which a part of the protrusion is a part of a single-crystal silicon layer of an SOI substrate as shown in FIG. 12 (b).
- An SOI substrate consisting of a thin film 3003 is manufactured.
- the single crystal silicon film 3003 has a ⁇ 100 ⁇ plane in the first embodiment, and a predetermined crystal orientation in the second and third embodiments.
- an SiO film 3004 is formed on the surface of the SOI substrate by thermal oxidation (Fig. 1
- a MISFET in which impurities are not intentionally introduced into the channel may be used.
- the formation and removal of the thermal oxide film before and after that may be omitted.
- a photoresist is applied to the entire surface of the single crystal silicon film 3003, and a resist mask 3005 is formed by using photolithography (FIG. 10D).
- the resist mask 3005 is anisotropically dry-etched, the resist mask 3005 is removed, and a projection 3006 having a predetermined height is formed on the SiO film 3002.
- the SiO film is appropriately oriented downward by anisotropic etching, or
- a ⁇ -gate FinFET and an ⁇ -gate FinFET can be formed, respectively.
- a thin Si ⁇ film 3007 is formed on the surface of the single crystal silicon protrusion 3006 by a thermal oxidation method.
- a polysilicon film is formed on the Si film 3007 by a CVD method,
- a predetermined pattern is selectively etched to form a gate electrode 3008.
- an impurity is doped into the single crystal silicon projection 3006 to form a source region and a drain region (FIG. 10 (f)).
- FIG. 11 shows a manufacturing process of a semiconductor device including a fin-type MISFET in which a part of a projection is a part of a silicon wafer substrate as shown in FIG. 12A.
- a silicon oxide film 3004 is formed on the surface of the single crystal silicon film 3003 by a thermal oxidation method (FIG. 11 (a)).
- the crystal orientation of the con film 3003 the ⁇ 100 ⁇ plane is used in the first embodiment, and the crystal orientation of a predetermined crystal orientation is used in the second and third embodiments.
- ions are implanted into the single crystal silicon film 3003 to form a semiconductor region (FIG. 11B). Then low on SiO oxide film 3004
- a silicon nitride film 3009 is formed by a pressure CVD method (FIG. 11C).
- a MISFET that does not intentionally introduce impurities into the channel can be used. Further, the formation and removal of the thermal oxide film before and after that may be omitted.
- a photoresist is applied to the entire surface of the silicon nitride film 3009, and a resist mask 3005 is formed using photolithography while leaving the photoresist only at a portion where a MOSFET is to be formed (Fig. 11 (d)). ).
- the resist mask 3005 is anisotropically dry-etched, the resist mask 3005 is removed, and a projection 3006 having a predetermined height is formed on the substrate (FIG. e)).
- the projections 3006, the SiO oxide film 3004, and the silicon nitride film 3009 are formed by low-pressure CVD.
- the Si ⁇ oxide film 3010 is formed to a thickness that covers all the protrusions made of (FIG. 11 (f)). Continued
- the SiO oxide film 3010 is etched to a predetermined thickness, and the isolation insulating film 3011 is formed.
- a thin Si oxide film 3007 is formed on the surfaces of the protrusions by a thermal oxidation method. Furthermore, on this Si ⁇ oxide film 3007
- a polysilicon film is formed by a CVD method, and after being made conductive by impurity diffusion, selective etching is performed on a predetermined pattern to form a gate electrode 3008.
- an impurity is doped into the projection 3006 made of single-crystal silicon to form a source.
- a region and a drain region are formed (FIG. 11F).
- an insulating film thicker than the gate insulating film can be formed between the upper portion of the fin and the gate electrode 3008. Even when the fin is on the SOI, an insulating film thicker than the gate insulating film can be formed between the upper portion of the fin and the gate electrode by the same method.
- FIG. 17 shows a method of manufacturing a semiconductor device (balta substrate type) in which Fin type MISFETs and planar type MISFETs are mixed. Steps in the middle (FIGS. 17 (a) and (b)) are the same as the steps in FIGS. 11 (a) and (f). Thereafter, in the manufacturing method of FIG. 11, the insulating film 3010 provided in a portion other than the fin is retracted, but in the manufacturing method of FIG. 17, the insulating film 3010 is retracted in a portion configuring the fin-type transistor. The difference is that it does not recede in the parts that make up the planar transistor (Fig. 17 (c)).
- FIG. 17 is a diagram of the hybrid transistor viewed from above.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005513479A JPWO2005022637A1 (ja) | 2003-08-28 | 2004-08-27 | フィン型電界効果トランジスタを有する半導体装置 |
US10/569,451 US20070187682A1 (en) | 2003-08-28 | 2004-08-27 | Semiconductor device having fin-type effect transistor |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003-304753 | 2003-08-28 | ||
JP2003304753 | 2003-08-28 | ||
JP2004-235346 | 2004-08-12 | ||
JP2004235346 | 2004-08-12 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2005022637A1 true WO2005022637A1 (ja) | 2005-03-10 |
Family
ID=34277642
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2004/012385 WO2005022637A1 (ja) | 2003-08-28 | 2004-08-27 | フィン型電界効果トランジスタを有する半導体装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20070187682A1 (ja) |
JP (1) | JPWO2005022637A1 (ja) |
WO (1) | WO2005022637A1 (ja) |
Cited By (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006339514A (ja) * | 2005-06-03 | 2006-12-14 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2007035957A (ja) * | 2005-07-27 | 2007-02-08 | Toshiba Corp | 半導体装置とその製造方法 |
JP2007073960A (ja) * | 2005-09-06 | 2007-03-22 | Taiwan Semiconductor Manufacturing Co Ltd | 半導体デバイスおよびcmosデバイス |
JP2008517464A (ja) * | 2004-10-18 | 2008-05-22 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Finfetと一体化した平坦基板デバイス及びその製造方法 |
EP1959492A1 (en) * | 2005-12-02 | 2008-08-20 | Tohoku University | Semiconductor device |
JP2009509344A (ja) * | 2005-09-19 | 2009-03-05 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 高密度のシェブロンfinFET及びそれを製造する方法 |
JP2009117818A (ja) * | 2007-10-15 | 2009-05-28 | Qimonda Ag | 集積回路の製造方法 |
JP2010067635A (ja) * | 2008-09-08 | 2010-03-25 | Imec | 電子回路および電子回路の製造方法 |
US7701018B2 (en) | 2004-03-19 | 2010-04-20 | Nec Corporation | Semiconductor device and method for manufacturing same |
US7777306B2 (en) * | 2007-03-06 | 2010-08-17 | International Business Machines Corporation | Defect-free hybrid orientation technology for semiconductor devices |
JP2010245522A (ja) * | 2009-04-03 | 2010-10-28 | Internatl Business Mach Corp <Ibm> | 半導体構造体およびその製造方法(移動度が最適化された方位を有する半導体ナノワイヤ) |
US7859065B2 (en) | 2005-06-07 | 2010-12-28 | Nec Corporation | Fin-type field effect transistor and semiconductor device |
US7989855B2 (en) | 2004-06-10 | 2011-08-02 | Nec Corporation | Semiconductor device including a deflected part |
DE102009047639B4 (de) * | 2009-01-28 | 2014-08-14 | Infineon Technologies Ag | Halbleiterelement, Fin-Feldeffekttransistor und integrierte Schaltung |
JP2014179604A (ja) * | 2013-03-11 | 2014-09-25 | Renesas Electronics Corp | フィンfet構造を有する半導体装置及びその製造方法 |
CN109216428A (zh) * | 2017-06-29 | 2019-01-15 | 台湾积体电路制造股份有限公司 | 半导体结构及其制造方法 |
JP2021153191A (ja) * | 2013-05-20 | 2021-09-30 | 株式会社半導体エネルギー研究所 | 半導体装置 |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7456476B2 (en) | 2003-06-27 | 2008-11-25 | Intel Corporation | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication |
US7042009B2 (en) | 2004-06-30 | 2006-05-09 | Intel Corporation | High mobility tri-gate devices and methods of fabrication |
US20060086977A1 (en) | 2004-10-25 | 2006-04-27 | Uday Shah | Nonplanar device with thinned lower body portion and method of fabrication |
US7518196B2 (en) | 2005-02-23 | 2009-04-14 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US7858481B2 (en) | 2005-06-15 | 2010-12-28 | Intel Corporation | Method for fabricating transistor with thinned channel |
US7547637B2 (en) | 2005-06-21 | 2009-06-16 | Intel Corporation | Methods for patterning a semiconductor film |
US7279375B2 (en) * | 2005-06-30 | 2007-10-09 | Intel Corporation | Block contact architectures for nanoscale channel transistors |
US7230287B2 (en) * | 2005-08-10 | 2007-06-12 | International Business Machines Corporation | Chevron CMOS trigate structure |
US20070090416A1 (en) | 2005-09-28 | 2007-04-26 | Doyle Brian S | CMOS devices with a single work function gate electrode and method of fabrication |
US7485503B2 (en) | 2005-11-30 | 2009-02-03 | Intel Corporation | Dielectric interface for group III-V semiconductor device |
JP2007299951A (ja) * | 2006-04-28 | 2007-11-15 | Toshiba Corp | 半導体装置およびその製造方法 |
US8143646B2 (en) | 2006-08-02 | 2012-03-27 | Intel Corporation | Stacking fault and twin blocking barrier for integrating III-V on Si |
US8362566B2 (en) | 2008-06-23 | 2013-01-29 | Intel Corporation | Stress in trigate devices using complimentary gate fill materials |
US8268729B2 (en) | 2008-08-21 | 2012-09-18 | International Business Machines Corporation | Smooth and vertical semiconductor fin structure |
US8420455B2 (en) | 2010-05-12 | 2013-04-16 | International Business Machines Corporation | Generation of multiple diameter nanowire field effect transistors |
US8519479B2 (en) * | 2010-05-12 | 2013-08-27 | International Business Machines Corporation | Generation of multiple diameter nanowire field effect transistors |
JP2012182354A (ja) * | 2011-03-02 | 2012-09-20 | Toshiba Corp | 半導体記憶装置 |
US8969154B2 (en) * | 2011-08-23 | 2015-03-03 | Micron Technology, Inc. | Methods for fabricating semiconductor device structures and arrays of vertical transistor devices |
US8629512B2 (en) | 2012-03-28 | 2014-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gate stack of fin field effect transistor with slanted sidewalls |
CN103367153B (zh) * | 2012-03-31 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | 鳍式场效应管及其形成方法 |
CN103579234A (zh) * | 2012-08-03 | 2014-02-12 | 中国科学院微电子研究所 | 一种半导体结构及其制造方法 |
US9136320B2 (en) * | 2013-04-08 | 2015-09-15 | Design Express Limited | Field effect transistor |
US9508799B2 (en) * | 2014-08-26 | 2016-11-29 | United Microelectronics Corp. | Substrate of semiconductor device including epitaxial layer and silicon layer having same crystalline orientation |
WO2016143653A1 (ja) * | 2015-03-06 | 2016-09-15 | 株式会社トクヤマ | Iii族窒化物積層体、及び該積層体を有する発光素子 |
DE102015106689A1 (de) | 2015-04-29 | 2016-11-03 | Infineon Technologies Ag | Verfahren zum Herstellen einer Halbleitervorrichtung mit geneigten Ionenimplantationsprozessen, Halbleitervorrichtung und integrierte Schaltung |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6380561A (ja) * | 1986-09-24 | 1988-04-11 | Nec Corp | 相補型半導体装置の製造方法 |
JP2003188273A (ja) * | 2001-12-13 | 2003-07-04 | Tadahiro Omi | 相補型mis装置 |
JP2003229575A (ja) * | 2002-02-04 | 2003-08-15 | Hitachi Ltd | 集積半導体装置及びその製造方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6413802B1 (en) * | 2000-10-23 | 2002-07-02 | The Regents Of The University Of California | Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture |
US7163851B2 (en) * | 2002-08-26 | 2007-01-16 | International Business Machines Corporation | Concurrent Fin-FET and thick-body device fabrication |
US6821834B2 (en) * | 2002-12-04 | 2004-11-23 | Yoshiyuki Ando | Ion implantation methods and transistor cell layout for fin type transistors |
US6885055B2 (en) * | 2003-02-04 | 2005-04-26 | Lee Jong-Ho | Double-gate FinFET device and fabricating method thereof |
-
2004
- 2004-08-27 US US10/569,451 patent/US20070187682A1/en not_active Abandoned
- 2004-08-27 WO PCT/JP2004/012385 patent/WO2005022637A1/ja active Application Filing
- 2004-08-27 JP JP2005513479A patent/JPWO2005022637A1/ja active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6380561A (ja) * | 1986-09-24 | 1988-04-11 | Nec Corp | 相補型半導体装置の製造方法 |
JP2003188273A (ja) * | 2001-12-13 | 2003-07-04 | Tadahiro Omi | 相補型mis装置 |
JP2003229575A (ja) * | 2002-02-04 | 2003-08-15 | Hitachi Ltd | 集積半導体装置及びその製造方法 |
Cited By (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7701018B2 (en) | 2004-03-19 | 2010-04-20 | Nec Corporation | Semiconductor device and method for manufacturing same |
US8486811B2 (en) | 2004-06-10 | 2013-07-16 | Nec Corporation | Semiconductor device and manufacturing process therefor |
US7989855B2 (en) | 2004-06-10 | 2011-08-02 | Nec Corporation | Semiconductor device including a deflected part |
JP2008517464A (ja) * | 2004-10-18 | 2008-05-22 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Finfetと一体化した平坦基板デバイス及びその製造方法 |
JP4711446B2 (ja) * | 2004-10-18 | 2011-06-29 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Finfetと一体化した平坦基板デバイス及びその製造方法 |
JP4648096B2 (ja) * | 2005-06-03 | 2011-03-09 | 株式会社東芝 | 半導体装置の製造方法 |
JP2006339514A (ja) * | 2005-06-03 | 2006-12-14 | Toshiba Corp | 半導体装置及びその製造方法 |
US7859065B2 (en) | 2005-06-07 | 2010-12-28 | Nec Corporation | Fin-type field effect transistor and semiconductor device |
US8247294B2 (en) | 2005-06-07 | 2012-08-21 | Nec Corporation | Manufacturing process of fin-type field effect transistor and semiconductor |
JP2007035957A (ja) * | 2005-07-27 | 2007-02-08 | Toshiba Corp | 半導体装置とその製造方法 |
JP4639172B2 (ja) * | 2005-09-06 | 2011-02-23 | 台湾積體電路製造股▲ふん▼有限公司 | 半導体デバイス |
JP2007073960A (ja) * | 2005-09-06 | 2007-03-22 | Taiwan Semiconductor Manufacturing Co Ltd | 半導体デバイスおよびcmosデバイス |
JP2009509344A (ja) * | 2005-09-19 | 2009-03-05 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 高密度のシェブロンfinFET及びそれを製造する方法 |
EP1959492A4 (en) * | 2005-12-02 | 2011-06-01 | Univ Tohoku | SEMICONDUCTOR COMPONENT |
EP1959492A1 (en) * | 2005-12-02 | 2008-08-20 | Tohoku University | Semiconductor device |
US7777306B2 (en) * | 2007-03-06 | 2010-08-17 | International Business Machines Corporation | Defect-free hybrid orientation technology for semiconductor devices |
JP2009117818A (ja) * | 2007-10-15 | 2009-05-28 | Qimonda Ag | 集積回路の製造方法 |
JP2010067635A (ja) * | 2008-09-08 | 2010-03-25 | Imec | 電子回路および電子回路の製造方法 |
DE102009047639B4 (de) * | 2009-01-28 | 2014-08-14 | Infineon Technologies Ag | Halbleiterelement, Fin-Feldeffekttransistor und integrierte Schaltung |
JP2010245522A (ja) * | 2009-04-03 | 2010-10-28 | Internatl Business Mach Corp <Ibm> | 半導体構造体およびその製造方法(移動度が最適化された方位を有する半導体ナノワイヤ) |
JP2014179604A (ja) * | 2013-03-11 | 2014-09-25 | Renesas Electronics Corp | フィンfet構造を有する半導体装置及びその製造方法 |
JP2021153191A (ja) * | 2013-05-20 | 2021-09-30 | 株式会社半導体エネルギー研究所 | 半導体装置 |
JP7157851B2 (ja) | 2013-05-20 | 2022-10-20 | 株式会社半導体エネルギー研究所 | 半導体装置 |
JP7426459B2 (ja) | 2013-05-20 | 2024-02-01 | 株式会社半導体エネルギー研究所 | 半導体装置 |
US11961917B2 (en) | 2013-05-20 | 2024-04-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device comprising stacked transistors |
CN109216428A (zh) * | 2017-06-29 | 2019-01-15 | 台湾积体电路制造股份有限公司 | 半导体结构及其制造方法 |
US11735594B2 (en) | 2017-06-29 | 2023-08-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit structure and method with hybrid orientation for FinFET |
Also Published As
Publication number | Publication date |
---|---|
US20070187682A1 (en) | 2007-08-16 |
JPWO2005022637A1 (ja) | 2007-11-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2005022637A1 (ja) | フィン型電界効果トランジスタを有する半導体装置 | |
US11139400B2 (en) | Non-planar semiconductor device having hybrid geometry-based active region | |
US9905650B2 (en) | Uniaxially strained nanowire structure | |
US7759737B2 (en) | Dual structure FinFET and method of manufacturing the same | |
JP4904815B2 (ja) | 半導体装置及びその製造方法 | |
CN108172548B (zh) | 用于形成金属氧化物半导体器件结构的鳍的方法 | |
US20160111426A1 (en) | Methods of integrating multiple gate dielectric transistors on a tri-gate (finfet) process | |
JP4216676B2 (ja) | 半導体装置 | |
EP3285300A1 (en) | Precision resistor for non-planar semiconductor device architecture | |
JP5270094B2 (ja) | 細型化されたボディを有する、狭いボディのダマシン・トライゲートFinFET | |
US20200027960A1 (en) | Semiconductor device and method of manufacturing the same | |
US9881927B2 (en) | CMOS-compatible polycide fuse structure and method of fabricating same | |
WO2005038931A1 (ja) | 半導体装置及び半導体装置の製造方法 | |
CN110634939A (zh) | 纳米线晶体管和衬底之间的电介质隔离层 | |
WO2005119764A1 (ja) | 半導体装置およびその製造方法 | |
WO2011066728A1 (zh) | 混合材料积累型全包围栅cmos场效应晶体管 | |
TW202125823A (zh) | 具有絕緣基體之閘極全包圍式積體電路結構 | |
US20230197821A1 (en) | Gate-all-around devices with optimized gate spacers and gate end dielectric | |
TW202129979A (zh) | 具有移除基板的環繞式閘極積體電路結構 | |
WO2005020325A1 (ja) | 半導体装置及びその製造方法 | |
US11581414B2 (en) | Gate-all-around devices with optimized gate spacers and gate end dielectric | |
US7105391B2 (en) | Planar pedestal multi gate device | |
US20240113214A1 (en) | Semiconductor structure with dielectric spacer and method for manufacturing the same | |
US20230387120A1 (en) | Semiconductor device structure and methods of forming the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 2005513479 Country of ref document: JP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 10569451 Country of ref document: US Ref document number: 2007187682 Country of ref document: US |
|
122 | Ep: pct application non-entry in european phase | ||
WWP | Wipo information: published in national office |
Ref document number: 10569451 Country of ref document: US |