JP4904815B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP4904815B2 JP4904815B2 JP2005514553A JP2005514553A JP4904815B2 JP 4904815 B2 JP4904815 B2 JP 4904815B2 JP 2005514553 A JP2005514553 A JP 2005514553A JP 2005514553 A JP2005514553 A JP 2005514553A JP 4904815 B2 JP4904815 B2 JP 4904815B2
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- 229910052697 platinum Inorganic materials 0.000 description 1
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Description
このトランジスタを含む基体上に設けられた層間絶縁膜、及び
この層間絶縁膜に形成された溝に導電体が埋め込まれてなる埋め込み導体配線を有し、
この埋め込み導体配線は、前記半導体凸部のソース/ドレイン領域と、前記層間絶縁膜下の他の導電部とを結合することを特徴とする半導体装置に関する。
前記埋め込み導体配線は、第1のトランジスタのソース/ドレイン領域と、前記の他の導電部として第2のトランジスタのゲート電極又はソース/ドレイン領域とに接続されている上記の半導体装置に関する。
前記埋め込み導体配線は、当該トランジスタにおいて、一の半導体凸部のソース/ドレイン領域と、前記の他の導電部として他の半導体凸部のソース/ドレイン領域とに接続されている上記の半導体装置に関する。
第1導電型トランジスタ及び第2導電型トランジスタのゲート電極が共通の導体配線で構成され、この導体配線は入力部へ導通され、
前記埋め込み導体配線が、第1導電型トランジスタのドレイン領域と第2導電型トランジスタのドレイン領域とに接続され、出力部へ導通されている上記の半導体装置に関する。
前記の各トランジスタは、基体平面に対して突出した半導体凸部と、この半導体凸部を跨ぐようにその上部から相対する両側面上に延在するゲート電極と、このゲート電極と前記半導体凸部の間に介在するゲート絶縁膜と、前記半導体凸部に設けられたソース/ドレイン領域とを有し、
前記の各トランジスタを構成する半導体凸部は、その長手方向が第1方向に沿って配置され、
第1駆動トランジスタ及び第1転送トランジスタは共通の第1半導体凸部を有し、第2駆動トランジスタ及び第2転送トランジスタは共通の第2半導体凸部を有し、第1負荷トランジスタは第1半導体凸部と隣り合う第3半導体凸部を有し、第2負荷トランジスタは第2半導体凸部に隣り合う第4半導体凸部を有し、
第1駆動トランジスタ及び第1負荷トランジスタのゲート電極は共通の第1導体配線で構成され、第2駆動トランジスタ及び第2負荷トランジスタのゲート電極は共通の第2導体配線で構成され、これらの導体配線はその長手方向が第1方向に垂直な第2方向に沿って配置されていることを特徴とする半導体装置に関する。
第1導体配線と、第2負荷トランジスタのドレイン領域と、第2駆動トランジスタのドレイン領域と、第2転送トランジスタのソース/ドレイン領域とに接続され、前記層間絶縁膜に形成された第1埋め込み導体配線、及び
第2導体配線と、第1負荷トランジスタのドレイン領域と、第1駆動トランジスタのドレイン領域と、第1転送トランジスタのソース/ドレイン領域とに接続され、前記層間絶縁膜に形成された第2埋め込み導体配線を有する上記の半導体装置に関する。
前記MIS型電界効果トランジスタを形成する工程と、前記半導体凸部を埋め込むように層間絶縁膜を形成する工程と、この層間絶縁膜に溝を形成して当該溝内に前記半導体凸部のソース/ドレイン領域および当該ソース/ドレイン領域と導通しようとする他の導電部のそれぞれ少なくとも一部を露出させる工程と、前記溝に導電体を埋め込んで前記ソース/ドレイン領域と前記の他の導電部とに接続される埋め込み導体配線を形成する工程とを有する半導体装置の製造方法に関する。
前記溝の形成工程において、互いに導通しようとする半導体凸部のソース/ドレイン領域のそれぞれ少なくとも一部を露出させ、当該溝に導電体を埋め込んで、当該トランジスタにおける一の半導体凸部のソース/ドレイン領域と他の半導体凸部のソース/ドレイン領域とに接続される埋め込み導体配線を形成する上記の半導体装置の製造方法に関する。
半導体凸部の高さH:20〜200nm、
ゲート長L:10〜100nm、
ゲート絶縁膜の厚さ:1〜5nm(SiO2の場合)、
チャネル形成領域の不純物濃度:0〜1×1019cm−3、
ソース/ドレイン領域の不純物濃度:1×1019〜1×1021cm−3。
Random Access Memory)の例である。ここで、一対の駆動トランジスタTd1、Td2と一対の転送トランジスタTt1、Tt2はnチャネル型であり、一対の負荷トランジスタTp1、Tp2はpチャネル型である。
Claims (17)
- 基体平面に対して突出した半導体凸部と、この半導体凸部を跨ぐようにその上部から相対する両側面上に延在するゲート電極と、このゲート電極と前記半導体凸部の間に介在するゲート絶縁膜と、前記半導体凸部に設けられたソース/ドレイン領域とを有するMIS型電界効果トランジスタ、
このトランジスタを含む基体上に設けられた層間絶縁膜、及び
この層間絶縁膜に形成された溝に導電体が埋め込まれてなる埋め込み導体配線を有し、
前記埋め込み導体配線は、前記半導体凸部のソース/ドレイン領域と、前記層間絶縁膜下の他の導電部とに接続され、且つ前記層間絶縁膜の上面と同一平面にある上面、及び前記ソース/ドレイン領域との接続部における半導体凸部上面より下方にある下面を有し、
この埋め込み導体配線は、前記半導体凸部のソース/ドレイン領域と、前記層間絶縁膜下の他の導電部とを結合し、
前記MIS型電界効果トランジスタとして、第1のトランジスタ及び第2のトランジスタを有し、
前記埋め込み導体配線は、第1のトランジスタのソース/ドレイン領域と、前記の他の導電部として第2のトランジスタのゲート電極とに接続されていることを特徴とする半導体装置。 - 基体平面に対して突出した半導体凸部と、この半導体凸部を跨ぐようにその上部から相対する両側面上に延在するゲート電極と、このゲート電極と前記半導体凸部の間に介在するゲート絶縁膜と、前記半導体凸部に設けられたソース/ドレイン領域とを有するMIS型電界効果トランジスタ、
このトランジスタを含む基体上に設けられた層間絶縁膜、及び
この層間絶縁膜に形成された溝に導電体が埋め込まれてなる埋め込み導体配線を有し、
前記埋め込み導体配線は、前記半導体凸部のソース/ドレイン領域と、前記層間絶縁膜下の他の導電部とに接続され、且つ前記層間絶縁膜の上面と同一平面にある上面、及び前記ソース/ドレイン領域との接続部における半導体凸部上面より下方にある下面を有し、
この埋め込み導体配線は、前記半導体凸部のソース/ドレイン領域と、前記層間絶縁膜下の他の導電部とを結合し、
前記MIS型電界効果トランジスタとして、CMOSインバータを構成する第1導電型トランジスタ及び第2導電型トランジスタを有し、
第1導電型トランジスタ及び第2導電型トランジスタのゲート電極が共通の導体配線で構成され、この導体配線は入力部へ導通され、
前記埋め込み導体配線が、第1導電型トランジスタのドレイン領域と第2導電型トランジスタのドレイン領域とに接続され、出力部へ導通されていることを特徴とする半導体装置。 - 前記埋め込み導体配線は、前記ソース/ドレイン領域との接続部において、当該半導体凸部の相対する両側面に接触している請求項1又は2に記載の半導体装置。
- 前記MIS型電界効果トランジスタとして、基体平面に対して突出した複数の半導体凸部と、これら複数の半導体凸部に跨って設けられ各半導体凸部の上部から相対する両側面上に延在する導体配線で構成されるゲート電極と、このゲート電極と各半導体凸部の間に介在するゲート絶縁膜と、各半導体凸部に設けられたソース/ドレイン領域とを有するトランジスタを有し、
前記埋め込み導体配線は、当該トランジスタにおいて、一の半導体凸部のソース/ドレイン領域と、前記の他の導電部として他の半導体凸部のソース/ドレイン領域とに接続されている請求項1〜3のいずれか一項に記載の半導体装置。 - 前記複数の半導体凸部が互いに平行配列している請求項4記載の半導体装置。
- 前記埋め込み導体配線が、プラグを介してまたは直接に上層配線と接続されている請求項1〜5のいずれか一項に記載の半導体装置。
- 前記埋め込み導体配線と前記ソース/ドレイン領域との接続部は、金属又は金属化合物からなる低抵抗化層を介して接続されている請求項1〜6のいずれか一項に記載の半導体装置。
- 前記半導体凸部は、基板平面に平行かつチャネル長方向に垂直な方向の幅Wが、少なくとも当該半導体凸部のソース/ドレイン領域と前記埋め込み導体配線との接続部において、ゲート電極下の部分の幅Wより広い部分を有する請求項1〜7のいずれか一項に記載の半導体装置。
- 一対の第1及び第2駆動トランジスタ、一対の第1及び第2負荷トランジスタ及び一対の第1及び第2転送トランジスタを備えたSRAMセル単位を有する半導体装置であって、
前記の各トランジスタは、基体平面に対して突出した半導体凸部と、この半導体凸部を跨ぐようにその上部から相対する両側面上に延在するゲート電極と、このゲート電極と前記半導体凸部の間に介在するゲート絶縁膜と、前記半導体凸部に設けられたソース/ドレイン領域とを有し、
前記の各トランジスタを構成する半導体凸部は、その長手方向が第1方向に沿って配置され、
第1駆動トランジスタ及び第1転送トランジスタは共通の第1半導体凸部を有し、第2駆動トランジスタ及び第2転送トランジスタは共通の第2半導体凸部を有し、第1負荷トランジスタは第1半導体凸部と隣り合う第3半導体凸部を有し、第2負荷トランジスタは第2半導体凸部に隣り合う第4半導体凸部を有し、
第1駆動トランジスタ及び第1負荷トランジスタのゲート電極は共通の第1導体配線で構成され、第2駆動トランジスタ及び第2負荷トランジスタのゲート電極は共通の第2導体配線で構成され、これらの導体配線はその長手方向が第1方向に垂直な第2方向に沿って配置され、
前記のSRAMセル単位を含む基体上に設けられた層間絶縁膜、
第1導体配線と、第2負荷トランジスタのドレイン領域と、第2駆動トランジスタのドレイン領域と、第2転送トランジスタのソース/ドレイン領域とに接続され、前記層間絶縁膜に形成された第1埋め込み導体配線、及び
第2導体配線と、第1負荷トランジスタのドレイン領域と、第1駆動トランジスタのドレイン領域と、第1転送トランジスタのソース/ドレイン領域とに接続され、前記層間絶縁膜に形成された第2埋め込み導体配線を有し、
第1及び第2埋め込み導体配線はそれぞれ、前記層間絶縁膜の上面と同一平面にある上面、並びに前記ドレイン領域及びソース/ドレイン領域との接続部における半導体凸部上面より下方にある下面を有することを特徴とする半導体装置。 - 第1及び第2埋め込み導体配線は、前記ドレイン領域及びソース/ドレイン領域との接続部において、当該半導体凸部の相対する両側面に接触している請求項9に記載の半導体装置。
- 前記のトランジスタとして、基体平面に対して突出した複数の半導体凸部と、これら複数の半導体凸部に跨って設けられ各半導体凸部の上部から相対する両側面上に延在する導体配線で構成されるゲート電極と、このゲート電極と各半導体凸部の間に介在するゲート絶縁膜と、各半導体凸部に設けられたソース/ドレイン領域とを有するトランジスタを有する請求項9又は10に記載の半導体装置。
- 基体平面に対して突出した半導体凸部と、この半導体凸部を跨ぐようにその上部から相対する両側面上に延在するゲート電極と、このゲート電極と前記半導体凸部の間に介在するゲート絶縁膜と、前記半導体凸部に設けられたソース/ドレイン領域とを有するMIS型電界効果トランジスタを備えた半導体装置の製造方法であって、
前記MIS型電界効果トランジスタを形成する工程と、前記半導体凸部を埋め込むように層間絶縁膜を形成する工程と、この層間絶縁膜に溝を形成して当該溝内に前記半導体凸部のソース/ドレイン領域および当該ソース/ドレイン領域と導通しようとする他の導電部のそれぞれ少なくとも一部を露出させる工程と、前記溝に導電体を埋め込んで前記ソース/ドレイン領域と前記の他の導電部とに接続される埋め込み導体配線を形成する工程とを有し、
前記の他の導電部は、前記MIS型電界効果トランジスタとして形成した他のトランジスタのゲート電極であり、
前記埋め込み導体配線は、前記半導体凸部のソース/ドレイン領域と、前記の他の導電部とに接続され、且つ前記層間絶縁膜の上面と同一平面にある上面、及び前記ソース/ドレイン領域との接続部における半導体凸部上面より下方にある下面を有する、半導体装置の製造方法。 - 前記MIS型電界効果トランジスタは、基体平面に対して突出した複数の半導体凸部と、これら複数の半導体凸部に跨って設けられ各半導体凸部の上部から相対する両側面上に延在する導体配線で構成されるゲート電極と、このゲート電極と各半導体凸部の間に介在するゲート絶縁膜と、各半導体凸部に設けられたソース/ドレイン領域とを有し、
前記溝の形成工程において、互いに導通しようとする半導体凸部のソース/ドレイン領域のそれぞれ少なくとも一部を露出させ、当該溝に導電体を埋め込んで、当該トランジスタにおける一の半導体凸部のソース/ドレイン領域と他の半導体凸部のソース/ドレイン領域とに接続される埋め込み導体配線を形成する請求項12記載の半導体装置の製造方法。 - 前記層間絶縁膜を形成する前に、前記半導体凸部の表面にSiエピタキシャル成長を行う工程を有する請求項12又は13に記載の半導体装置の製造方法。
- 前記層間絶縁膜を形成する前に、前記半導体凸部に金属または金属化合物からなる低抵抗化層を形成する工程を有する請求項12〜14のいずれか一項に記載の半導体装置の製造方法。
- 前記溝を形成した後に、当該溝内で露出する半導体凸部の表面にSiエピタキシャル成長を行う工程を有する請求項12又は13に記載の半導体装置の製造方法。
- 前記溝を形成した後に、当該溝内で露出する前記半導体凸部に金属または金属化合物からなる低抵抗化層を形成する工程を有する請求項12〜14、16のいずれか一項に記載の半導体装置の製造方法。
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