JP5370161B2 - 半導体材料内へのトレンチの形成 - Google Patents
半導体材料内へのトレンチの形成 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 76
- 239000000463 material Substances 0.000 title claims description 13
- 230000015572 biosynthetic process Effects 0.000 title 1
- 238000000034 method Methods 0.000 claims description 33
- 238000005530 etching Methods 0.000 claims description 23
- 150000004767 nitrides Chemical class 0.000 claims description 19
- 125000006850 spacer group Chemical group 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 239000011810 insulating material Substances 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 230000003796 beauty Effects 0.000 claims 1
- 239000012774 insulation material Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 79
- 238000005468 ion implantation Methods 0.000 description 13
- 229910021332 silicide Inorganic materials 0.000 description 10
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 239000013626 chemical specie Substances 0.000 description 6
- 238000005520 cutting process Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 229910052736 halogen Inorganic materials 0.000 description 2
- 150000002367 halogens Chemical class 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910021334 nickel silicide Inorganic materials 0.000 description 2
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
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- 150000002500 ions Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Description
本発明の1つの実施形態によると、半導体層上に半導体素子を製造するための方法において、
半導体層の上にゲート誘電体層を形成する工程と、
前記ゲート誘電体層の上にゲート材料層を形成する工程と、
前記ゲート材料層をパターニングしてゲート構造を形成する工程と、
前記ゲート構造をマスクとして使用して、前記半導体層にイオン注入する工程と、
前記ゲート構造を貫通するようにエッチングして、第1のパターニング済みゲート構造を形成し、及び、前記半導体層を貫通するようにエッチングして、前記半導体層の第1部分及び第2部分、及び前記パターニング済みゲート構造を取り囲むトレンチを前記半導体層に形成する工程と、
前記トレンチに絶縁材料を充填する工程とを備える、方法を要旨とする。
上記の方法において、前記電気的に接続する工程は、
絶縁層を前記基板の上に堆積させる工程と、
トレンチを、前記ゲートの少なくとも一部分の上の前記絶縁層に形成する工程と、
前記絶縁層中の前記トレンチに導電材料を充填する工程とを備えていてもよい。
金属層を前記第1のパターニング済みゲート構造の上に堆積させる工程と、
前記金属層をパターニングして、該金属層の一部分を前記第1のパターニング済みゲート構造の上に残す工程とを備えるものであってもよい。
エッチングする前記工程では更に、前記第1のパターニング済みゲート構造が、前記半導体層中の前記トレンチと同じ垂直平面で終端する端部を有し、前記第1部分は前記第1のパターニング済みゲート構造の第1の側に位置するとともに、前記第2部分は第1のパターニング済みゲート構造の第2の側に位置するものでもよい。
トレンチサイドウォールスペーサを前記トレンチの側壁に形成する工程と、
絶縁材料を前記トレンチに、前記トレンチサイドウォールスペーサを形成する工程の後に堆積させる工程を備えることもある。
半導体層の上にゲート構造を形成する工程と、
前記ゲート構造をマスクとして使用してイオン注入を行う工程と、
イオン注入する前記工程の後に、前記半導体層にトレンチを形成することにより前記半導体層に活性領域を画定する工程において、前記ゲート構造及び前記半導体層を貫通するようにエッチングして、前記エッチングによってパターニング済みゲート構造が前記活性領域に形成される、前記活性領域を画定する工程と、
絶縁材料を前記トレンチに堆積させる工程とを備える。
高k誘電体をゲート誘電体として該半導体層の上に、該ゲート構造を形成する前に形成する工程を備えるものでもよい。
導電配線を前記パターニング済みゲート構造に電気的に接続する工程とをさらに備えることもある。
前記第1及び第2端部は前記活性領域の前記境界と同じ垂直平面で終端し、及び、前記第1導電構造はゲートとして機能するとともに、ソースドレインイオン注入を行なうためのイオン注入マスクとして機能することができるために十分厚いことと、該トレンチ内の絶縁材料とを備える。
また、第2導電構造をさらに備え、前記第2導電構造は、一部分前記第1導電構造の上に有し、前記第1導電構造と電気的にコンタクトし、前記第1導電構造の材料とは異なる材料からなり、及び前記活性領域の外に延びるものであってもよい。
前記第1導電構造は金属を含み、高k誘電体によって前記第1導電構造が前記半導体層から分離されるものであってもよい。
更に、本明細書において使用する「a」または「an」は、一つ(one)よりも多くの一つ以上(one or more)として定義される。また、請求項群における「at least one」及び「one or more」のような前置き語句の使用は、別の請求要素の前に不定冠詞「a」または「an」を配置することによって、このような不定冠詞の付いた請求要素を含む特定の請求項が決して、同じ請求項が前置き語句「one or more」または「at least one」、及び「a」または「an」のような不定冠詞を含む場合においても、このような要素を一つのみ含む発明に制限されるものとして解釈されてはならない。同じ解釈が定冠詞の使用に関しても当てはまる。
Claims (7)
- 半導体層上に半導体素子を製造するための方法において、
半導体層の上にゲート誘電体層を形成する工程と、
前記ゲート誘電体層の上にゲート材料層を形成する工程と、
前記ゲート材料層をパターニングしてゲート構造を形成する工程と、
前記ゲート構造をマスクとして使用して、前記半導体層にイオン注入し、それによって、イオン注入された半導体層の第1部分及び第2部分を前記ゲート構造の両側に形成する工程と、
前記ゲート構造、前記第1部分及び前記第2部分の上に窒化膜層を形成する工程と、
前記ゲート構造を貫通するようにエッチングして、第1のパターニング済みゲート構造を形成し、及び、前記半導体層を貫通するようにエッチングして、前記第1部分、前記第2部分及び前記第1のパターニング済みゲート構造を取り囲むトレンチを前記半導体層に形成する工程と、
絶縁材料が前記トレンチに充填され且つ前記窒化膜層を覆うように、絶縁材料を堆積させる工程と、
前記絶縁材料を、前記第1のパターニング済みゲート構造の上の窒化膜層の部分が露出するように平坦化する工程と、
露出した窒化膜層の部分をエッチングして、前記第1のパターニング済みゲート構造を露出させる工程と、
導電配線を前記第1のパターニング済みゲート構造に電気的に接続する工程とを備え、
ゲート構造を貫通するようにエッチングする前記工程において、第2のパターニング済みゲート構造を形成し、前記第1及び第2のパターニング済みゲート構造がトレンチの幅だけ離間することを特徴とする、方法。 - サイドウォールスペーサを前記ゲート構造の側壁に形成する工程と、
前記ゲート構造及び該サイドウォールスペーサをマスクとして使用して、前記第1部分及び前記第2部分にイオン注入する工程とをさらに備える、請求項1に記載の方法。 - 前記電気的に接続する工程は、
金属層を前記第1のパターニング済みゲート構造の上に堆積させる工程と、
前記金属層をパターニングして、該金属層の一部分を前記第1のパターニング済みゲート構造の上に残す工程とを備える、請求項1に記載の方法。 - トレンチに充填する前記工程の後に、前記半導体層の中において、ストレッサ層を前記第1部分、前記第1のパターニング済みゲート構造、及び前記第2部分の上に形成する工程をさらに備え、前記ストレッサ層が、前記第1のパターニング済みゲート構造の高さよりも高い高さを該第1及び第2部分の上に有する、請求項1に記載の方法。
- 前記ストレッサを形成する工程において、前記ストレッサが窒化物を含むことを特徴とする、請求項4に記載の方法。
- エッチングする前記工程では更に、前記第1のパターニング済みゲート構造が、前記半導体層中の前記トレンチと同じ垂直平面で終端する端部を有し、前記第1部分は前記第1のパターニング済みゲート構造の第1の側に位置するとともに、前記第2部分は第1のパターニング済みゲート構造の第2の側に位置することを特徴とする、請求項1に記載の方法。
- 前記トレンチに充填する工程は、
トレンチサイドウォールスペーサを前記トレンチの側壁に形成する工程と、
絶縁材料を前記トレンチに、前記トレンチサイドウォールスペーサを形成する工程の後に堆積させる工程を備える、請求項1に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/683,846 | 2007-03-08 | ||
US11/683,846 US7879663B2 (en) | 2007-03-08 | 2007-03-08 | Trench formation in a semiconductor material |
PCT/US2008/053133 WO2008109221A1 (en) | 2007-03-08 | 2008-02-06 | Trench formation in a semiconductor material |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2010520645A JP2010520645A (ja) | 2010-06-10 |
JP2010520645A5 JP2010520645A5 (ja) | 2011-03-24 |
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EP (1) | EP2122677A4 (ja) |
JP (1) | JP5370161B2 (ja) |
KR (1) | KR101530099B1 (ja) |
CN (1) | CN101627468A (ja) |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009130167A (ja) * | 2007-11-26 | 2009-06-11 | Renesas Technology Corp | 半導体装置およびその製造方法 |
US10573751B2 (en) * | 2012-01-23 | 2020-02-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for providing line end extensions for fin-type active regions |
JP2019106441A (ja) * | 2017-12-12 | 2019-06-27 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US10707352B2 (en) * | 2018-10-02 | 2020-07-07 | Qualcomm Incorporated | Transistor with lightly doped drain (LDD) compensation implant |
Family Cites Families (44)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4789648A (en) | 1985-10-28 | 1988-12-06 | International Business Machines Corporation | Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias |
US4988643A (en) | 1989-10-10 | 1991-01-29 | Vlsi Technology, Inc. | Self-aligning metal interconnect fabrication |
US5021848A (en) | 1990-03-13 | 1991-06-04 | Chiu Te Long | Electrically-erasable and electrically-programmable memory storage devices with self aligned tunnel dielectric area and the method of fabricating thereof |
US5019879A (en) | 1990-03-15 | 1991-05-28 | Chiu Te Long | Electrically-flash-erasable and electrically-programmable memory storage devices with self aligned tunnel dielectric area |
JPH04206775A (ja) * | 1990-11-30 | 1992-07-28 | Casio Comput Co Ltd | 薄膜トランジスタ |
JPH0521465A (ja) * | 1991-07-10 | 1993-01-29 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JPH0613615A (ja) * | 1992-04-10 | 1994-01-21 | Fujitsu Ltd | 半導体装置の製造方法 |
US5523258A (en) | 1994-04-29 | 1996-06-04 | Cypress Semiconductor Corp. | Method for avoiding lithographic rounding effects for semiconductor fabrication |
US5496771A (en) | 1994-05-19 | 1996-03-05 | International Business Machines Corporation | Method of making overpass mask/insulator for local interconnects |
US5545581A (en) | 1994-12-06 | 1996-08-13 | International Business Machines Corporation | Plug strap process utilizing selective nitride and oxide etches |
US5920108A (en) * | 1995-06-05 | 1999-07-06 | Harris Corporation | Late process method and apparatus for trench isolation |
JPH113999A (ja) * | 1997-06-13 | 1999-01-06 | Sony Corp | 半導体装置の製造方法 |
TW351849B (en) | 1997-09-11 | 1999-02-01 | United Microelectronics Corp | Method for fabricating shadow trench insulation structure |
US5998835A (en) * | 1998-02-17 | 1999-12-07 | International Business Machines Corporation | High performance MOSFET device with raised source and drain |
JPH11274508A (ja) * | 1998-03-25 | 1999-10-08 | Toshiba Corp | 薄膜トランジスタの製造方法 |
KR20000074841A (ko) | 1999-05-26 | 2000-12-15 | 윤종용 | 트렌치 격리 형성 방법 |
JP2001144170A (ja) * | 1999-11-11 | 2001-05-25 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US6359305B1 (en) | 1999-12-22 | 2002-03-19 | Turbo Ic, Inc. | Trench-isolated EEPROM flash in segmented bit line page architecture |
JP3519662B2 (ja) * | 2000-03-14 | 2004-04-19 | 松下電器産業株式会社 | 半導体装置及びその製造方法 |
JP3647384B2 (ja) * | 2000-04-04 | 2005-05-11 | 松下電器産業株式会社 | 薄膜半導体素子およびその製造方法並びに表示パネル |
JP2002033483A (ja) * | 2000-07-17 | 2002-01-31 | Sony Corp | 薄膜半導体装置の製造方法 |
KR20020042312A (ko) | 2000-11-30 | 2002-06-05 | 윤종용 | 반도체 디바이스 및 그 제조방법 |
US6624043B2 (en) * | 2001-09-24 | 2003-09-23 | Sharp Laboratories Of America, Inc. | Metal gate CMOS and method of manufacturing the same |
KR20030055997A (ko) | 2001-12-27 | 2003-07-04 | 삼성전자주식회사 | 얕은 트렌치 아이솔레이션 구조를 갖는 반도체 장치 및 그형성방법 |
US6858514B2 (en) | 2002-03-29 | 2005-02-22 | Sharp Laboratories Of America, Inc. | Low power flash memory cell and method |
US6867462B2 (en) * | 2002-08-09 | 2005-03-15 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device using an SOI substrate and having a trench isolation and method for fabricating the same |
GB0229217D0 (en) * | 2002-12-14 | 2003-01-22 | Koninkl Philips Electronics Nv | Vertical insulated gate transistor and manufacturing method |
KR100878498B1 (ko) | 2002-12-30 | 2009-01-15 | 주식회사 하이닉스반도체 | 트랜지스터 제조방법 |
US7018873B2 (en) * | 2003-08-13 | 2006-03-28 | International Business Machines Corporation | Method of making a device threshold control of front-gate silicon-on-insulator MOSFET using a self-aligned back-gate |
US6838332B1 (en) * | 2003-08-15 | 2005-01-04 | Freescale Semiconductor, Inc. | Method for forming a semiconductor device having electrical contact from opposite sides |
JP5144001B2 (ja) * | 2003-12-30 | 2013-02-13 | 三星電子株式会社 | 多結晶シリコン半導体素子及びその製造方法 |
US7087965B2 (en) * | 2004-04-22 | 2006-08-08 | International Business Machines Corporation | Strained silicon CMOS on hybrid crystal orientations |
US7141476B2 (en) * | 2004-06-18 | 2006-11-28 | Freescale Semiconductor, Inc. | Method of forming a transistor with a bottom gate |
KR100617051B1 (ko) * | 2004-12-27 | 2006-08-30 | 동부일렉트로닉스 주식회사 | 반도체 소자의 제조방법 |
US7470573B2 (en) * | 2005-02-18 | 2008-12-30 | Sharp Laboratories Of America, Inc. | Method of making CMOS devices on strained silicon on glass |
KR100653714B1 (ko) | 2005-04-12 | 2006-12-05 | 삼성전자주식회사 | 반도체소자의 제조방법 및 그에 의해 제조된 반도체소자 |
US7335932B2 (en) * | 2005-04-14 | 2008-02-26 | International Business Machines Corporation | Planar dual-gate field effect transistors (FETs) |
US7192855B2 (en) * | 2005-04-15 | 2007-03-20 | Freescale Semiconductor, Inc. | PECVD nitride film |
US7361534B2 (en) * | 2005-05-11 | 2008-04-22 | Advanced Micro Devices, Inc. | Method for fabricating SOI device |
US7732289B2 (en) * | 2005-07-05 | 2010-06-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a MOS device with an additional layer |
US7326617B2 (en) * | 2005-08-23 | 2008-02-05 | United Microelectronics Corp. | Method of fabricating a three-dimensional multi-gate device |
JP5098261B2 (ja) * | 2005-12-09 | 2012-12-12 | セイコーエプソン株式会社 | 半導体装置および半導体装置の製造方法 |
US7635620B2 (en) * | 2006-01-10 | 2009-12-22 | International Business Machines Corporation | Semiconductor device structure having enhanced performance FET device |
US7485508B2 (en) * | 2007-01-26 | 2009-02-03 | International Business Machines Corporation | Two-sided semiconductor-on-insulator structures and methods of manufacturing the same |
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2007
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TW200903711A (en) | 2009-01-16 |
JP2010520645A (ja) | 2010-06-10 |
US20080217705A1 (en) | 2008-09-11 |
KR20090125247A (ko) | 2009-12-04 |
EP2122677A1 (en) | 2009-11-25 |
TWI414039B (zh) | 2013-11-01 |
US7879663B2 (en) | 2011-02-01 |
WO2008109221A1 (en) | 2008-09-12 |
EP2122677A4 (en) | 2011-11-23 |
CN101627468A (zh) | 2010-01-13 |
KR101530099B1 (ko) | 2015-06-18 |
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