TWI639218B - 半導體元件與其製造方法 - Google Patents

半導體元件與其製造方法 Download PDF

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TWI639218B
TWI639218B TW106123511A TW106123511A TWI639218B TW I639218 B TWI639218 B TW I639218B TW 106123511 A TW106123511 A TW 106123511A TW 106123511 A TW106123511 A TW 106123511A TW I639218 B TWI639218 B TW I639218B
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Taiwan
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well
interlayer dielectric
dielectric layer
resistor wire
diffusion region
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TW106123511A
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TW201830636A (zh
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林峪群
陳柏年
蔡振華
林志勇
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台灣積體電路製造股份有限公司
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    • H01L28/20—Resistors
    • H01L28/24—Resistors with an active material comprising a refractory, transition or noble metal, metal compound or metal alloy, e.g. silicides, oxides, nitrides
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
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  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
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  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

半導體元件包括具有第一導電類型之基板、在基板中形成且具有第二導電類型之第一阱、形成在第一阱中且具有第一導電類型之第一擴散區域、設置在第一阱及此第一擴散區域上方之第一層間介電層，及由導電材料形成且經嵌入在此第一層間介電層中之電阻器導線。在平面圖中，電阻器導線與第一擴散區域重疊且至少部分地與第一阱重疊。

Description

半導體元件與其製造方法
本揭露係關於用於製造半導體元件之方法，且更特定而言係關於用於底層結構上方之電阻器導線之結構及製造方法。
在半導體元件中，諸如積體電路(integrated circuit；IC)或大型積體電路(large scale integration；LSI)，使用了多個電阻器。一些電阻器為在基板中形成之擴散區域，且一些電阻器為在底層結構上之上層中形成的導電層。隨著半導體元件尺寸愈來愈小，需要電阻器之減小的寄生電容。
根據本揭露之一個態樣，半導體元件包括具有第一導電類型之基板、在基板中形成且具有第二導電類型之第一阱、形成在第一阱中且具有第一導電類型之第一擴散區域、設置在第一阱及第一擴散區域上方之第一層間介電層及由導電材料形成且經嵌入在第一層間介電層中之電阻器導線。在平面 圖中，電阻器導線與第一擴散區域重疊且至少部分地與第一阱重疊。
根據本揭露之另一態樣，半導體元件包括具有第一導電類型之基板、形成在基板上方且由未經摻雜或本質的半導體製成之中間層、在中間層中形成之具有第一導電類型之第一擴散區域、設置在中間層及第一擴散區域上方之第一層間介電層及由導電材料形成且經嵌入在第一層間介電層中之電阻器導線。在平面圖中，電阻器導線與第一擴散區域重疊且至少部分地與中間層重疊。
根據本揭露之又一態樣，在製造半導體元件之方法中，在基板中形成第一阱。基板具有第一導電類型且第一阱具有第二導電類型。形成具有第一導電類型之第一擴散區域。在第一阱及第一擴散區域上方形成第一層間介電(ILD)層。在第一層間介電層上方形成電阻器導線。在第一層間介電層及電阻器導線上方形成第二層間介電層。電阻器導線係由導電材料製成，且在平面圖中，電阻器導線與第一擴散區域重疊且至少部分地與第一阱重疊。
1‧‧‧基板
5'‧‧‧鰭式結構
9'‧‧‧閘極結構
10‧‧‧閘極結構/虛設閘極結構
12‧‧‧帽絕緣層
12'‧‧‧帽絕緣層
14‧‧‧側壁間隔物
14'‧‧‧側壁間隔物
20‧‧‧第一阱
30‧‧‧第二阱
31‧‧‧中間層
40‧‧‧隔離絕緣層
50‧‧‧第一擴散區域
55'‧‧‧源極/汲極區域
57‧‧‧接觸層
60‧‧‧第一層間介電層
70‧‧‧第一接觸插塞
75‧‧‧第一金屬導線
80‧‧‧第二接觸插塞
85‧‧‧第二金屬導線
100‧‧‧第二層間介電層
100A‧‧‧第二層間介電層
105‧‧‧第一蝕刻終止層/第一絕緣層
120‧‧‧第三層間介電層
125‧‧‧第二蝕刻終止層/第二絕緣層
130‧‧‧第四層間介電層
135‧‧‧第三蝕刻終止層
200‧‧‧電阻器導線
300‧‧‧觸點
300A‧‧‧觸點
300B‧‧‧觸點
400‧‧‧上層金屬導線
D1‧‧‧距離
D2‧‧‧距離
L1‧‧‧長度
T1‧‧‧厚度
W1‧‧‧寬度
Z、X‧‧‧方向
本揭露當結合隨附圖式閱讀時自以下詳細描述最佳地理解。應強調，根據工業中之標準實務，各種特徵並非按比例繪製且僅出於說明目的使用。事實上，出於論述清晰之目的，可任意增加或減小各特徵之尺寸。
第1A圖至第1C圖為根據本揭露之實施例之半導體元件之各種佈局的平面圖。
第2圖為根據本揭露之實施例之半導體元件之橫截面圖。
第3圖為根據本揭露之其他實施例之半導體元件之橫截面圖。
第4圖至第7圖為根據本揭露之實施例之半導體元件製程之各種階段的橫截面示意圖。
第8圖為根據本揭露之其他實施例之半導體元件之橫截面圖。
第9圖為根據本揭露之實施例之半導體元件之橫截面圖。
第10圖為根據本揭露之實施例之半導體元件之橫截面圖。
第11圖為根據本揭露之實施例之半導體元件之橫截面圖。
第12圖為根據本揭露之其他實施例之半導體元件之橫截面圖。
第13圖為根據本揭露之其他實施例之半導體元件之橫截面圖。
應理解，以下揭露內容提供許多不同的實施例或實例用於實施本揭露之不同特徵。下文描述組件及排列之特定 實施例或實例以簡化本揭露。當然，此等僅為實例且並不意欲為限制性。舉例而言，元件之尺寸不限於所揭露之範圍或值，而可取決於製程條件及/或元件之所要特性。此外，以下描述中在第二特徵上方或在第二特徵上形成第一特徵可包括以直接接觸形成第一及第二特徵的實施例，且亦可包括可形成插入在第一與第二特徵之間的額外特徵以使得第一與第二特徵可不直接接觸的實施例。可出於簡便性及簡明性之目的任意地以不同的比例繪製各種特徵。
此外，為了便於描述，本文可使用空間相對性術語(諸如「在……之下」、「在……下方」、「下部」、「在……上方」、「上部」及類似術語)來描述如圖式中所說明之一個元件或特徵與另一元件(或多個元件)或特徵(或多個特徵)之關係。除了圖式中所描繪之定向外，空間相對性術語意欲包含使用或操作中之元件之不同定向。元件可經其他方式定向(旋轉90度或處於其他定向)且因此可同樣地解讀本文所使用之空間相對描述詞。此外，術語「由……製成」可意謂「包含」或「由……組成」。
第1A圖為根據本揭露之實施例之半導體元件之佈局結構的平面圖(自上方觀察)。第1B圖及第1C圖為根據本揭露之實施例之其他佈局結構的平面圖。第2圖為對應於第1A圖之線X1-X1之橫截面圖。
在第1A圖中，提供在Y軸方向中延伸之電阻器導線200。電阻器導線200係由導電材料製成，諸如金屬、金屬合金或金屬氮化物。由於電阻器導線200為電阻器，因此與用 於傳遞信號之其他導線相比，電阻器導線200之電導率相對較低。在一些實施例中，電阻器導線200之電阻率在約1Ω/□至約1000Ω/□範圍內。用於電阻器導線200之材料包括例如TiN、TaN或TiSiN。
電阻器導線200之大小及厚度可取決於電阻器導線200之目的或應用而變化。在一些實施例中，電阻器導線200之厚度T1(參見第2圖)在約1nm至約10nm範圍內，且在其他實施例中在約3nm至約6nm範圍內。電阻器導線200之寬度W1在約20nm至約200nm範圍內，且在其他實施例中在約40nm至約100nm範圍內。
如第1A圖及第2圖中所示，電阻器導線200包括觸點(或通孔)300A及300B，其係用於將電阻器導線200經由上層金屬導線400連接至另一電路元件。在一些實施例中，僅在電阻器導線200上提供兩個觸點300A及300B。在其他實施例中，提供四個觸點，其中兩個觸點臨近彼此排列且係用於提供其間的電流，且其餘兩個觸點臨近彼此排列且係用於量測電壓或獲得壓降。在一些實施例中，電阻器導線200之長度L1(觸點300A與300B之間的距離)在約100nm至約10μm範圍內，且在其他實施例中在約200nm至約5μm範圍內。
如第1A圖及第2圖中所示，在緊靠電阻器導線200下方，一或多個虛設結構10(例如，虛設閘極結構)及一或多個第一擴散區域50經設置在基板1上方。在一些實施例中，第一阱20(例如，P阱)在p型基板1中形成，且第二阱30(例如，N阱)在第一阱20中形成。第一阱20之電導類型與基 板1之電導類型相同且不同於第二阱30之電導類型。在某些實施例中，未形成第一阱20且第二阱30係在基板1中形成。
在一些實施例中，對於例如藉由一或多個離子植入操作及/或一或多個熱擴散操作形成之平面型FET，第一及/或第二阱為基板1之一部分。在其他實施例中，第一及/或第二阱為設置在基板1上方之鰭式結構。在某些實施例中，至少第二阱30為在X軸方向中延伸的一或多個虛設鰭式結構。
鰭式結構可藉由任何適當的方法圖案化。舉例而言，鰭式結構可使用一或多個光微影製程，包括雙圖案化或多圖案化製程來圖案化。大體上，雙圖案化或多圖案化製程結合光微影與自對準製程，從而允許建立例如間距小於使用單個直接的光微影製程可獲得之間距的圖案。舉例而言，在一個實施例中，形成在基板上方犧牲層且使用光微影製程將犧牲層圖案化。使用自對準製程沿著圖案化犧牲層形成間隔物。隨後移除犧牲層，且剩餘的間隔物或心軸可隨後用於圖案化鰭式結構。
如第1A圖及第2圖中所示，在平面圖中，電阻器導線200完全與虛設閘極結構10及第一擴散區域50重疊。此外，電阻器導線200至少部分地與第一及第二阱20、30重疊。虛設閘極結構10中之每一者可包括虛設閘極介電層及虛設閘極結構層。在本揭露中，虛設「元件」意謂此「元件」不具有電氣功能或不為功能電路之一部分，且「平面圖」意謂自上方沿著基板1之法線(Z軸方向)朝向基板1之視圖。在一些實施例中，在虛設閘極結構10上提供閘極帽絕緣層12。
在一個實施例中，複數個虛設閘極結構10經設置在第二阱30上方。虛設閘極結構之數目可小至每一電阻器導線一個，且可提供多於兩個虛設閘極結構。在第2圖中，圖示兩個虛設閘極結構10，但在電阻器導線200下方沿著X軸方向之虛設閘極結構之數目不限於兩個。複數個虛設閘極結構10在Y軸方向中延伸且在X軸方向中排列。舉例而言，如第1A圖中所示，在一些實施例中，虛設閘極結構10經設置在電阻器導線200下之2×2矩陣中。如第1A圖中所示，在平面圖中，電阻器導線200與四個虛設閘極結構10重疊。
在平面圖中，虛設閘極結構10經設置在一對觸點300A與300B之間，且因此觸點300A、300B不與虛設閘極結構10重疊。然而，在其他實施例中，觸點中之至少一者可與虛設閘極結構10重疊。
在平面圖中，第一擴散區域50亦經設置在此對觸點300A與300B之間。在一些實施例中，沿著Y軸方向之第一擴散區域50之尺寸小於沿著Y軸方向之虛設閘極結構10之尺寸，且第一擴散區域50之尺寸可等於或大於虛設閘極結構10之尺寸。在第1A圖中，在平面圖中，一個第一擴散區域50夾在兩個虛設閘極結構10之間。在其他實施例中，如第1C圖中所示，在平面圖中，多個(例如，2個、3個、4個……)第一擴散區域50夾在兩個虛設閘極結構10之間。在某些實施例中，如第1C圖中所示，在平面圖中，一個第一擴散區域50夾在兩個或兩個以上的虛設閘極結構10之間。
此外，如第1B圖中所示，第一擴散區域50不僅設置在兩個臨近的虛設閘極結構10之間且亦在各別虛設閘極結構10之一或多個相對側面處。在一些實施例中，第一擴散區域50為具有或不具有矽化物層之摻雜磊晶層。
在第1A圖中，在電阻器導線200外部，設置虛設閘極結構10。在一些實施例中，可設置主動FET而非虛設結構。在一些實施例中，在第一擴散區域50上方形成由導電材料製成之接觸層57。
在第1B圖中，在平面圖中，設置兩組電阻器導線200，虛設閘極結構10插入在此兩組電阻器導線200間。在一些實施例中，主動FET可插入在兩組電阻器導線之間。在一些實施例中，臨近的兩個電阻器導線200之間的間隔在約10nm至約2μm範圍內。此外，在第1C圖中，兩個電阻器導線200臨近彼此設置而不在其間插入虛設閘極結構。在一些實施例中，臨近的兩個電阻器導線200之間的間隔在約50nm至約1μm範圍內。
如第2圖中所示，在一些實施例中，隔離絕緣層(淺溝槽隔離(shallow trench isolation；STI))40亦經設置在第一及第二阱20、30中。在第1A圖至第1C圖中，出於簡便性目的省略隔離絕緣層40。此外，在一些實施例中，在虛設閘極結構10上方形成第一層間介電(interlayer dielectric；ILD)層60。虛設閘極結構10可嵌入在第一層間介電層60中。在一些實施例中，第二層間介電層100進一步經設置在第一層間介電層60上方，且電阻器導線200經嵌入在第二層間介電層100 中。在一些實施例中，閘極帽絕緣層12之上表面與電阻器導線200之底部之間的距離D1在約5nm至20nm範圍內。在一些實施例中，電阻器導線200之底部與上層金屬導線400之底部之間的距離D2(與第二層間介電層100之厚度相同)在約10nm至50nm範圍內。
在一些實施例中，觸點300A及300B係在第二層間介電層100中形成。在其他實施例中，電阻器導線200係在形成於第二層間介電層100上之上部層間介電層中之一者中形成，且觸點300A及300B係在設置在第二層間介電層100上之上部層間介電層中之一者中形成。
在一些實施例中，基板1為例如p型矽基板，其雜質濃度在約1×1015cm-3至約1×1018cm-3範圍內。在其他實施例中，基板為n型矽基板，其雜質濃度在約1×1015cm-3至約1×1018cm-3範圍內。或者，基板可包含另一元素半導體，諸如鍺；化合物半導體，包括第IV-IV族化合物半導體(諸如SiC及SiGe)、第III-V族化合物半導體(諸如GaAs、GaP、GaN、InP、InAs、InSb、GaAsP、AlGaN、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP)；或其組合。在一個實施例中，基板為SOI(絕緣體上矽)基板之矽層。
在一些實施例中，第一阱20為摻雜有BF2及/或In之p型阱，摻雜濃度為約1×1013至約5×1013個原子/立方公分。在其他實施例中，濃度為約2.5×1013至約3×1013個原子/立方公分。
在一些實施例中，第二阱30為摻雜有As及/或P之n型阱，摻雜濃度為約1×1013至約1×1014個原子/立方公分。在其他實施例中，濃度為約4×1013至約5×1013。在一些實施例中，植入能量為約40keV至約150keV。在一些實施例中，第二阱30為電浮動(floating)。
在一些實施例中，第一擴散區域50為摻雜有BF2及/或In之重度摻雜p型(P+)阱，摻雜濃度為約1×1014至約1×1016個原子/立方公分。在其他實施例中，濃度為約5×1014至約5×1015個原子/立方公分。
在前述結構下，形成兩個電容C1及C2且將其串聯連接。第一電容C1在電阻器導線200與第一擴散區域50(例如，p型)之間形成，且第二電容C2在第一擴散區域50與第二阱30(例如，n型)及/或第一阱20(例如，p型)(及基板(例如，p型))之間形成。串聯電容可減小電阻器導線200與基板1之間的總寄生電容。
在一些實施例中，與第二阱30為p型(與第一阱20及基板1相同)之情況相比，電阻器導線200與基板1之間的寄生電容可減小44%。
在一些實施例中，中間層31形成在第一阱20上。或者，在另一些實施例中，如第3圖所示，中間層31形成在基板1上。中間層31可為本質的或未經摻雜之半導體層，其可在不有意添加摻雜劑的情況下藉由磊晶生長形成。由本質的或未經摻雜之半導體製成之中間層31之雜質濃度小於約1×1011個 原子/立方公分。在一些實施例中，中間層31為磊晶形成之矽層。
第4圖至第11圖為橫截面圖，其說明根據本揭露之實施例之半導體元件之順序製程之各種階段。應理解，可在由第4圖至第11圖所示之製程之前、在其期間及在其之後提供額外操作，且下文描述之一些操作可經替換或除去以執行方法之額外實施例。操作/製程之次序可為可互換的。
第4圖至第7圖為橫截面圖，其說明對應於第2圖之電阻器區域。
如第4圖中所示，在基板上形成第一阱20及隔離絕緣層(isolation insulating layer；STI)40。如上文所闡述，第一阱20可為在X軸方向中延伸之鰭式結構或可為由隔離絕緣層40圍繞之體層(基板之一部分)。第一阱20係藉由具有或不具有遮罩圖案之一或多個離子植入操作形成。
隨後，如第5圖中所示，在第一阱20中形成第二阱30。第二阱30係藉由具有或不具有遮罩圖案之一或多個離子植入操作形成。
隨後，形成閘極結構10，在閘極結構10上提供閘極帽絕緣層12。在電阻器區域中，閘極結構10為虛設閘極結構。此外，在閘極結構10之相對側面上形成側壁間隔物14。
在一些實施例中，閘極結構10可為藉由閘極置換技術形成之金屬閘極結構。在其他實施例中，閘極結構10可藉由多晶矽形成。
隨後，如第7圖中所示，第一擴散區域50係藉由具有或不具有遮罩圖案之一或多個離子植入操作形成。儘管在第7圖中，第一擴散區域50僅在兩個閘極結構10之間形成，但在其他實施例中，第一擴散區域係在閘極結構之相對側面形成。第一擴散區域50可在側壁間隔物14形成之前形成。
第8圖至第11圖為電阻器區域及電路區域之橫截面圖，其中形成主動電路元件。第8圖至第11圖說明電阻器區域以及電路區域均包括主動FET。
第8圖為在閘極結構由第一層間介電(ILD)層60覆蓋之後的半導體元件之結構。在第8圖之電路區域中，閘極結構9’係在通道層，例如鰭式結構5’之一部分上方形成及帽絕緣層12’經設置在閘極結構9’上方。在一些實施例中，閘極結構9’為包括高介電常數閘極介電層之金屬閘極結構。鰭式結構5’自隔離絕緣層40突出。在一些實施例中，金屬閘極結構9’之厚度在15nm至50nm範圍內。在一些實施例中，帽絕緣層12’之厚度在約10nm至約30nm範圍內，且在其他實施例中此厚度在約15nm至約20nm範圍內。在金屬閘極結構9’及帽絕緣層12’之側壁上提供側壁間隔物14’。在一些實施例中，在側壁間隔物底部的側壁間隔物14’之薄膜厚度在約3nm至約15nm範圍內，且在其他實施例中此薄膜厚度在約4nm至約10nm範圍內。金屬閘極結構9’、帽絕緣層12’與側壁間隔物14’之組合可共同地稱為閘極結構。此外，源極/汲極(source/drain；S/D)區域55’臨近閘極結構形成，且閘極結構之間的間隔係由第一層間介電層60填充。S/D區域55’為摻雜區域及/或磊晶形 成區域，其具有一或多個半導體層。在一些實施例中，在S/D區域55’上形成矽化物層，諸如WSi、CoSi、NiSi或TiSi。
類似地，在電阻器區域中，形成實質上相同的結構。虛設閘極結構10形成在基板上方，其在上文關於第4圖至第7圖描述。
在此實施例中，使用藉由閘極置換製程製造之鰭式場效電晶體(鰭式FET)。金屬閘極結構9’及/或10包括一或多個金屬材料層，諸如Al、Cu、W、Ti、Ta、TiN、TiAl、TiAlC、TiAlN、TaN、NiSi、CoSi、其他導電材料。設置在通道層與金屬閘極之間的閘極介電層包括一或多個金屬氧化物層，諸如高介電常數金屬氧化物層。用於高介電常數介電質之金屬氧化物之實例包括Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu之氧化物及/或其混合物。在一些實施例中，一或多個功函數調節層經插入在閘極介電層與金屬材料之間。功函數調節層係由導電材料製成，諸如TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC之單層，或此等材料中之兩者或兩者以上之多層。對於n通道場效電晶體，TaN、TaAlC、TiN、TiC、Co、TiAl、HfTi、TiSi及TaSi中之一或多者用作功函數調節層；且對於p通道場效電晶體，TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC及Co中之一或多者用作功函數調節層。
帽絕緣層12、12’包括一或多個絕緣材料層，諸如基於氮化矽之材料，包括SiN、SiCN及SiOCN。側壁間隔 物14、14’係由與帽絕緣層不同的材料製成且包括一或多個絕緣材料層，諸如基於氮化矽之材料，包括SiN、SiON、SiCN及及SiOCN。第一層間介電層60包括一或多個絕緣材料層，諸如基於氧化矽之材料層，包括二氧化矽(SiO2)、氮氧化矽、碳氧化矽或氮碳氧化矽或其他低介電常數材料。
側壁間隔物之材料、帽絕緣層之材料及第一層間介電層之材料彼此不同，以使得此等層中之每一者均可經選擇性地蝕刻。在一個實施例中，側壁間隔物係由SiOCN、SiCN或SiON製成，帽絕緣層係由SiN製成，且第一層間介電層60係由SiO2製成。
隨後，如第9圖中所示，在第一層間介電層60上方形成第二層間介電層之下部100A。在一些實施例中，在後續接觸孔蝕刻操作中充當第一蝕刻終止層(etch stop layer；ESL)之第一絕緣層105經設置在第一層間介電層60與第二層間介電層之下部100A之間。
第一絕緣層105包括一或多個基於氮化矽之材料層，諸如SiN、SiCN或SiOCN。第二層間介電層之下部100A包括一或多個絕緣材料層，諸如基於氧化矽之材料，諸如二氧化矽(SiO2)、氮氧化矽、碳氧化矽或氮碳氧化矽或其他低介電常數材料。
在形成第二層間介電層之下部100A之後，在第二層間介電層之下部100A上形成電阻器導線200，如第9圖中所示。在第二層間介電層之下部100A上方形成導電材料之毯覆層，且執行圖案化操作以便獲得電阻器導線200。毯覆層可藉 由化學氣相沉積(chemical vapor deposition；CVD)、物理氣相沉積(physical vapor deposition；PVD)(包括濺射)或其他適當的薄膜形成方法形成。
隨後，在第二層間介電層之下部100A上方形成第二層間介電層100之上部，且電阻器導線200經嵌入在第二層間介電層100中，如第10圖中所示。在一些實施例中，在電路區域中，藉由使用例如雙鑲嵌製程形成第一接觸插塞70及第一金屬導線75，如第10圖中所示。第一接觸插塞70及第一金屬導線75包括一或多個Cu、Al、Ti、Co、W或Ni或其合金或TiN或TaN之層。
此外，如第11圖中所示，在第二層間介電層100上方形成第三層間介電層120。在一些實施例中，充當後續接觸孔蝕刻操作中之第二蝕刻終止層之第二絕緣層125經設置在第二層間介電層100與第三層間介電層120之間。第三層間介電層120及第二蝕刻終止層125之材料或配置類似於第二層間介電層100及第一蝕刻終止層105之材料或配置。
在形成第三層間介電層120之後，形成連接至電阻器導線200之觸點300，如第11圖中所示。
在一些實施例中，在電路區域中，第二接觸插塞80及第二金屬導線85係藉由使用例如雙或單鑲嵌製程形成，如第11圖中所示。觸點300可與第二接觸插塞80及/或第二金屬導線85同時形成。第二接觸插塞80及第二金屬導線85之材料或配置類似於第一接觸插塞70及第一金屬導線75之材料或配置。
第12圖為電阻器導線結構之另一實施例。在第12圖中，電阻器導線200經嵌入在第三層間介電層120中。
在形成第8圖之結構之後，在第一層間介電層60上方形成第二層間介電層100及第一蝕刻終止層105。在一些實施例中，在電路區域中形成第一接觸插塞70及第一金屬導線75。隨後，在第二層間介電層100上方形成第三層間介電層120之下部。在一些實施例中，充當後續接觸孔蝕刻操作中之第二蝕刻終止層之第二絕緣層125經設置在第二層間介電層100與第三層間介電層120之下部之間。
在形成第三層間介電層120之下部之後，在第三層間介電層120之下部上形成電阻器導線200。隨後，在第三層間介電層之下部上方形成第三層間介電層120之上部，且電阻器導線200經嵌入在第三層間介電層120中。此外，如第12圖中所示，在第三層間介電層120中形成觸點300。在一些實施例中，在電路區域中，第二接觸插塞80及第二金屬導線85係藉由使用例如雙鑲嵌製程形成。在一些實施例中，觸點300與第二接觸插塞80及/或第二金屬導線85同時形成。
第13圖圖示本揭露之另一實施例之橫截面圖。在第13圖中，電阻器導線200經嵌入在上部(例如，第四)層間介電層130中。
在形成第10圖之結構之後，在第二層間介電層100上方形成第三層間介電層120及第二蝕刻終止層125。在形成第三層間介電層120之後，在一些實施例中，在電路區域中，形成第二接觸插塞80及第二金屬導線85。隨後，藉由使用與 關於第9圖至第11圖類似的操作，形成第三蝕刻終止層135、第四層間介電層130、電阻器導線200及觸點300，如第13圖中所示。
當在其中形成電阻器導線200之層間介電層下進一步形成一或多個層間介電層時，重複前述操作。
應理解，第11圖、第12圖及第13圖中所示的元件經受進一步互補金屬氧化物半導體(complementary metal oxide semiconductor；CMOS)製程以形成各種特徵，諸如互連金屬層、介電層、鈍化層等等。
在前述實施例中，電阻器導線200在Y軸方向中延伸。但電阻器導線200之佈局不限於此佈局，且一些電阻器導線200在X軸方向中延伸。
本文描述之各種實施例或實例提供若干優於現有技術之優點。舉例而言，在本揭露中，在電阻器導線下，形成串聯連接的兩個電容C1及C2。第一電容C1在電阻器導線與第一擴散區域(例如，p型)之間形成，且第二電容C2在第一擴散區域與第二阱(例如，n型)及/或第一阱(例如，p型)(及基板(例如，p型))之間形成。串聯電容可減小電阻器導線與基板之間的總寄生電容。與第二阱為p型(與第一阱及基板相同)之情況相比，電阻器導線與基板之間的寄生電容可減小44%。
將理解，本文不一定已論述所有的優點，不存在所有實施例或實例均需要之特定優點，且其他實施例或實例可提供不同的優點。
根據本揭露之一個態樣，半導體元件包括具有第一導電類型之基板、在基板中形成且具有第二導電類型之第一阱、形成在第一阱中且具有第一導電類型之第一擴散區域、設置在第一阱及第一擴散區域上方之第一層間介電層及由導電材料形成且經嵌入在第一層間介電層中之電阻器導線。在平面圖中，電阻器導線與第一擴散區域重疊且至少部分地與第一阱重疊。
根據本揭露之另一態樣，半導體元件包括具有第一導電類型之基板、形成在基板上方且由未經摻雜或本質的半導體製成之中間層、在中間層中形成之具有第一導電類型之第一擴散區域、設置在中間層及第一擴散區域上方之第一層間介電層及由導電材料形成且經嵌入在第一層間介電層中之電阻器導線。在平面圖中，電阻器導線與第一擴散區域重疊且至少部分地與中間層重疊。
根據本揭露之又一態樣，在製造半導體元件之方法中，在基板中形成第一阱。基板具有第一導電類型且第一阱具有第二導電類型。形成具有第一導電類型之第一擴散區域。在第一阱及第一擴散區域上方形成第一層間介電(ILD)層。在第一層間介電層上方形成電阻器導線。在第一層間介電層及電阻器導線上方形成第二層間介電層。電阻器導線係由導電材料製成，且在平面圖中，電阻器導線與第一擴散區域重疊且至少部分地與第一阱重疊。
前述內容概述若干實施例或實例之特徵，以使得熟習此項技術者可較佳理解本揭露之態樣。熟習此項技術者應 理解，其可容易地使用本揭露作為設計或修改用於執行本文所介紹之實施例或實例之相同目的及/或達成相同優點的其他製程及結構之基礎。熟習此項技術者應同時認識到，此等等效構造不偏離本揭露之精神及範疇，且其可在不偏離本揭露之精神及範疇之情況下於本文中進行各種變化、替換及變更。

Claims (10)

  1. 一種半導體元件，包含：一基板，具有一第一導電類型；一第一阱，形成在該基板中且具有一第二導電類型；一第一擴散區域，形成在該第一阱中且具有該第一導電類型；一第一層間介電層，設置在該第一阱及該第一擴散區域上方；及一電阻器導線，由一導電材料形成且嵌入在該第一層間介電層中，其中在平面圖中，該電阻器導線與該第一擴散區域重疊且至少部分地與該第一阱重疊。
  2. 如請求項1所述之半導體元件，更包含設置在該第一阱上方之一虛設結構，其中在平面圖中，該電阻器導線與該虛設結構重疊。
  3. 如請求項2所述之半導體元件，其中：該虛設結構包括兩個或兩個以上虛設閘極結構，該兩個或兩個以上虛設閘極結構設置在該第一阱上方且在一第一方向中延伸且以垂直於該第一方向之一第二方向排列，及該電阻器導線在該第一方向中延伸。
  4. 如請求項3所述之半導體元件，其中沿著該第一方向，該電阻器導線比該虛設閘極結構長。
  5. 如請求項1所述之半導體元件，更包含在該基板中形成之具有該第二導電類型之一第二阱，其中該第一阱係在該第二阱中形成。
  6. 一種半導體元件，包含：一基板，具有一第一導電類型；一中間層，在該基板上方形成且係由未經摻雜或本質的半導體製成；一第一擴散區域，在該中間層中形成且具有該第一導電類型；一第一層間介電層，設置在該中間層及該第一擴散區域上方；一電阻器導線，由一導電材料形成且經嵌入在該第一層間介電層中，其中在平面圖中，該電阻器導線與該第一擴散區域重疊且至少部分地與該中間層重疊。
  7. 如請求項6所述之半導體元件，更包含一虛設結構，設置在該中間層上，其中在平面圖中，該電阻器導線與該虛設結構重疊，其中：該虛設結構包括兩個或兩個以上虛設閘極結構，該兩個或兩個以上虛設閘極結構設置在該中間層上方且在一第一方向中延伸且以垂直於該第一方向之一第二方向排列，及該電阻器導線在該第一方向中延伸。
  8. 如請求項7所述之半導體元件，其中沿著該第一方向，該電阻器導線比該虛設閘極結構長。
  9. 一種製造半導體元件之方法，該方法包含：在一基板中形成一第一阱，該基板具有一第一導電類型且該第一阱具有一第二導電類型；形成具有該第一導電類型之一第一擴散區域；在該第一阱及該第一擴散區域上方形成一第一層間介電(interlayer dielectric；ILD)層；在該第一層間介電層上方形成一電阻器導線；在該第一層間介電層及該電阻器導線上方形成一第二層間介電層，其中：該電阻器導線係由一導電材料製成，及在平面圖中，該電阻器導線與該第一擴散區域重疊且至少部分地與該第一阱重疊。
  10. 如請求項9所述之方法，更包含，在形成該第一層間介電層之前在該第一阱上方形成由一導電材料製成之虛設閘極結構。
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