TW201905982A - 半導體結構及其製作方法 - Google Patents

半導體結構及其製作方法

Info

Publication number
TW201905982A
TW201905982A TW106142600A TW106142600A TW201905982A TW 201905982 A TW201905982 A TW 201905982A TW 106142600 A TW106142600 A TW 106142600A TW 106142600 A TW106142600 A TW 106142600A TW 201905982 A TW201905982 A TW 201905982A
Authority
TW
Taiwan
Prior art keywords
region
semiconductor
semiconductor substrate
fin active
fin
Prior art date
Application number
TW106142600A
Other languages
English (en)
Other versions
TWI672736B (zh
Inventor
沈澤民
吳志強
吳忠政
蔡慶威
程冠倫
王志豪
曹敏
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201905982A publication Critical patent/TW201905982A/zh
Application granted granted Critical
Publication of TWI672736B publication Critical patent/TWI672736B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76275—Vertical isolation by bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7846—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the lateral device isolation region, e.g. STI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本揭露提供一種半導體結構。此半導體結構包含具有第一區域及第二區域的半導體基材；第一半導體材料的第一鰭片主動區域配置於第一區域，並以第一方向定向，其中第一鰭片主動區域沿第一方向具有晶體方向<100>；以及第二半導體材料的第二鰭片主動區域配置於第二區域，並以第一方向定向，其中第二鰭片主動區域沿第一方向具有晶體方向<110>。

Description

具有混合定向的鰭式場效電晶體的 積體電路結構及方法
半導體積體電路(integrated circuit,IC)產業經歷了指數成長。積體電路材料及設計的科技進步產生了許多世代的積體電路，其中每個世代具有比前代更小且更複雜的電路。在積體電路的發展過程中，一般來說，功能密度(functional density)(如每單位晶片面積的互連元件的數量)提升，而幾何尺寸(可以使用製程製造的最小組件或線)減小。這種縮小的過程一般藉由增加生產效率及降低相關成本來提供優點。
為了實現這些進展，這樣的縮小亦增加了IC的加工及製造的複雜度。IC加工及製造的類似發展是需要的。舉例來說，諸如鰭式場效電晶體(FinFET)的三維電晶體已被引入以取代平面電晶體。此外，期望的載子移動率(carrier mobility)也隨著元件速度及效能而提高。然而，現有的結構及相關的方法並不適用於包含鰭式場效電晶體的三維結構。
雖然現有的鰭式場效電晶體元件及鰭式場效電 晶體元件的製造方法通常已經足夠用於其預期的目的，但是它們不是在所有方面都完全令人滿意的。舉例來說，現有的結構及相關方法不適合或沒有針對包含鰭式場效電晶體的三維結構進行最佳化，特別是高移動率的通道。因此，需要積體電路結構及其製造方法以解決上述問題。
100‧‧‧方法
102、104、106、108、110、112、116、118、122、124、126‧‧‧操作
200‧‧‧半導體結構
202‧‧‧第一半導體基材
204‧‧‧第二半導體基材
206、208‧‧‧標示/晶體方向
302‧‧‧角度
304、306‧‧‧上表面
502‧‧‧氧化矽層
602‧‧‧第一區域
604‧‧‧第二區域
608‧‧‧硬遮罩
610‧‧‧圖案化光阻層
702‧‧‧溝槽
704‧‧‧間隔
802、804‧‧‧半導體材料層
1002、1004‧‧‧鰭片主動區域
1102‧‧‧淺溝槽隔離特徵
1106‧‧‧奈米線
1202‧‧‧n型鰭式場效電晶體
1204‧‧‧p型鰭式場效電晶體
1206、1222‧‧‧源極
1208、1224‧‧‧汲極
1212、1226‧‧‧閘極
1236、1238‧‧‧方向
1302、1304‧‧‧實驗數據
1306、1308‧‧‧數據
X、Y‧‧‧方向
當結合隨附圖式閱讀時，自以下詳細描述將很好地理解本揭露。應強調，根據工業中的標準實務，各特徵並非按比例繪製且僅用於說明之目的。事實上，為了論述清晰之目的，可任意增加或減小特徵之尺寸。
第1圖繪示根據一些實施例的積體電路製造方法的流程圖。
第2圖繪示根據一些實施例建構的相結合以形成半導體結構的兩半導體基材的上視圖。
第3圖繪示根據一些實施例建構的相結合以形成半導體結構的兩半導體基材的透視圖。
第4圖繪示根據一些實施例建構的在製程階段的半導體結構的上視圖。
第5、6、7、8、9、10及11A圖繪示根據一些實施例建構的在各個製程階段的半導體結構的剖面圖。
第11B圖繪示根據一些實施例建構的半導體結構的剖面圖。
第12A圖繪示根據一些實施例的部分半導體結構的上視圖。
第12B圖繪示根據一些實施例的部分半導體結構的透視圖。
第13A及13B圖繪示根據一些實施例建構的半導體結構的實驗數據圖。
以下揭示內容提供許多不同實施例或示例，用於實施本揭露之不同特徵。下文描述組件及排列之特定實例以簡化本揭露書的內容。當然，該等實例僅為示例且並不意欲為限制性。舉例而言，以下描述中在第二特徵上方或第二特徵上形成第一特徵可包括以直接接觸形成第一特徵及第二特徵的實施例，且亦可包括可在第一特徵與第二特徵之間形成額外特徵以使得第一特徵及第二特徵可不處於直接接觸的實施例。另外，本揭露可在各實例中重複元件符號及/或字母。此重複本身並不指示所論述之各實施例及/或配置之間的關係。
進一步地，為了便於描述，本文可使用空間相對性用語(諸如「之下」、「下方」、「下部」、「上方」、「上部」及類似者)來描述諸圖中所圖示一個元件或特徵與另一元件(或多個元件)或特徵(或多個特徵)之關係。除了諸圖所描繪之定向外，空間相對性用語意欲包含元件在使用或操作中之不同定向。裝置可經其他方式定向(旋轉90度或處 於其他定向)且因此可同樣解讀本文所使用之空間相對性描述詞。
本揭露係涉及鰭式場效電晶體(FinFET)元件，但不限於此。鰭式場效電晶體元件，舉例來說，可以為包含p型金屬氧化物半導體(PMOS)鰭式場效電晶體元件及n型金屬氧化物半導體(NMOS)鰭式場效電晶體元件的互補式金屬氧化物半導體(complementary metal-oxide-semiconductor,CMOS)。以下揭露將繼續以鰭式場效電晶體的示例說明本揭露的各種實施例。然而，須了解到，除非特別指明，本揭露的應用不應限制於特定類型的元件。
第1圖為製作半導體結構200(特別是包含具有一或多個鰭式場效電晶體元件的鰭式場效電晶體結構)的方法100的流程圖，而半導體結構200是根據一些實施例所建構。根據一些實施例，第2圖為兩個半導體基材的上視圖，此二半導體基材結合以形成半導體結構200；第3圖為結合兩個半導體基材的透視圖。第4圖為在製程階段的半導體結構200的上視圖。第5圖至第11圖為在各個製程階段的半導體結構200的剖面圖。第12A圖為半導體結構200的局部上視圖。第12B圖為半導體結構200的局部透視圖。第13A圖及第13B圖繪示根據一些示例的半導體結構200的實驗數據圖。須了解到，可以在此方法之前、期間以及之後執行額外的步驟，且在其他的實施例的方法中，一些上述的步驟可以被取代或移除。參照第1圖至第13B圖，一併說明半導體 結構200及其製作方法100。
如第2圖的上視圖所示，方法100由半導體基材202及半導體基材204開始。詳細的說，第一半導體基材202與第二半導體基材204的晶體結構及平面定向(plane orientation)相同。在本實施例中，第一半導體基材202及第二半導體基材204皆為矽基材，例如矽晶圓。在進一步的本實施例中，第一半導體基材202及第二半導體基材204為具有相同平面定向的晶體結構的矽晶圓，例如本示例的(100)。這裡的(xyz)為代表結晶矽晶圓上表面的平面定向的密勒指數(miller index)。因此，如第2圖所示，半導體基材202及204的晶體方向<100>為各自基材的上表面的標示206及208。這裡的<100>為另一個代表結晶半導體基材的晶體方向族的密勒指數。
儘管在本實施例中這兩個半導體基材為矽基材。然而，揭露的結構及方法並不限於此，且可以延伸至其他合適的半導體基材及其他合適的定向。舉例來說，基材210可以包含元素半導體，例如晶體結構中的鍺；化合物半導體，例如矽鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、和/或銻化銦或其組合。在進一步的實施例中，那些半導體材料膜可以磊晶成長於矽晶圓上。
參考第1圖，方法100包含操作102，以一個定向偏移結合兩個半導體基材202及204。在本實施例中，以使得兩個基材202及204的相同晶體方向(例如<100>)具有45度角的方式將兩個基材202及204結合在一起。操作102 在後續更進一步描述。
如第3圖所示，旋轉第一基材202及第二基材204，並配置使得對應的<100>晶體方向之間具有角度302的偏移。角度302為45度。在本實施例中，如第3圖所示，第一基材202的上表面304及第二基材204的上表面306配置為面向相同方向。
兩個基材202及204藉由合適的結合技術以這樣的配置結合在一起，例如直接結合、共晶結合(eutectic bonding)、熔合結合(fusion bonding)、擴散結合(diffusion bonding)、陽極結合(anodic bonding)或其他適合的結合方法。在一個實施例中，基材藉由直接矽結合(direct silicon bonding,DSB)而結合在一起。舉例來說，直接矽結合製程可以包含預處理、在較低的溫度下預結合以及在較高的溫度下退火。當兩個基材結合在一起時，可以形成埋藏氧化矽層(buried silicon oxide layer,BOX)。在一些示例中，熱矽氧化物膜藉由熱氧化形成於一個結合表面(或兩個結合表面：第一基材202的上表面及第二基材204的下表面)。接著結合表面定位成具有如上所述的第3圖所示的定向和配置。結合表面藉由加熱及機械壓力結合在一起。加熱的溫度可以為1000℃或更高。在結合製程期間，加熱及機械壓力可以具有不同的設定，以最佳化結合的效果。舉例來說，結合製程可以包含兩個步驟：第一步驟在室溫下使用機械壓力，而第二步驟在高於1000℃下熱退火。在一些示例中，可以薄化半導體基材202及204之中至少一者，例 如藉由研磨或拋光，以在結合前或結合後達到合適厚度。在一個替代的實施例中，可以藉由矽表面直接結合的方式消除埋藏氧化矽層。在另一個實施例中，熱退火溫度可以減低至相對較低的溫度，例如介於400℃至450℃之間。
第4圖繪示結合的兩個基材的上視圖。X方向及Y方向為笛卡兒座標系(Cartesian coordinate)，且定義於(100)平面表面上。第二基材204的<100>晶體方向208係沿著Y軸，而第一基材202的<100>晶體方向206係沿著X軸及Y軸之間的對角線方向，此方向與Y軸夾角為45度的角度302。特別的是，第一基材202具有沿Y軸的晶體方向<110>。
第5圖為具有結合在一起的第一基材202及第二基材204的半導體結構200的剖面圖。在本實施例中，氧化矽膜502介於兩個基材之間。同樣的，基材的上表面為(100)定向，但第一基材202相對於第二基材204具有45度的旋轉，使得第一基材202沿Y軸具有晶體方向<110>，而第二基材204沿Y軸具有晶體方向<100>。
請參考第1圖及第6圖，方法100進行至操作104，形成圖案化遮罩於半導體結構200的第二基材204上。半導體結構200包含第一區域602的n型場效電晶體(NFET)及第二區域604的p型場效電晶體(PFET)。圖案化遮罩覆蓋第一區域602並包含暴露出第二區域604的開口。圖案化遮罩可以為軟遮罩(例如圖案化光阻層)或硬遮罩(例如介電材料層)。在本實施例中，使用的是硬遮罩。硬遮罩 608配置於第二基材204的上表面上；使用微影製程形成圖案化光阻層610於硬遮罩608上；以及蝕刻硬遮罩608以把開口從圖案化光阻層610轉移至硬遮罩608。在一些示例中，硬遮罩608包含隨後沉積在半導體結構200上的氧化矽及氮化矽。硬遮罩608可以藉由熱氧化、化學氣相沉積(chemical vapor deposition,CVD)、原子層沉積(atomic layer deposition,ALD)、任何其他合適的方法或其組合形成。例示性的微影製程可以包含形成光阻層、使用微影曝光製程曝光光阻、執行曝光後烘烤(post-exposure bake)製程及顯影光阻層以形成圖案化光阻層。微影製程可以用其他技術替代性地置換，例如電子束描劃(e-beam writing)、離子束描劃(ion-beam writing)、無遮罩圖案化(maskless patterning)或分子印刷(molecular printing)。在一些其他實施例中，圖案化光阻層可以直接作為隨後的蝕刻製程的蝕刻遮罩。在硬遮罩608形成之後，圖案化光阻層610可以藉由合適的製程移除，例如濕式剝離(wet stripping)或電漿灰化(plasma ashing)。
參考第1圖及第7圖，方法100包含操作106，蝕刻第二區域604的第二半導體基材204，直到第二區域604的第一基材202暴露出來，形成溝槽702。蝕刻製程設計為使用硬遮罩608作為蝕刻遮罩選擇性的移除第二區域604的半導體材料。可以繼續蝕刻製程以凹陷第一半導體基材202或確保第二區域604的第一半導體基材202暴露出來。蝕刻製程可以包含乾蝕刻、濕蝕刻或其組合。圖案化遮罩608保 護第一區域602的第二基材204不被蝕刻。在各種示例中，蝕刻製程包含使用合適的蝕刻劑的乾蝕刻，例如含氟蝕刻氣體或含氯蝕刻氣體，例如Cl2、CCl2F2、CF4、SF6、NF3、CH2F2或其他合適的蝕刻氣體。在一些其他的示例中，蝕刻製程包含使用合適的蝕刻劑的濕蝕刻，例如KOH溶液。蝕刻製程可以包含多於一個步驟。舉例來說，蝕刻製程可以包含第一蝕刻步驟蝕刻第二基材204的矽材料，以及第二蝕刻步驟蝕刻氧化矽層502。在又一示例中，蝕刻製程包含使用含氟蝕刻氣體或含氯蝕刻氣體的乾蝕刻步驟以蝕刻矽，以及使用氫氟酸溶液的濕蝕刻步驟以蝕刻氧化矽。在一些實施例中，間隔704可以形成於溝槽702的側壁上。間隔704可以包含介電材料於溝槽702的側壁上，以使得隨後在溝槽702中磊晶生長的半導體材料可以具有第一半導體基材202的晶體定向，而不會被第二基材204影響。此外，間隔704提供第一區域602及第二區域604之間的隔離。間隔704可以藉由包含沉積(例如化學氣相沉積或物理氣相沉積)及諸如乾蝕刻的非等向性蝕刻的製程形成。在一些示例中，間隔704包含氮化矽、氧化矽、氮化鈦或其組合。
參考第1圖及第8圖，方法100進行至操作108，從第二區域604的第一半導體基材202磊晶成長半導體材料802。半導體材料802填充溝槽702。在一個實施例中，半導體材料802不同於第二半導體基材204的半導體材料，以達到提升移動率的應變效果。舉例來說，第二半導體材料802為矽鍺(SiGe)。在其他示例中，第二半導體材料802可 以為矽、鍺或其他合適的元素半導體材料或化合物半導體材料。在一些實施例中，操作108的磊晶成長可以包含多於一個步驟，以成長不同半導體材料的多層半導體，達到提升元件效能及其他目的。在本實施例中，操作108包含矽的第一磊晶成長以形成矽層804及矽鍺的第二磊晶成長以形成矽鍺層802。
參考第1圖及第9圖，方法100可以進行至操作110，執行諸如化學機械研磨(chemical mechanical polishing,CMP)的拋光製程以平坦化上表面。硬遮罩608可以作為CMP製程期間的拋光停止層，並且在CMP之後藉由蝕刻移除。或者，硬遮罩608可以藉由CMP製程移除。
半導體層802從半導體層804垂直生長，且大致填充溝槽702。在本實施例中，由於間隔704的存在，半導體層802與間隔704之間可能會有間隙。在這種情況下，操作110的拋光製程額外移除或減少這樣的間隙。
因為半導體材料802是從相對於第二半導體基材204旋轉的第一半導體基材202磊晶成長而形成的，半導體材料802是晶體結構，且具有與第一半導體基材202相同的晶體定向。舉例來說，第二區域604的第二半導體材料802的上表面還是(100)晶體平面，而第一區域602的第二半導體基材204的上表面亦具有(100)晶體平面。然而，由於旋轉的緣故，這兩個區域的晶體方向不同。特別的是，第一區域602的第二半導體基材204沿著X軸及Y軸具有<100>晶體方向，而第二區域604的第二半導體材料802沿著X軸與Y 軸之間的對角線方向具有<100>晶體方向。此外，第二區域604的第二半導體材料802具有沿X軸及Y軸定向的晶體方向<110>。
參考第1圖及第10圖，方法100可進行至操作112，形成鰭式主動區域1002於第一區域602以及鰭式主動區域1004於第二區域604。鰭式主動區域(或簡稱為鰭片或鰭片特徵)係為三維半導體特徵，各種元件形成於其上，例如場效電晶體(FET)。
在一些實施例中，鰭片1002及鰭片1004藉由任何合適的製程形成，包含沉積、微影和/或蝕刻製程。在一個實施例中，藉由圖案化半導體結構200(第一區域602的第二基材204及第二區域604的半導體材料802)形成溝槽而形成鰭片1002及鰭片1004。在進一步的實施例中，半導體結構200的圖案化可以包含形成硬遮罩；通過硬遮罩的開口對半導體結構200進行蝕刻製程，以形成溝槽於半導體結構200中。硬遮罩可以藉由包含沉積硬遮罩材料層及蝕刻硬遮罩材料層的製程而形成。在一些示例中，硬遮罩材料層包含隨後沉積於半導體結構200上的氧化矽層及氮化矽層。硬遮罩材料層可以藉由熱氧化、化學氣相沉積(CVD)、原子層沉積(ALD)或其他適合的方法形成。形成圖案化硬遮罩的製程更包含使用微影製程形成圖案化光阻層以及通過圖案化光阻層的開口蝕刻硬遮罩材料層，以將開口轉移至硬遮罩材料層。在一些其他實施例中，圖案化光阻層可以直接用作為形成溝槽的蝕刻製程的蝕刻遮罩。如第10圖所示，蝕刻製 程可以包含多於一個步驟，且可以繼續蝕刻穿過第一區域602的氧化矽層502及第二區域604的矽層802，直到第一半導體基材202。
第一區域602的鰭片1002可以稱為n型鰭片，因為其中的半導體材料適當的摻雜以形成n型場效電晶體。精確地說，半導體材料摻雜諸如硼的p型摻雜劑。類似地，第二區域604的鰭片1004可以稱為p型鰭片，因為它們最終會適當地摻雜以形成p型電晶體。精確地說，它們會摻雜諸如磷的n型摻雜劑。摻雜劑可以藉由離子植入(ion implantation)或原位摻雜(in-situ doping)被引入對應的區域中。
鰭片具有拉長的形狀並且在Y方向上定向。特別的是，由於上述旋轉的緣故，n型鰭片1002沿Y方向具有晶體方向<100>，而p型鰭片1004沿Y方向具有晶體方向<110>。此外，n型鰭片1002的X方向及Y方向皆具有晶體方向<100>，而p型鰭片1004的X方向及Y方向皆具有晶體方向<110>。另外，如第10圖所示，n型鰭片1002及p型鰭片的側壁表面定向依序為(001)及(110)。
參考第1圖及第11A圖，方法100可以進行至操作116，形成淺溝槽隔離(shallow trench isolation,STI)特徵1102以隔開各個鰭式主動區域。STI特徵1102的形成更可以包含第一操作122用一或多種介電材料填充溝槽；第二操作124拋光半導體結構200以移除多餘的介電材料並平坦化上表面；以及第三操作126使用選擇性蝕刻使STI特徵 1102凹陷。第二操作124用介電材料填充填充溝槽可以包含用對應的介電材料填充的一或多個步驟。舉例來說，用熱氧化製程形成熱氧化矽層於溝槽中，及用包含CVD的合適技術，例如高密度電漿CVD(HDPCVD)或流動式CVD(FCVD)，填充諸如氧化矽的另一個介電材料於溝槽中。第三操作126使介電材料凹陷可以包含蝕刻製程(例如濕蝕刻、乾蝕刻或其組合)選擇性回蝕介電材料，形成STI特徵1102。
或者，例如第11B圖所示，半導體結構200可以具有不同結構。在第11B圖的半導體結構200中，鰭片主動區域1004由複數個堆疊的奈米線1106取代，因此複數個通道定義於奈米線1106中。根據一些示例，奈米線1106的形成在此進一步說明。在操作108中，磊晶成長包含磊晶成長替代的半導體材料，例如Si、SiGe、Si或SiGe。在操作112中，形成鰭片主動區域包含圖案化半導體材料(如上所述)以及更包含選擇性蝕刻製程以選擇性移除一種半導體材料，而使其他半導體材料殘留，例如選擇性移除矽(或在替代性的示例中選擇性移除矽鍺)，因而形成奈米線1106。因此，各種諸如場效電晶體的元件可以形成於第11A圖的鰭片1002及鰭片1004上，或者可以形成於第11B圖的鰭片1002及奈米線1106上。
回頭參考第1圖，方法100可以進行至操作118，形成n型場效電晶體於第一區域602的n型鰭片1002及p型場效電晶體於第二區域604的p型鰭片1004(或奈米 線1106)。或者，諸如場效電晶體、偶極電晶體(dipole transistors)、二極體(diodes)、被動元件(電阻、電感、電容或其組合)或其組合等各種半導體元件形成於鰭片上。在第12A圖及第12B圖繪示的本實施例中，例示性的n型場效電晶體1202及p型場效電晶體1204依序形成於鰭片1002及鰭片1004上，而因此稱為鰭式場效電晶體(FinFET)。第12A圖為根據一些實施例的半導體結構200的上視圖，而第12B圖則為其示意圖。在第12A圖及第12B圖中，僅繪示一個n型鰭式場效電晶體1202於第一區域602及一個p型鰭式場效電晶體1204於第二區域604以便說明。
更詳細說明，n型鰭式場效電晶體1202形成於第一區域602的鰭片1002。n型鰭式場效電晶體1202包含形成於鰭片1002的源極1206及汲極1208，以及閘極1212介於源極1206及汲極1208之間。類似地，p型鰭式場效電晶體1204形成於第二區域604的鰭片1004。p型鰭式場效電晶體1204包含形成於鰭片1004的源極1222及汲極1224，以及閘極1226介於源極1222及汲極1224之間。
特別地，每個鰭式場效電晶體(FinFET)的通道定義於對應的鰭片介於源極及汲極之間的部分，並且在閘極下面。在本實施例中，n型鰭式場效電晶體1202具有第一通道1232於鰭片1202中，而p型鰭式場效電晶體1204具有第二通道1234於鰭片1204中。對於n型鰭式場效電晶體1202而言，載子(電子)流從源極1206沿著方向1236通過通道1232至汲極1208，方向1236為晶體方向<100>。對於p型 鰭式場效電晶體1204而言，載子(電洞)流從源極1222沿著方向1238通過通道1234至汲極1224，方向1238為晶體方向<110>。藉由提供具有n型鰭式場效電晶體及p型鰭式場效電晶體的半導體結構200，且n型鰭式場效電晶體及p型鰭式場效電晶體具有對應的通道晶體方向，提升了載子移動率以及元件的效能。
下面更進一步描述鰭式場效電晶體(FinFET)的結構及形成。第一區域中602的閘極1212包含閘極介電特徵配置於通道上以及閘極電極配置於閘極介電特徵上。閘極更可以包含閘極間隔體配置於閘極電極的側壁上。閘極介電特徵包含閘極介電材料，例如氧化矽或合適的具有較高介電常數的介電材料(高k介電材料)。在本實施例中，閘極介電特徵包含多於一個介電材料層。舉例來說，閘極介電特徵包含介面介電層(interfacial dielectric layer)，例如氧化矽以及在介面介電層上的高k介電材料層。
閘極電極包含導電材料層，例如摻雜的多晶矽、金屬、金屬合金、金屬矽化物或其組合。在一些實施例中，閘極電極包含多於一個導電材料層。舉例來說，閘極電極包含具有合適功函數的第一導電層於閘極介電特徵上以及第二導電層於第一導電層上。在一個n型鰭式場效電晶體的示例中，第一導電層包含鈦或鈦鋁(titanium aluminum)。在另一個示例中，第二導電層包含鋁、鎢、銅、摻雜的多晶矽或其組合。
類似地，第二區域604的閘極1226亦包含閘極 介電層及閘極電極。第二區域604的閘極電極可以具有與第一區域602的閘極1212類似的結構。然而，導電材料可以不同。舉例來說，在第二區域604中，閘極電極包含第一導電材料層(例如氮化鉭或氮化鈦)以及第二導電材料層(例如鋁、鎢、銅、摻雜的多晶矽或其組合)。n型場效電晶體及p型場效電晶體的第一導電層設計為具有不同的功函數，以最佳化臨界電壓(threshold voltage)。
閘極(1212或1226)藉由包含各種沉積及圖案化的製程形成。根據一些實施例，將更詳細描述閘極的形成。在一個實施例中，介面層形成於半導體基材上(特別是通道上)。介面層可以包含使用合適的技術形成的氧化矽，例如原子層沉積(ALD)、熱氧化或紫外線-臭氧氧化(UV-Ozone Oxidation)。介面層可以具有小於10Å的厚度。高k介電材料層形成於介面層上。高k介電層包含具有介電常數高於熱氧化矽(約3.9)的介電材料。高k介電材料層藉由合適的製程形成，例如ALD或其他合適的技術。其他形成高k介電材料層的方法包含金屬有機CVD、PVD、紫外線-臭氧氧化或分子束磊晶(molecular beam epitaxy,MBE)。在一個實施例中，高k介電材料包含HfO2。或者，高k介電材料層包含金屬氮化物、金屬矽酸鹽或其他金屬氧化物。介面層及高k介電材料層構成閘極介電層。
在一些實施例中，閘極電極包含多晶矽。多晶矽層藉由諸如CVD的合適技術形成於閘極介電層上。在一個示例中，可以使用諸如PVD的合適技術進一步形成封蓋 層於高k介電材料層及多晶矽層之間。在一些示例中，封蓋層可以包含氮化鈦(TiN)、氮化鉭(TaN)或其組合。封蓋層可以具有一或多個功能，例如擴散阻障、蝕刻停止和/或保護。
在沉積之後，圖案化閘極材料層以形成閘極堆疊(或複數個閘極堆疊)。圖案化閘極堆疊包含微影製程及蝕刻。微影製程形成圖案化光阻層。在一個示例中，微影製程包含光阻塗布、軟烘烤、曝光、曝光後烘烤(PEB)、顯影及硬烘烤。隨後使用圖案化光阻層作為蝕刻遮罩藉由蝕刻來圖案化閘極推疊材料層。蝕刻製程可以包含一或多個蝕刻步驟。舉例來說，多個使用不同蝕刻劑的蝕刻步驟可以應用於蝕刻對應的閘極堆疊材料層。
在其他實施例中，閘極堆疊材料層的圖案化可以替代性的使用硬遮罩作為蝕刻遮罩。硬遮罩可以包含氮化矽、氮氧化矽、氧化矽、其他合適的材料或其組合。硬遮罩層沉積於閘極堆疊材料層上。圖案化光阻層藉由微影製程形成於硬遮罩層上。之後，通過圖案化光阻層的開口蝕刻硬遮罩層，因而形成圖案化硬遮罩層。圖案化光阻層可以在隨後使用合適的製程移除，例如濕式剝離(wet stripping)或電漿灰化(plasma ashing)。
閘極間隔體包含介電材料且可以具有一或多層。在一些實施例中，閘極間隔體包含氧化矽、氮化矽、氮氧化矽、其他合適的介電材料或其組合。閘極間隔體藉由沉積或非等向性蝕刻(例如乾蝕刻)形成。
在一些實施例中，源極及汲極特徵可以進一步包含藉由諸如離子植入的合適製程形成於鰭片特徵中的輕摻雜汲極(light-doped drain,LDD)特徵。輕摻雜汲極特徵具有與通道相反的摻雜類型。對於n型場效電晶體的示例來說，通道為p型，而輕摻雜汲極特徵為n型。在另一個p型場效電晶體的示例中，通道為n型，而輕摻雜汲極特徵為p型。輕摻雜汲極特徵及閘極堆疊可以在製程中一併形成。舉例來說，沉積閘極堆疊材料層並圖案化以形成閘極介電層及閘極電極層；藉由離子植入並使用虛設閘極堆疊(以及STI特徵)限制輕摻雜汲極特徵而形成輕摻雜汲極特徵；以及再形成閘極間隔體。在其他實施例中，輕摻雜汲極特徵為選擇性的，且可以從半導體結構200去除。
在一些替代的實施例中，閘極堆疊可以藉由閘極置換製程形成。閘極置換製程包含形成虛設閘極；形成源極及汲極特徵；移除虛設閘極；以及隨後形成包含具有高k介電材料的閘極介電層及金屬閘極電極的最終閘極。在各種實施例中，閘極置換製程可以為high-k-last製程，其移除虛設閘極的閘極介電層及閘極電極兩者並以最終閘極堆疊置換。
在一些替代性的實施例中，源極及汲極特徵具有不同半導體材料，使其具有應變效果，且可以藉由包含以下步驟的製程形成：蝕刻以使源極及汲極區域凹陷；以及使用不同的半導體(不同於通道材料)藉由磊晶成長填充凹陷。在一些實施例中，選擇半導體材料使通道區域具有適合 的應變效果，如此提升了對應的載子移動率。舉例來說，源極及汲極特徵的半導體材料包含碳化矽或矽鍺。
源極及汲極特徵可以藉由一或多個離子植入形成。以下描述使用NMOS電晶體作為示例，NMOS電晶體的源極及汲極特徵的形成是相似的。在一些實施例中，NMOS電晶體的源極及汲極特徵藉由包含形成輕摻雜汲極特徵的第一離子植入及形成源極/汲極特徵的第二離子植入的離子植入製程而形成。在其他實施例中，閘極堆疊的形成及源極及汲極特徵的形成整合在集合製程中。在進一步的實施例中，沉積並圖案化閘極堆疊；對鰭片主動區域執行第一離子植入以形成輕摻雜汲極特徵；閘極間隔體藉由合適的製程(例如介電沉積及乾蝕刻)形成於閘極堆疊的側壁上；以及對鰭片主動區域執行第二離子植入以形成源極/汲極特徵。
方法100在上述的操作之前、期間和/或之後進一步包含其他操作。舉例來說，方法100進一步包含形成層間介電層(interlayer dielectric material,ILD)於半導體結構200上的操作。層間介電層包含一或多種介電材料，例如氧化矽、低k介電材料或其組合。在一些實施例中，層間介電層的形成包含沉積及化學機械研磨(CMP)。
方法100包含形成多層互連結構以耦合各個元件而形成功能電路(functional circuit)的操作。多層互連結構包含垂直互連，例如通孔特徵或接觸特徵，以及水平互連，例如金屬線。這些互連特徵可以由各種導電材料形成，例如銅、鎢和/或矽化物。在一個示例中，使用鑲嵌和/或雙 鑲嵌製程用銅形成多層互連結構。
本揭露提供半導體結構及其製造方法。半導體結構包含n型鰭式場效電晶體的第一鰭式主動區域以及p型鰭式場效電晶體的第二鰭式主動區域。第一鰭式主動區域及第二鰭式主動區域具有不同晶體方向的通道，尤其，n型鰭式場效電晶體的通道沿著晶體方向<100>，而p型鰭式場效電晶體的通道沿著晶體方向<110>，以提升移動率及元件效能。方法包含以一個旋轉結合兩個半導體基材，達到上述的晶體方向。此外，p型鰭式場效電晶體的通道藉由使用矽鍺而具有應變，以提升移動率。
本揭露的實施例提供優於現有技術的優點，然而需要了解到，其他的實施例可以提供不同的優點，並不需要在此討論所有的優點，並且對於所有的實施例都不需要特定的優點。根據一些示例，藉由利用揭露的方法及結構，n型鰭式場效電晶體的電子移動率及p型鰭式場效電晶體的電子移動率如第13A圖及第13B圖提升。第13A圖繪示n型鰭式場效電晶體1202的實驗數據1302，其以電子移動率對對應的鰭片1202的寬度作圖。第13B圖繪示繪示p型鰭式場效電晶體1204的實驗數據1304，其以電洞移動率對對應的鰭片1204的寬度作圖。數據1306是來自具有沿<110>晶體方向的通道的n型鰭式場效電晶體的參考數據，而數據1308是不具有來自矽鍺的應變的p型鰭式場效電晶體的參考數據。從上述的實驗數據，顯示n型鰭式場效電晶體1202及p型鰭式場效電晶體1204的移動率皆提升。特別的是，可以 圖案化鰭片以在特徵之間產生相對緊密的間隔，上述的揭露十分適合用於此。另外，根據上述的揭露，可以處理用來形成鰭式場效電晶體鰭片的間隔(也被稱為心軸(mandrels))。相反的，現有的平面元件的方法及結構無法提供組合來最佳化並提升n型場效電晶體及p型場效電晶體。
因此，本揭露根據一些實施例提供半導體結構。半導體結構包含具有第一區域及第二區域的半導體基材；第一半導體材料的第一鰭片主動區域配置於第一區域，以第一方向定向，其中第一鰭片主動區域沿著第一方向具有<100>晶體方向；以及第二半導體材料的第二鰭片主動區域配置於第二區域並以第一方向定向，其中第二鰭片主動區域沿著第一方向具有<110>晶體方向。
本揭露亦根據一些實施例提供製作半導體結構的方法。方法包含結合第一半導體基材及第二半導體基材，以使對應的晶體定向<001>具有45度旋轉；形成圖案化遮罩於第二半導體基材上以覆蓋第一區域並暴露出第二區域；蝕刻第二區域的第二半導體基材以暴露出第一半導體基材；磊晶成長第二半導體材料於第二區域的第一半導體基材上；以及圖案化第二半導體基材及第二半導體材料以形成第一鰭片主動區域於第一區域及第二區域的第二鰭片主動區域中。第一鰭片主動區域以第一方向定向，且沿著第一方向具有晶體方向<100>。第二鰭片主動區域以第一方向定向，且沿著第一方向具有晶體方向<110>。
本揭露根據一些實施例提供半導體結構。半導體結構包含具有第一區域及第二區域的半導體基材；第一半導體材料的第一鰭片主動區域配置於第一區域，以第一方向定向，且藉由介電特徵與半導體基材隔離，其中第一鰭片主動區域沿著第一方向具有<100>晶體方向；第二半導體材料的第二鰭片主動區域配置於第二區域並以第一方向定向，其中第二鰭片主動區域沿著第一方向具有<110>晶體方向；n型鰭式場效電晶體形成於第一鰭片主動區域上；p型鰭式場效電晶體形成於第二鰭片主動區域上。
上文概述若干實施例或示例之特徵，使得熟習此項技術者可更好地理解本揭露之態樣。熟習此項技術者應瞭解，可輕易使用本揭露作為基礎來設計或修改其他製程及結構，以便實施本文所介紹之實施例的相同目的及/或實現相同優點。熟習此項技術者亦應認識到，此類等效結構並未脫離本揭露之精神及範疇，且可在不脫離本揭露之精神及範疇的情況下產生本文的各種變化、替代及更改。

Claims (20)

  1. 一種半導體結構，包含：一半導體基材，具有一第一區域及一第二區域；一第一半導體材料的一第一鰭片主動區域配置於該第一區域中，並以一第一方向定向，其中該第一鰭片主動區域沿著該第一方向具有一<100>晶體方向；以及一第二半導體材料的一第二鰭片主動區域配置於該第二區域中，並以該第一方向定向，其中該第二鰭片主動區域沿著該第一方向具有一<110>晶體方向。
  2. 如請求項1所述之半導體結構，更包含：一n型場效電晶體形成於該第一區域的該第一鰭片主動區域中；以及一p型場效電晶體形成於該第二區域的該第二鰭片主動區域中。
  3. 如請求項2所述之半導體結構，其中該第一半導體材料為矽，而該第二半導體材料為矽鍺。
  4. 如請求項3所述之半導體結構，其中該第二鰭片主動區域包含一矽層，該矽層具有與該介電特徵的一上表面共平面的一上表面。
  5. 如請求項1所述之半導體結構，更包含一介電材料層配置以隔離該第一鰭片主動區域與該半導體基 材，其中該介電特徵為氧化矽。
  6. 如請求項5所述之半導體結構，更包含一淺溝槽隔離特徵形成於半導體基材中，其中該淺溝槽隔離特徵具有一側壁，該側壁直接接觸該介電特徵的一側壁。
  7. 如請求項6所述之半導體結構，其中該淺溝槽隔離特徵具有與該介電特徵的一上表面共平面的一上表面，且該淺溝槽隔離特徵具有位於該介電特徵之一下表面之下的一下表面。
  8. 如請求項1所述之半導體結構，其中該第一鰭片主動區域及該第二鰭片主動區域是位於具有(100)晶體表面的一上表面的一晶體結構中。
  9. 如請求項1所述之半導體結構，其中該半導體基材為沿著該第一方向具有一<001>晶體方向的一矽基材。
  10. 如請求項1所述之半導體結構，其中該半導體基材為沿著該第一方向具有一<110>晶體方向的一矽基材。
  11. 一種方法，包含：結合一第一半導體基材及一第二半導體基材，使得對 應的<001>晶體方向具有一45度旋轉；形成一圖案化遮罩於該第二半導體基材上，以覆蓋一第一區域並暴露出一第二區域；蝕刻該第二區域的該第二半導體基材，以暴露出該第一半導體基材；磊晶成長一第二半導體材料於該第一區域的該第一半導體基材上；以及圖案化該第二半導體基材及該第二半導體材料，以形成一第一鰭片主動區域於該第一區域中及一第二鰭片主動區域於該第二區域中，其中該第一鰭片主動區域以一第一方向定向，並沿著該第一方向具有一<100>晶體方向，其中該第二鰭片主動區域以該第一方向定向，並沿著該第一方向具有一<110>晶體方向。
  12. 如請求項11所述之方法，其中該結合該第一半導體及該第二半導體包含藉由一矽氧化層結合該第一半導體及該第二半導體。
  13. 如請求項12所述之方法，其中該蝕刻該第二區域的該第二半導體基材包含進一步蝕刻穿過該矽氧化層直到暴露出該第二區域的該第一半導體基材。
  14. 如請求項13所述之方法，其中該蝕刻該第二區域的該第二半導體包含進一步凹陷該第二區域的該第一半導體基材。
  15. 如請求項11所述之方法，其中該第一半導體基材及該第二半導體基材為矽基材；以及該磊晶成長該半導體材料於該第二區域的該第一半導體基材包含磊晶成長矽鍺。
  16. 如請求項11所述之方法，更包含對該第二半導體基材執行一第一拋光製程，以形成一平坦化上表面。
  17. 如請求項11所述之方法，其中該圖案化該第二半導體基材及該半導體材料包含：形成複數個溝槽於該第二半導體基材及該半導體材料中；以一介電材料填充該些溝槽；執行一第二拋光製程；以及凹陷該介電材料以形成該第一鰭片主動區域及該第二鰭片主動區域。
  18. 如請求項11所述之方法，更包含形成具有負電導率的一第一場效電晶體於該第一區域的該第一鰭片主動區域及具有正電導率的一第二場效電晶體於該第二區域的該第二鰭片主動區域。
  19. 一種半導體結構，包含： 一半導體基材，具有一第一區域及一第二區域；一第一半導體材料的一第一鰭片主動區域配置於該第一區域，以一第一方向定向，並藉由一介電特徵與該半導體基材隔離，其中該第一鰭片主動區域沿著該第一方向具有一<100>晶體方向；一第二半導體材料的一第二鰭片主動區域配置於該第二區域，以該第一方向定向，其中該第二鰭片主動區域沿著該第一方向具有一<110>晶體方向；一n型鰭式場效電晶體形成於該第一鰭片主動區域上；以及一p型鰭式場效電晶體形成於該第二鰭片主動區域上。
  20. 如第19項所述之半導體結構，其中該第一半導體材料為矽，而該第二半導體材料為矽鍺。
TW106142600A 2017-06-29 2017-12-05 半導體結構及其製作方法 TWI672736B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201762526471P 2017-06-29 2017-06-29
US62/526,471 2017-06-29
US15/800,390 US10535680B2 (en) 2017-06-29 2017-11-01 Integrated circuit structure and method with hybrid orientation for FinFET
US15/800,390 2017-11-01

Publications (2)

Publication Number Publication Date
TW201905982A true TW201905982A (zh) 2019-02-01
TWI672736B TWI672736B (zh) 2019-09-21

Family

ID=64734450

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106142600A TWI672736B (zh) 2017-06-29 2017-12-05 半導體結構及其製作方法

Country Status (4)

Country Link
US (3) US10535680B2 (zh)
KR (1) KR102082445B1 (zh)
CN (1) CN109216428B (zh)
TW (1) TWI672736B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10680109B2 (en) * 2017-09-28 2020-06-09 Taiwan Semiconductor Manufacturing Co., Ltd. CMOS semiconductor device having fins and method of fabricating the same
US10840152B2 (en) 2018-09-27 2020-11-17 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US11594637B2 (en) * 2020-03-27 2023-02-28 Intel Corporation Gate-all-around integrated circuit structures having fin stack isolation
US11735669B2 (en) * 2020-07-30 2023-08-22 Taiwan Semiconductor Manufacturing Company, Ltd. Vertically-oriented complementary transistor
US11308257B1 (en) 2020-12-15 2022-04-19 International Business Machines Corporation Stacked via rivets in chip hotspots
US20230268382A1 (en) * 2022-02-22 2023-08-24 Intel Corporation Integrated circuit devices with angled transistors formed based on angled wafers

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070187682A1 (en) * 2003-08-28 2007-08-16 Nec Corporation Semiconductor device having fin-type effect transistor
JP2008227026A (ja) 2007-03-12 2008-09-25 Toshiba Corp 半導体装置の製造方法
EP2073267A1 (en) 2007-12-19 2009-06-24 INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM vzw (IMEC) Method of fabricating multi-gate semiconductor devices and devices obtained
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US8803316B2 (en) 2011-12-06 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. TSV structures and methods for forming the same
US8803292B2 (en) 2012-04-27 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate vias and methods for forming the same
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
CN103579234A (zh) * 2012-08-03 2014-02-12 中国科学院微电子研究所 一种半导体结构及其制造方法
US8802504B1 (en) 2013-03-14 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8993380B2 (en) 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
CN103824799B (zh) * 2014-03-05 2016-06-08 上海华虹宏力半导体制造有限公司 对准结构及晶圆
US9425126B2 (en) 2014-05-29 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structure for chip-on-wafer-on-substrate
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
US9431514B2 (en) * 2014-12-19 2016-08-30 Stmicroelectronics, Inc. FinFET device having a high germanium content fin structure and method of making same
US9728640B2 (en) * 2015-08-11 2017-08-08 International Business Machines Corporation Hybrid substrate engineering in CMOS finFET integration for mobility improvement
US9679763B1 (en) * 2015-11-20 2017-06-13 International Business Machines Corporation Silicon-on-insulator fin field-effect transistor device formed on a bulk substrate

Also Published As

Publication number Publication date
US20200152666A1 (en) 2020-05-14
US11031418B2 (en) 2021-06-08
US10535680B2 (en) 2020-01-14
US20190006391A1 (en) 2019-01-03
US11735594B2 (en) 2023-08-22
TWI672736B (zh) 2019-09-21
KR20190002273A (ko) 2019-01-08
CN109216428B (zh) 2023-01-06
CN109216428A (zh) 2019-01-15
US20210296485A1 (en) 2021-09-23
KR102082445B1 (ko) 2020-02-28

Similar Documents

Publication Publication Date Title
US11749720B2 (en) Integrated circuit structure and method with solid phase diffusion
US11682697B2 (en) Fin recess last process for FinFET fabrication
TWI702657B (zh) 鰭狀場效電晶體裝置與其形成方法
TWI672736B (zh) 半導體結構及其製作方法
TWI570785B (zh) 半導體裝置與其形成方法及鰭狀場效電晶體裝置
US8686516B2 (en) Silicide formation and associated devices
KR101688699B1 (ko) FinFET 소자의 구조 및 그 형성 방법
US9337195B2 (en) Semiconductor devices and methods of manufacture thereof
CN105742343A (zh) 用于3d finfet金属栅极的结构和方法
CN104733321B (zh) 制造FinFET器件的方法
US10522633B2 (en) Methods and structures of novel contact feature
US20160351458A1 (en) Ion implantation methods and structures thereof
TW202213789A (zh) 半導體結構之製造方法
US20230411399A1 (en) Integrated Circuit Structure and Method with Hybrid Orientation for FinFET
TWI807762B (zh) 半導體裝置的製作方法
TWI783302B (zh) 半導體裝置及其形成方法