CN105742343A - 用于3d finfet金属栅极的结构和方法 - Google Patents
用于3d finfet金属栅极的结构和方法 Download PDFInfo
- Publication number
- CN105742343A CN105742343A CN201510777147.6A CN201510777147A CN105742343A CN 105742343 A CN105742343 A CN 105742343A CN 201510777147 A CN201510777147 A CN 201510777147A CN 105742343 A CN105742343 A CN 105742343A
- Authority
- CN
- China
- Prior art keywords
- layer
- gate
- gate stack
- semiconductor structure
- dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 100
- 239000002184 metal Substances 0.000 title claims abstract description 100
- 238000000034 method Methods 0.000 title claims description 95
- 239000004065 semiconductor Substances 0.000 claims abstract description 121
- 239000000758 substrate Substances 0.000 claims abstract description 76
- 239000003989 dielectric material Substances 0.000 claims abstract description 56
- 239000010410 layer Substances 0.000 claims description 230
- 239000000463 material Substances 0.000 claims description 45
- 230000004888 barrier function Effects 0.000 claims description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 17
- 239000000945 filler Substances 0.000 claims description 14
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 11
- 239000011229 interlayer Substances 0.000 claims description 9
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 9
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 7
- 229910052721 tungsten Inorganic materials 0.000 claims description 7
- 239000010937 tungsten Substances 0.000 claims description 7
- 239000000203 mixture Substances 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 230000008569 process Effects 0.000 description 19
- 238000000151 deposition Methods 0.000 description 18
- 230000006870 function Effects 0.000 description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 16
- 238000005530 etching Methods 0.000 description 16
- 238000000059 patterning Methods 0.000 description 16
- 229910052710 silicon Inorganic materials 0.000 description 16
- 239000010703 silicon Substances 0.000 description 16
- 230000015572 biosynthetic process Effects 0.000 description 13
- 238000005516 engineering process Methods 0.000 description 13
- 238000005498 polishing Methods 0.000 description 13
- 239000002002 slurry Substances 0.000 description 13
- 230000008021 deposition Effects 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 10
- 239000002019 doping agent Substances 0.000 description 9
- 230000005669 field effect Effects 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- 239000000126 substance Substances 0.000 description 8
- 229910044991 metal oxide Inorganic materials 0.000 description 7
- 150000004706 metal oxides Chemical class 0.000 description 7
- 230000002085 persistent effect Effects 0.000 description 7
- 238000005240 physical vapour deposition Methods 0.000 description 7
- 125000006850 spacer group Chemical group 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910010037 TiAlN Inorganic materials 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 229910015844 BCl3 Inorganic materials 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 239000013110 organic ligand Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 101100373011 Drosophila melanogaster wapl gene Proteins 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000007687 exposure technique Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 210000004483 pasc Anatomy 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7856—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Materials Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
根据一些实施例本发明提供了一种半导体结构。半导体结构包括半导体衬底;以及设置在半导体衬底上的栅极堆叠件;其中,栅极堆叠件包括高k介电材料层以及设置在高k介电材料层上的各个金属层,其中,栅极堆叠件具有凸顶面。本发明实施例涉及用于3D FINFET金属栅极的结构和方法。
Description
技术领域
本发明实施例涉及用于3DFINFET金属栅极的结构和方法
背景技术
本申请要求2014年12月30日提交的标题为“STRUCTUREANDMETHODFOR3DFINFETMETALGATE”的美国临时申请第62/098,005号的优先权,其全部内容结合于此作为参考。
在集成电路工业的先进的工艺节点中,采用高k介电材料和金属以形成诸如金属-氧化物-半导体场效应晶体管(MOSFET)的场效应晶体管(FET)的栅极堆叠件。在现有的形成金属栅极堆叠件的方法中,在去除伪栅极的栅极替代工艺中形成金属栅极,以及用栅极材料填充栅极沟槽。由于高封装密度和小部件尺寸,实现适当的空隙填充和轮廓控制,尤其是用于具有3D结构的FET(诸如鳍式场效应晶体管(FINFET))的适当的空隙填充和轮廓控制是一个挑战。因此,需要金属栅极堆叠件的结构及其形成方法以解决上述确定的问题。
发明内容
根据本发明的一个实施例,提供了一种半导体结构,包括:半导体衬底;以及栅极堆叠件,设置在所述半导体衬底上,其中,所述栅极堆叠件包括高k介电材料层以及设置在所述高k介电材料层上的各个金属层,其中,所述栅极堆叠件具有凸顶面。
根据本发明的另一实施例,还提供了一种半导体结构,包括:半导体衬底;以及设置在所述半导体衬底上的栅极堆叠件;其中,所述栅极堆叠件包括:栅极介电层,所述栅极介电层包括高k介电材料;设置在所述高k介电材料层上的覆盖层;设置在所述覆盖层上方的功函金属层;设置在所述功函金属层上的阻挡层;以及设置在所述阻挡层上的填充金属层,其中,所述栅极堆叠件具有凸顶面。
根据本发明的又另一实施例,还提供了一种形成半导体结构的方法,包括:在半导体衬底上形成伪栅极;在所述衬底上形成层间介电层;去除所述伪栅极,在所述层间介电层中产生栅极沟槽;形成各个栅极材料层以填充在所述栅极沟槽中,其中,所述栅极材料层包括栅极介电层、位于所述覆盖层上的各个金属层;以及实施选择性去除工艺,由此形成具有凸顶面的栅极堆叠件。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳地理解本发明的各个方面。应该注意,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各种部件的尺寸可以被任意增大或减小。
图1是根据一些实施例构建的用于制造具有金属栅极堆叠件的半导体结构的方法的流程图。
图2和图4至图10是根据一些实施例构建的在各个制造阶段的半导体结构的截面图。
图3B和图13B是根据一些实施例构建的在各个制造阶段的半导体结构的顶视图。
图3A和图3C是根据一些实施例构建的图3B中的半导体结构的截面图。
图13A和图13C是根据一些实施例构建的图13B中的半导体结构的截面图。
图11和图12根据一些实施例构建的图10中的半导体结构的栅极堆叠件的截面图。
具体实施方式
应当理解,以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。此外,本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。此外,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。
图1是根据本发明的各个方面构建的制造具有栅极堆叠件的半导体器件的方法100的一个实施例的流程图。图2和图3至图10是根据一些实施例的在各个制造阶段的半导体结构200的截面图。图11和图12是根据一些实施例的在半导体结构200中的栅极堆叠件的截面图。图3A和图3C以及图13A和图13C示出了根据一些其他实施例构建的具有鳍结构的半导体结构217。参照图1至图13共同描述半导体结构200(或217)及其制造方法100。
方法100始于102,提供半导体衬底210。半导体衬底210包括硅。可选地,衬底210包括锗或硅锗。在其他实施例中,半导体210可以使用另一半导体材料,诸如金刚石、碳化硅、砷化镓、GaAsP、AlInAs、AlGaAs、GaInP或它们的其他适合的组合。
半导体衬底也包括各个掺杂区,诸如通过诸如离子注入的适合的技术形成的n-阱和p-阱。半导体衬底210也包括各个隔离部件,诸如形成在衬底中以限定有源区214和将有源区上的各个器件分开的浅沟槽隔离(STI)部件212。STI的形成可以包括在衬底中蚀刻沟槽以及通过诸如氧化硅、氮化硅或氮氧化硅的绝缘材料填充沟槽。填充的沟槽可以具有多层结构,诸如热氧化物衬垫层,以及填充沟槽的氮化硅。在一个实施例中,可以使用以下工艺顺序来生成STI结构:生长焊盘氧化物,形成低压化学汽相沉积(LPCVD)氮化物层,使用光刻胶并且掩蔽来图案化STI开口,在衬底中蚀刻沟槽,可选择地生长热氧化物沟槽衬垫层以改进沟槽界面,用CVD氧化物填充沟槽,以及使用化学机械抛光(CMP)来抛光和平坦化。
在一些实施例中,半导体衬底210的顶面和STI部件212的顶面基本上是共平面的,产生共同的顶面。这被称为平面结构。在其他实施例中,半导体衬底210的顶面和STI部件212的顶面不是共平面的,产生三维结构,诸如如截面图图3A中示出的半导体结构217中的鳍结构216。在半导体结构217中,有源区214在STI部件212的顶面之上延伸,以及因此被称为鳍结构或鳍有源结构。因此在鳍结构216上形成各个器件。具体地,在鳍结构216上形成场效应晶体管(FET),以及相应的FET的栅极从鳍结构的多个表面(顶面和侧面)与沟道连接,因此增强器件性能。因此,形成在鳍结构216上的FET被称为FinFET。
参照图3B和图3C进一步描述半导体结构217。图3B示出了顶视图中的半导体结构217,以及图3C示出了根据一些实施例构建的沿着图3B中的虚线BB’的截面图中的半导体结构217。因此,图3A中的半导体结构217是沿着图3B中的虚线AA’的截面图。
参照图3B,半导体结构217包括限定有源区214的鳍结构216。隔离部件212形成在衬底210上并且限定鳍结构216。有源区214限定在鳍结构216中。鳍结构216包括一个或多个定位在第一方向上的指状部件。将在后面描述的栅极220形成在鳍结构216上方并且定位在不同于第一方向的第二方向上。在具体实施例中,第一和第二方向是彼此正交的。
参照图3C,半导体结构217包括限定有源区的鳍结构216。隔离部件212形成在衬底210上并且限定鳍结构216。鳍结构216在隔离部件212的顶面之上延伸。
公开的半导体结构(200或217)及其制造方法100提供对集成电路的改进,尤其是对FinFET的改进。可以通过各个技术来形成鳍结构216。在一些实施例中,通过使STI部件212凹进(诸如通过选择性蚀刻)来形成鳍结构216。在一些其他实施例中,通过选择性外延生长(SEG)来形成鳍结构216。在SEG工艺中,利用与衬底210的材料相同的材料(诸如硅)或不同的材料(诸如硅锗或碳化硅)来形成鳍结构216以进一步实现其他功能(例如,应变的效应)。方法100适用于平面半导体结构200和非平面半导体结构217。为了简化,以下大部分附图仍然使用平面器件以描述方法100。
返回参照图2(以及3A、3B和图3C),可以在一个或多个有源区214中形成掺杂阱218。在一些实施例中,有源区214设计为形成FET,诸如p型FET(pFET)或n型FET(nFET)。在一些实例中,pFET将形成在有源区214上,以及掺杂阱218包括n型掺杂剂,诸如磷(P)。在一些实施例中,nFET将形成在有源区214上,以及掺杂阱218包括分布在有源区中的p型掺杂剂,诸如硼(B)。可以通过诸如一个或多个离子注入的合适的掺杂工艺通过掩模层的开口将掺杂剂引入掺杂阱218。STI部件212的进一步功能是将掺杂剂限定于期望的有源区。在一些实施例中,nFET和pFET均形成在衬底210中,诸如在互补金属氧化物半导体(CMOS)电路中。
仍参照图2,方法100进行至操作104,在半导体衬底210上形成一个或多个伪栅极堆叠件220。栅极堆叠件220包括栅极介电层222和栅极导电层224。栅极堆叠件220的形成包括沉积和图案化。图案化还包括光刻工艺和蚀刻。硬掩模层可以进一步用于图案化栅极堆叠件220。
在一些实施例中,如图2的左边更详细示出的,栅极介电层222包括形成在半导体衬底210上的高k介电材料层222A。可以在栅极介电层222上形成覆盖层226。在覆盖层226上形成作为栅极导电层的多晶硅层。栅极介电层222还可以包括插入在半导体衬底210和高k介电材料层222A之间的界面层(IL)222B。
在进一步的实施例中,在形成高k介电材料层222A之前在衬底210上形成界面层222B。界面层222B可以包括通过诸如原子层沉积(ALD)、热氧化或UV-臭氧氧化的适合的技术来形成的氧化硅。界面层可以具有小于10埃的厚度。
高k介电材料层222A包括介电常数高于热氧化硅的介电常数(约3.9)的介电材料。通过诸如ALD的合适的工艺来形成高k介电材料层222A。形成高k介电材料层的其他方法包括金属有机化学汽相沉积(MOCVD)、物理汽相沉积(PVD)、UV-臭氧氧化或分子束外延(MBE)。在一个实施例中,高k介电材料包括HfO2。可选地,高k介电材料层222A包括金属氮化物、金属硅化物或其他金属氧化物。
在高k介电材料层222A上形成覆盖层226。在一个实施例中,覆盖层226包括氮化钛(TiN)。在另一实例中,氮化钛层的厚度在约5埃和约20埃之间的范围内。覆盖层226可以可选地或额外的包括其他合适的材料。通过诸如PVD的适合的技术形成覆盖层226。
在覆盖层226上形成多晶硅层224。通过诸如CVD的适合的技术形成多晶硅层224。在一个实例中,多晶硅层224是未掺杂的。在另一实例中,多晶硅层224的厚度在约500埃和约1000埃之间的范围内。
图案化的掩模可以进一步形成在多重栅极材料层上并且用作掩模以形成栅极堆叠件220。在多晶硅层224上形成图案化的掩模。图案化的掩模限定各个栅极区和各个开口,各个开口暴露将被去除的栅极堆叠件材料层。图案化的掩模包括诸如氮化硅和/或氧化硅的硬掩模或可选地包括光刻胶。在一个实施例中,图案化的掩模层包括具有氮化硅和氧化硅的图案化的硬掩模层。作为一个实例,通过低压化学汽相沉积(LPCVD)工艺来在多晶硅层上沉积氮化硅层。使用光刻工艺进一步图案化氮化硅和氧化硅层以形成图案化的光刻胶层以及使用蚀刻工艺以蚀刻位于图案化的光刻胶层的开口内的氮化硅和氧化硅。可选地,其他介电材料可以用作图案化的硬掩模。例如,氮氧化硅可以用作硬掩模。在另一实施例中,图案化的硬掩模包括通过光刻工艺形成的图案化的光刻胶层。示例性图案化工艺可以包括光刻胶涂覆、软烘烤、掩模对准、曝光、后曝光烘烤、显影光刻胶以及硬烘烤的工艺步骤。也可以通过诸如无掩蔽光刻、电子束写入、离子束写入和分子印记的其他适合的方法来实施或替代光刻曝光工艺。
方法包括图案化栅极材料层。通过图案化的掩模的开口对栅极材料应用一个或多个蚀刻工艺。蚀刻工艺可以包括干蚀刻、湿蚀刻或它们的组合。在其他实例中,蚀刻工艺可以包括有效地蚀刻各个栅极材料层的多重步骤。
在一些其他实施例中,诸如在后高k工艺中,在伪栅极堆叠件220中不形成高k介电层。在这种情况下,栅极介电层222包括氧化硅以及栅极导电层224包括多晶硅。沉积和图案化工艺类似于以上所所描述的那些沉积和图案化工艺。
类似地,在图3A至图3C中的半导体结构217的鳍结构216上形成栅极堆叠件220。具体地,如图3C所示,栅极堆叠件220沉积在鳍结构216上方并且延伸至隔离部件212。由于鳍结构216的顶面和隔离部件212的顶面是不共平面的,因此栅极堆叠件220的沉积在鳍结构216上的部分和栅极堆叠件220的沉积在隔离部件212上的部分具有在不同的水平面处的各自的底面(或换句话说,是不共平面的)。
参照图4,方法100包括操作106以在衬底210中形成源极和漏极230。在操作106中,可以在栅极堆叠件220的侧壁上形成栅极间隔件234。源极和漏极(S/D)230形成在衬底210上并且被栅极堆叠件220插入在源极和漏极(S/D)230之间。
在又另一实施例中,半导体结构200还可以包括在衬底210上形成的具有相同类型导电性和较低掺杂浓度的轻掺杂漏极(LDD)部件232。分别通过离子注入形成LDD部件232和S/D230。随后实施一个或多个热退火工艺以激活掺杂的物种。
栅极间隔件234包括一个或多个介电材料,诸如氧化硅、氮化硅、氮氧化硅或它们的组合。在一个实施例中,栅极间隔件234包括设置在栅极堆叠件的侧壁上的密封间隔件以及设置在密封间隔件上的主间隔件,通过包括沉积和蚀刻的工序来分别形成密封间隔件和主间隔件。
在一些实例中,源极和漏极230包括通过合适的技术(诸如离子注入)引入至半导体衬底210的掺杂的掺杂物种。在一个实施例中,栅极堆叠件220配置在有源区中以用于n型场效应晶体管(nFET),源极和漏极的掺杂剂是诸如磷或砷的n型掺杂剂。在另一实施例中,栅极堆叠件配置在有源区中以用于p型场效应晶体管(pFET),源极和漏极的掺杂剂是诸如硼或镓的p型掺杂剂。在又另一实施例中,源极和漏极230包括轻掺杂漏极(LDD)部件和重掺杂源极漏极(S/D)部件,轻掺杂漏极(LDD)部件和重掺杂源极漏极(S/D)部件共同被称为源极和漏极。分别通过离子注入形成LDD部件和S/D部件。随后实施一个或多个热退火工艺以激活掺杂的物种。
在一些实例中,通过外延生长来形成源极和漏极230以增强器件性能,诸如以用于增强迁移率的应变效应。在进一步的实施例中,如图5所示,源极和漏极230的形成包括选择性地蚀刻衬底210以形成凹槽236;以及在凹槽236中外延生长半导体材料以生成源极和漏极230(诸如图4中示出的那些)。可以使用湿和/或干蚀刻工艺以选择性地蚀刻衬底210的材料来形成凹槽236。在进一步的实施例中,栅极堆叠件220、栅极间隔件234和STI部件212共同地用作蚀刻硬掩模,由此在源极和漏极区中形成凹槽236。在一些实例中,使用诸如四氟化碳(CF4)、四甲基氢氧化铵(THMA)、其他合适的蚀刻剂或它们的组合的蚀刻剂以形成凹槽236。
此后,通过外延生长晶体结构的源极和漏极(S/D)部件230用半导体材料填充沟槽236。外延生长可以包括原位掺杂以形成具有适合的掺杂剂的S/D。在一些实施例中,外延生长是选择性沉积工艺,选择性沉积工艺包括在外延生长期间的蚀刻,从而使得半导体材料基本生长在凹槽236中的半导体表面上。具体地,选择性沉积工艺包括用于蚀刻效果的氯并且使得沉积具有选择性。设计和调整选择性沉积工艺以外延地生长使得在凹槽236中形成的S/D230包括晶体结构的半导体材料。半导体材料不同于衬底210的半导体材料。例如,半导体材料包括碳化硅或硅锗,而衬底210是硅衬底。在一些实施例中,选择半导体材料以用于沟道区中的适合的应变效应使得增强相应的载流子迁移率。在一个实例中,有源区214是用于pFET,半导体材料是掺杂有硼的硅锗以用于S/D230,而衬底210是硅衬底。在另一实例中,有源区214是用于nFET,半导体材料是掺杂有磷的碳化硅以用于S/D230,而衬底210是硅衬底。
在又另一实施例中,可以在源极和漏极区上进一步形成硅化物部件以降低接触电阻。可以通过被称为自对准硅化(自对准多晶硅化salicide)的技术来形成硅化物部件,自对准硅化包括至硅衬底上的金属沉积(诸如镍沉积)、使金属与硅反应以形成硅化物的热退火,以及去除未反应的金属的蚀刻。
参照图6,方法100进行至操作108,在衬底以及栅极堆叠件220上形成层间介电层(ILD)240。通过诸如CVD的适合的技术沉积ILD240。ILD240包括诸如氧化硅、低k介电材料或它们组合的介电材料。然后,此后可以应用化学机械抛光(CMP)工艺以平坦化ILD240的顶面。在一个实例中,通过CMP工艺暴露栅极堆叠件以用于随后的工艺步骤。在其中在先前操作中不去除用以图案化栅极堆叠件220的硬掩模的另一实例中,CMP也去除硬掩模。可选地,CMP停止在硬掩模上以及此后通过蚀刻工艺去除硬掩模。
参照图7,方法100进行至操作110,部分地或完全地去除栅极堆叠件220,生成沟槽242。操作110包括一个或多个蚀刻步骤以通过诸如一个或多个湿蚀刻、干蚀刻或它们的组合的合适的蚀刻工艺选择性地去除栅极导电层224或可选地栅极堆叠件220。
参照图8,方法100进行至操作112,在栅极沟槽242中填充各个栅极材料层,在栅极沟槽242中形成金属栅极250。在诸如后高k工艺中的一些实施例中,栅极材料层包括栅极介电层254和栅极导电层(或栅电极)256。栅极介电层254包括高k介电材料。栅极导电层256包括金属。在一些实施例中,栅极导电层256包括多层,诸如覆盖层、功函金属层、阻挡层和填充金属层(诸如铝或钨)。栅极材料层还可以包括插入在衬底210和高k介电材料之间的诸如氧化硅的界面层252。界面层252是栅极介电层的部分。通过诸如CVD、PVD、镀、ALD或其他合适的技术的沉积在栅极沟槽242中填充各个栅极材料层。
高k介电层252包括介电常数高于热氧化硅的介电常数(约3.9)的介电材料。通过诸如ALD的合适的工艺来形成高k介电材料层252。形成高k介电材料层的其他方法包括金属有机化学汽相沉积(MOCVD)、PVD、UV-臭氧氧化或MBE。在一个实施例中,高k介电材料包括HfO2。可选地,高k介电材料层252包括金属氮化物、金属硅化物或其他金属氧化物。
在图11的截面图中示出的一个实施例中,栅电极256包括覆盖层256A、阻挡层256B、功函金属层256C,另一阻挡层256D和填充金属层256E。在进一步的实施例中,覆盖层256A包括通过诸如ALD的合适的工艺来形成的氮化钛、氮化钽或其他合适的材料。阻挡层256B包括通过诸如ALD的适合的沉积技术形成的氮化钛、氮化钽或其他合适的金属。
功函金属层256C包括具有合适的功函的金属或金属合金的导电层。使得增强相应的FET以用于其器件性能。功函(WF)金属层256C对于pFET和nFET是不同的,分别被称为n型WF金属和p型WF金属。WF金属的选择取决于将要在有源区214上形成的FET。例如,半导体衬底200包括用于nFET的第一有源区214和用于nFET的另一有源区,以及因此在相应的栅极堆叠件中分别形成n型WF金属和p型WF金属。具体地,n型WF金属是具有第一功函的金属使得降低相关的nFET的阀值电压。n型WF金属接近于硅导带能量(Ec)或更低的功函,呈现更容易的电子逃逸。例如,n型WF金属具有约4.2eV或更小的功函。p型WF金属是具有第二功函的金属使得降低相关的pFET的阀值电压。p型WF金属接近于硅价带能量(Ev)或更高的功函,呈现至核子的更强的电子结合能。例如,p型功函金属具有约5.2eV或更高的WF。
在一些实施例,n型WF金属包括钽(Ta)。在其他实施例中,n型WF金属包括钛铝(TiAl)、氮化钛铝(TiAlN)或它们的组合。在其他实施例中,n-金属包括Ta、TiAl、TiAlN、氮化钨(WN)或它们的组合。n型WF金属可以包括如堆叠件的各个金属基薄膜以用于最优化的器件性能和工艺兼容性。在一些实施例中,p型WF金属包括氮化钛(TiN)或氮化钽(TaN)。在其他实施例中,p型WF金属包括TiN、TaN、氮化钨(WN)、钛铝(TiAl)或它们的组合。p型WF金属可以包括如堆叠件的各个金属基薄膜以用于最优化的器件性能和工艺兼容性。通过诸如PVD的合适的技术沉积功函金属。
阻挡层256D包括通过诸如ALD的合适的沉积技术形成的氮化钛、氮化钽或其他合适的材料。在各个实施例中,填充金属层256E包括铝、钨或其他合适的金属。通过诸如PVD或镀的合适的技术来沉积填充金属层256E。
参照图9,方法100进行至操作114,形成具有凸顶面的金属栅极250。在操作112之后,栅极材料层基本上填充在栅极沟槽242中以及也可以沉积在ILD层240上。操作114去除沉积在ILD层240上的栅极材料以及操作114设计为形成金属栅极250的凸顶面。这可通过选择性去除工艺来实现,选择性去除工艺具有各个栅极材料的不同的去除速率。具体地,选择性去除工艺对边缘栅极材料层(诸如高k介电材料和覆盖层)具有较高的去除速率以及对中心栅极材料层(诸如填充金属层)具有较低的去除速率。具体地,择性去除工艺具有选择性去除速率使得去除速率从边缘金属层到中心金属层降低。
在一些实施例中,选择性去除工艺是选择性CMP工艺。应用CMP工艺以去除过量的栅极材料,诸如沉积在ILD层240上的金属。选择性CMP工艺设计为具有选择性去除速率以形成凸顶面。在一些实例中,用于选择性CMP工艺的浆体设计为包括合适的化学物质以实现这样的抛光选择性。在一些其他实例中,用于选择性CMP工艺中的浆体设计为包括具有蚀刻选择性的化学物质、具有适合的尺寸的研磨微粒、适合的抛光压力、用于抛光选择性的多重抛光步骤或它们的组合。
在一些实施例中,选择性CMP工艺包括第一CMP步骤和第二CMP步骤。第一CMP步骤包括第一浆体、第一压力和第一抛光持续时间。第二CMP步骤包括第二浆体、第二压力和第二抛光持续时间。第二浆体、第二压力和第二抛光持续时间分别不同于第一浆体、第一压力和第一抛光持续时间,或它们(浆体、压力和抛光持续时间)中的一个是不同的。两个CMP步骤设计为具有抛光选择性使得去除边缘栅极材料多于去除中心栅极材料。在一个实例中,具有第一浆体和第一压力的第一CMP步骤设计为相对于中心栅极材料基本上去除边缘栅极材料;而具有第二浆体和第二压力的第二CMP步骤设计为相对于边缘栅极材料基本上去除中心栅极材料。第一CMP步骤中的第一抛光持续时间大于第二CMP步骤中的第二抛光持续时间。由此,去除更多的边缘栅极材料以及形成栅极250的凸顶面。在进一步的实施例中,第一浆体和第二浆体在蚀刻化学物质和相应浆体中的研磨微粒方面彼此不同。
在一些实施例中,选择性去除工艺是选择性蚀刻工艺。应用选择性蚀刻工艺以去除过量的栅极材料,诸如沉积在ILD层240上的金属。选择性蚀刻工艺设计为具有选择性去除速率以形成凸顶面。在一些实例中,选择用于选择性蚀刻工艺的蚀刻剂以具有这样的蚀刻选择性。在一些其他实例中,蚀刻剂包括F2、Cl2、BCl3或它们的混合。在一些其他实施例中,选择性蚀刻工艺包括第一蚀刻步骤和第二蚀刻步骤。第一蚀刻步骤包括设计为选择性地蚀刻边缘栅极材料的第一蚀刻剂;而第二蚀刻步骤包括第二蚀刻剂。第二蚀刻剂不同于第一蚀刻剂并且设计为选择性地蚀刻中心栅极材料。例如,第一蚀刻剂包括氟化氢(HF)溶液以选择性地去除栅极介电材料而第二蚀刻剂包括H3PO4、HNO3、HCl或它们的组合。在进一步的实例中,HF溶液使用无水溶剂以减小ILD层240的去除。诸如通过控制蚀刻时间来控制第一蚀刻步骤和第二蚀刻步骤,以形成栅极250的凸顶面。
在一些其他实施例中,选择性去除工艺包括CMP和蚀刻的组合,最优化蚀刻以形成凸顶面。例如,去除工艺包括CMP工艺和此后的选择性蚀刻工艺。CMP工艺基本上去除了ILD层之上的过量的栅极材料。选择性蚀刻工艺(诸如HF溶液)设计为选择性地去除栅极介电材料。
因此,形成的栅极堆叠件250具有凸顶面。栅极堆叠件250从中心到边缘的高度差是H以及栅极宽度是W。在一些实例中,高度差H在从约2nm至约10nm的范围内。在一些实施例中,比率H/W的范围是从约10%至约50%。
参照图1和图10,方法100包括其他制造操作116。在本实施例中,操作116包括在衬底210上形成覆盖层260的工序。在一个实例中,覆盖层260的形成包括沉积和抛光。在进一步的实例中,通过诸如CVD的适合的技术在衬底上沉积介电材料的覆盖层260。覆盖层260的介电材料包括诸如氧化硅、氮化硅、低k介电材料或其他合适的介电材料的适合的材料。抛光工艺可以是CMP工艺。在CMP工艺之后,平坦化半导体衬底200的顶面。具体地,如图12所示,覆盖层设置在边缘区中的栅极堆叠件250的顶面上,由此对栅极堆叠件250提供保护使栅极堆叠件250免受在随后的制造工艺期间的化学损坏或其他损坏,诸如从侧壁的化学侵蚀。覆盖层260用作阻挡层。例如,在后面的形成接触件的操作中,进行化学蚀刻(chemicaletchingisevolved)以开放(open)随后形成的ILD层。蚀刻化学物质可以进一步从侧壁蚀刻至栅极堆叠件250并且因此损坏栅极堆叠件250。在保护覆盖层260的情况下,保护栅极堆叠件250以及由此使栅极堆叠件250免受损坏。
类似地,在操作116之后,图13A至图13C中示出了通过方法100制造的半导体结构217,以及图13B是半导体结构217的顶视图。图13A和图13C是分别沿着图13B中的虚线AA’和BB’的半导体结构217的截面图。具体地,凸栅极250设置在鳍结构216和隔离部件212上。栅极250的位于鳍结构216上的第一部分和栅极250的位于隔离部件212上的第二部分具有各自的在不同水平处(换句话说,不公平面的)的底面。栅极250的顶面是不平坦的但是具有凸形形状使得覆盖层260能够形成在栅极250的边缘上。
随后可以是其他工艺步骤以形成功能电路。例如,互连结构形成在衬底上并且设计为连接各个晶体管和其他器件以形成功能电路。互连部件包括各个导电部件,诸如用于水平连接的金属线和用于垂直连接的接触件/通孔。各个互连部件可以采用包括铜、钨和硅的各个导电材料。在一个实例中,镶嵌工艺用于形成基于铜的多层互连结构。在另一实施例中,钨用于在接触孔中形成钨插塞。
即使在附图中仅示出了一个栅极堆叠件250,然而,在衬底210上形成具有凸顶面的多个栅极堆叠件,以及在衬底210上形成各个相应的nFET、pFET和其他电路器件。在一些实施例中,在3D鳍有源区上形成栅极堆叠件250以及栅极堆叠件250是FinFET的部分。
本发明不限于其中半导体结构包括场效应晶体管(诸如金属氧化物硅(MOS)晶体管)的应用,以及本发明可以延伸至具有金属栅极堆叠件的其他集成电路中。例如,半导体结构200可以包括动态随机存取存储(DRAM)单元、单电子晶体管(SET)和/或其他微电子器件(本文中共同地称为微电子器件)。在另一实施例中,半导体结构200包括FinFET晶体管。当然,本发明的各个方面也可应用于和/或容易地适用于其他类型的晶体管,以及可以在不同的应用中(包括传感器单元、存储单元、逻辑单元以及其他)采用本发明的各个方面。
尽管已经详细地描述了本发明的实施例,本领域中的技术人员可以理解,在不背离本发明的精神和范围的情况下,在此他们可以做出多种变化、替换以及改变。在一个实施例中,栅电极可以可选地或额外地包括其他合适的金属。基脚工序(footingprocedure)可以执行其他有效的清洗工序。公开的方法用于,但不限于,形成诸如n型金属-氧化物-半导体场效应晶体管(nMOSFET)的一个晶体管。例如,可以在相同的衬底上形成多个nMOSFET和多个p型金属-氧化物-半导体场效应晶体管(pMOSFET),在共同的工序(其中分别形成一些部件)中形成nMOSFET和pMOSFET。在特定实例中,在nMOSFET区中形成n型WF金属,而n金属的沉积覆盖pMOSFET区。
在另一实施例中,半导体衬底可以包括外延层。例如,衬底可以具有位于块状半导体上面的外延层。此外,衬底可以包括绝缘体上半导体(SOI)衬底,诸如掩埋介电层。可选地,衬底可以包括诸如埋氧层(BOX)的掩埋介电层,诸如通过被称为注氧分离(SIMOX)技术、晶圆接合、选择性外延生长(SEG)的方法或其他适合的方法形成的埋氧层。
本发明提供了半导体结构及其制造方法。半导体结构包括具有凸顶面的栅极堆叠件。此外,可以在栅极堆叠件的凸顶面的边缘区上形成覆盖层。覆盖层用作阻挡层以在随后的制造工艺期间保护栅极堆叠件免受诸如化学损坏的各种损坏。凸栅极堆叠件的形成包括选择性去除工艺,诸如选择性CMP或选择性蚀刻工艺,选择性蚀刻工艺设计为对不同的金属层具有不同的蚀刻速率,尤其是对边缘金属层具有较高的去除速率以及对中心金属层具有较低的去除速率。
各个优势可以体现在方法100、半导体结构200的一个或多个实施例中。半导体结构200包括具有凸顶面的栅极堆叠件250。此外,此外,可以在边缘区的凸顶面上形成覆盖层260。覆盖层260用作阻挡层。例如,在随后形成接触件的操作期间,进行化学蚀刻(chemicaletchingisevolved)以开放随后形成的ILD层。蚀刻化学物质可以进一步从侧壁蚀刻至栅极堆叠件250并且因此损坏栅极堆叠件250。在保护覆盖层260的情况下,保护栅极堆叠件250以及由此使栅极堆叠件250免受损坏。因此,确保了器件质量和改进了器件性能。
因此,本发明提供了半导体结构。半导体结构包括半导体衬底;以及设置在半导体衬底上的栅极堆叠件;其中栅极堆叠件包括高k介电材料层,以及设置在高k介电材料层上的各个金属层,其中栅极堆叠件具有凸顶面。
根据一些实施例,本发明也提供了一种半导体结构。半导体结构包括半导体衬底;以及设置在半导体衬底上的栅极堆叠件,其中,栅极堆叠件包括栅极介电层,栅极介电层包括高k介电材料;以及设置在高k介电材料层上的覆盖层;设置在覆盖层上方的功函金属层;设置在功函金属层上的阻挡层,以及设置在阻挡层上的填充金属层。栅极堆叠件具有凸顶面。
根据一些实施例,本发明提供了一种方法。方法包括在半导体衬底上形成伪栅极;在衬底上形成层间介电层;去除伪栅极,在层间介电层中产生栅极沟槽;形成各个栅极材料层以填充在沟槽中,其中栅极材料层包括栅极介电层、位于覆盖层上的各个金属层;以及实施选择性去除工艺,由此形成具有凸顶面的栅极堆叠件。
根据本发明的一个实施例,提供了一种半导体结构,包括:半导体衬底;以及栅极堆叠件,设置在所述半导体衬底上,其中,所述栅极堆叠件包括高k介电材料层以及设置在所述高k介电材料层上的各个金属层,其中,所述栅极堆叠件具有凸顶面。
在上述半导体结构中,所述栅极堆叠件的所述凸顶面具有高度差H和宽度W;以及比率H/W的范围是从约10%至约50%。
在上述半导体结构中,所述高度差H的范围是从约2nm至约10nm。
在上述半导体结构中,还包括顶部覆盖层,所述顶部覆盖层设置在所述栅极堆叠件的在边缘区中的所述凸顶面上。
在上述半导体结构中,所述顶部覆盖层包括选自由氧化硅、氮化硅、低k介电材料和它们的组合组成的组的介电材料。
在上述半导体结构中,所述栅极堆叠件包括:位于所述半导体衬底上的界面层;位于所述界面层上的高k介电材料层;位于所述高k介电材料层上的覆盖层;设置在所述覆盖层上方的功函金属层;位于所述功函金属层上的阻挡层;以及填充金属层。
在上述半导体结构中,还包括设置在所述功函金属层和所述覆盖层之间的另一阻挡层。
在上述半导体结构中,所述界面层包括氧化硅;所述覆盖层包括氮化钛和氮化钽中的一种;所述阻挡层包括氮化钛和氮化钽中的一种;以及所述填充金属层包括铝和钨中的一种。
根据本发明的另一实施例,还提供了一种半导体结构,包括:半导体衬底;以及设置在所述半导体衬底上的栅极堆叠件;其中,所述栅极堆叠件包括:栅极介电层,所述栅极介电层包括高k介电材料;设置在所述高k介电材料层上的覆盖层;设置在所述覆盖层上方的功函金属层;设置在所述功函金属层上的阻挡层;以及设置在所述阻挡层上的填充金属层,其中,所述栅极堆叠件具有凸顶面。
在上述半导体结构中,所述栅极堆叠件的所述凸顶面具有高度差H和宽度W;以及比率H/W的范围是从约10%至约50%。
在上述半导体结构中,所述高度差H的范围是从约2nm至约10nm。
在上述半导体结构中,还包括顶部覆盖层,所述顶部覆盖层设置在所述栅极堆叠件的在边缘区中的所述凸顶面上。
在上述半导体结构中,所述顶部覆盖层包括选自由氧化硅、氮化硅、低k介电材料和它们的组合组成的组的介电材料。
根据本发明的又另一实施例,还提供了一种形成半导体结构的方法,包括:在半导体衬底上形成伪栅极;在所述衬底上形成层间介电层;去除所述伪栅极,在所述层间介电层中产生栅极沟槽;形成各个栅极材料层以填充在所述栅极沟槽中,其中,所述栅极材料层包括栅极介电层、位于所述覆盖层上的各个金属层;以及实施选择性去除工艺,由此形成具有凸顶面的栅极堆叠件。
在上述方法中,所述选择性去除工艺包括选择性化学机械抛光(CMP)工艺,其中,所述选择性CMP工艺使用具有化学物质的浆体以提供对所述各个金属层的选择性去除速率。
在上述方法中,所述选择性去除工艺包括选择性蚀刻工艺,其中,所述选择性蚀刻工艺使用对所述各个金属层具有选择性蚀刻速率的蚀刻剂。
在上述方法中,所述蚀刻剂包括第一蚀刻剂,所述第一蚀刻剂包括选自由F2、Cl2、BCl3和它们的组合组成的组的化学物质。
在上述方法中,所述的形成各个栅极材料层包括形成:栅极介电层,所述栅极介电层包括高k介电材料;设置在所述高k介电材料层上的覆盖层;设置在所述覆盖层上方的功函金属层;设置在所述功函金属层上的阻挡层;以及设置在所述阻挡层上的填充金属层,其中,所述栅极堆叠件具有凸顶面。
在上述方法中,还包括在所述栅极堆叠件的在边缘区中的所述凸顶面上形成顶部覆盖层,其中,所述顶部覆盖层的形成包括在所述衬底和所述栅极堆叠件上沉积介电层;以及对所述顶部覆盖层实施化学机械抛光工艺。
在上述方法中,所述顶部覆盖层的所述沉积包括沉积介电材料层,所述介电材料层选自由氧化硅、氮化硅、低k介电材料和它们的组合组成的组。
上面概述了若干实施例的特征。本领域技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,在此他们可以做出多种变化、替换以及改变。
Claims (10)
1.一种半导体结构,包括:
半导体衬底;以及
栅极堆叠件,设置在所述半导体衬底上,其中,所述栅极堆叠件包括高k介电材料层以及设置在所述高k介电材料层上的各个金属层,其中,所述栅极堆叠件具有凸顶面。
2.根据权利要求1所述的半导体结构,其中,所述栅极堆叠件的所述凸顶面具有高度差H和宽度W;以及比率H/W的范围是从约10%至约50%。
3.根据权利要求2所述的半导体结构,其中,所述高度差H的范围是从约2nm至约10nm。
4.根据权利要求1所述的半导体结构,还包括顶部覆盖层,所述顶部覆盖层设置在所述栅极堆叠件的在边缘区中的所述凸顶面上。
5.根据权利要求4所述的半导体结构,其中,所述顶部覆盖层包括选自由氧化硅、氮化硅、低k介电材料和它们的组合组成的组的介电材料。
6.根据权利要求1所述的半导体结构,其中,所述栅极堆叠件包括:
位于所述半导体衬底上的界面层;
位于所述界面层上的高k介电材料层;
位于所述高k介电材料层上的覆盖层;
设置在所述覆盖层上方的功函金属层;
位于所述功函金属层上的阻挡层;以及
填充金属层。
7.根据权利要求6所述的半导体结构,还包括设置在所述功函金属层和所述覆盖层之间的另一阻挡层。
8.根据权利要求5所述的半导体结构,其中
所述界面层包括氧化硅;
所述覆盖层包括氮化钛和氮化钽中的一种;
所述阻挡层包括氮化钛和氮化钽中的一种;以及
所述填充金属层包括铝和钨中的一种。
9.一种半导体结构,包括:
半导体衬底;以及
设置在所述半导体衬底上的栅极堆叠件;其中,所述栅极堆叠件包括:
栅极介电层,所述栅极介电层包括高k介电材料;
设置在所述高k介电材料层上的覆盖层;
设置在所述覆盖层上方的功函金属层;
设置在所述功函金属层上的阻挡层;以及
设置在所述阻挡层上的填充金属层,其中,所述栅极堆叠件具有凸顶面。
10.一种形成半导体结构的方法,包括:
在半导体衬底上形成伪栅极;
在所述衬底上形成层间介电层;
去除所述伪栅极,在所述层间介电层中产生栅极沟槽;
形成各个栅极材料层以填充在所述栅极沟槽中,其中,所述栅极材料层包括栅极介电层、位于所述覆盖层上的各个金属层;以及
实施选择性去除工艺,由此形成具有凸顶面的栅极堆叠件。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201462098005P | 2014-12-30 | 2014-12-30 | |
US62/098,005 | 2014-12-30 | ||
US14/687,447 US9876114B2 (en) | 2014-12-30 | 2015-04-15 | Structure and method for 3D FinFET metal gate |
US14/687,447 | 2015-04-15 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN105742343A true CN105742343A (zh) | 2016-07-06 |
CN105742343B CN105742343B (zh) | 2019-06-14 |
Family
ID=56116834
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201510777147.6A Active CN105742343B (zh) | 2014-12-30 | 2015-11-13 | 用于3d finfet金属栅极的结构和方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US9876114B2 (zh) |
KR (1) | KR101887255B1 (zh) |
CN (1) | CN105742343B (zh) |
DE (1) | DE102015107272B4 (zh) |
TW (1) | TWI594303B (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109309123A (zh) * | 2017-07-28 | 2019-02-05 | 联华电子股份有限公司 | 半导体元件及其制作方法 |
CN110943160A (zh) * | 2018-09-21 | 2020-03-31 | 台湾积体电路制造股份有限公司 | 集成芯片及其形成方法 |
Families Citing this family (37)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10090304B2 (en) * | 2013-09-25 | 2018-10-02 | Intel Corporation | Isolation well doping with solid-state diffusion sources for FinFET architectures |
CN106252391B (zh) * | 2015-06-09 | 2021-02-19 | 联华电子股份有限公司 | 半导体结构及其制作方法 |
US9685368B2 (en) | 2015-06-26 | 2017-06-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure having an etch stop layer over conductive lines |
US10644153B2 (en) * | 2016-02-25 | 2020-05-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method for fabricating the same |
US9640540B1 (en) | 2016-07-19 | 2017-05-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and method for an SRAM circuit |
US10522650B2 (en) | 2016-11-29 | 2019-12-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and methods of manufacture |
US10340370B2 (en) | 2016-12-07 | 2019-07-02 | Qualcomm Incorporated | Asymmetric gated fin field effect transistor (FET) (finFET) diodes |
DE102018114750A1 (de) | 2017-11-14 | 2019-05-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Transistor-layout zum reduzieren des kink-effekts |
US10510855B2 (en) | 2017-11-14 | 2019-12-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Transistor layout to reduce kink effect |
US10468410B2 (en) * | 2017-11-15 | 2019-11-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Metal gate modulation to improve kink effect |
US10355102B2 (en) | 2017-11-15 | 2019-07-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method of manufacturing the same |
US10510889B2 (en) * | 2017-11-29 | 2019-12-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | P-type strained channel in a fin field effect transistor (FinFET) device |
EP4220719A3 (en) * | 2017-11-30 | 2023-08-16 | INTEL Corporation | Fin patterning for advanced integrated circuit structure fabrication |
US10868116B2 (en) | 2017-11-30 | 2020-12-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Circuit structure and method for reducing electronic noises |
US10381481B1 (en) | 2018-04-27 | 2019-08-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multi-layer photoresist |
US10504775B1 (en) | 2018-05-31 | 2019-12-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods of forming metal layer structures in semiconductor devices |
US10755970B2 (en) | 2018-06-15 | 2020-08-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structures |
US10930794B2 (en) | 2018-06-29 | 2021-02-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Self-aligned spacers for multi-gate devices and method of fabrication thereof |
US11444174B2 (en) | 2018-08-17 | 2022-09-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with Fin end spacer dummy gate and method of manufacturing the same |
US10797174B2 (en) | 2018-08-17 | 2020-10-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with fin end spacer dummy gate and method of manufacturing the same |
US11056393B2 (en) | 2018-09-27 | 2021-07-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for FinFET fabrication and structure thereof |
US10923565B2 (en) | 2018-09-27 | 2021-02-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Self-aligned contact air gap formation |
US11380682B2 (en) | 2018-10-23 | 2022-07-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuits with FinFET gate structures |
US11239313B2 (en) | 2018-10-30 | 2022-02-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated chip and method of forming thereof |
US11217484B2 (en) | 2018-10-31 | 2022-01-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET gate structure and related methods |
US11257673B2 (en) | 2018-11-26 | 2022-02-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dual spacer metal patterning |
US11152486B2 (en) | 2019-07-15 | 2021-10-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET semiconductor device having source/drain contact(s) separated by airgap spacer(s) from the gate stack(s) to reduce parasitic capacitance |
US11437372B2 (en) | 2019-09-26 | 2022-09-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Liner structures |
US11690209B2 (en) | 2019-09-28 | 2023-06-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin-based well straps for improving memory macro performance |
US11508738B2 (en) | 2020-02-27 | 2022-11-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | SRAM speed and margin optimization via spacer tuning |
US11610977B2 (en) | 2020-07-28 | 2023-03-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods of forming nano-sheet-based devices having inner spacer structures with different widths |
US11527621B2 (en) | 2020-08-05 | 2022-12-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Gate electrode deposition and structure formed thereby |
US11735484B2 (en) | 2020-09-30 | 2023-08-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Post gate dielectric processing for semiconductor device fabrication |
US11728401B2 (en) | 2020-10-30 | 2023-08-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structures and methods thereof |
US11637195B2 (en) | 2020-11-02 | 2023-04-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal gate patterning process including dielectric Fin formation |
US11605563B2 (en) | 2021-04-16 | 2023-03-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with non-conformal gate dielectric layers |
US11862709B2 (en) | 2021-04-28 | 2024-01-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Inner spacer structure and methods of forming such |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1638130A (zh) * | 2004-01-05 | 2005-07-13 | 三星电子株式会社 | 半导体存储器及其制造方法 |
JP2007080955A (ja) * | 2005-09-12 | 2007-03-29 | Nec Corp | 半導体装置及びその製造方法 |
US20130260549A1 (en) * | 2012-03-27 | 2013-10-03 | International Business Machines Corporation | Replacement gate with reduced gate leakage current |
US20130273729A1 (en) * | 2009-10-30 | 2013-10-17 | Globalfoundries Inc. | High-k metal gate electrode structures formed by separate removal of placeholder materials in transistors of different conductivity type |
US20130328111A1 (en) * | 2012-06-08 | 2013-12-12 | International Business Machine Corporations | Recessing and capping of gate structures with varying metal compositions |
Family Cites Families (43)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4762118B2 (ja) * | 2006-11-17 | 2011-08-31 | 株式会社東芝 | 不揮発性半導体記憶装置 |
US7820552B2 (en) * | 2007-03-13 | 2010-10-26 | International Business Machines Corporation | Advanced high-k gate stack patterning and structure containing a patterned high-k gate stack |
US7667271B2 (en) | 2007-04-27 | 2010-02-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin field-effect transistors |
JP2008282901A (ja) | 2007-05-09 | 2008-11-20 | Sony Corp | 半導体装置および半導体装置の製造方法 |
US7875519B2 (en) | 2008-05-21 | 2011-01-25 | Intel Corporation | Metal gate structure and method of manufacturing same |
US7910453B2 (en) | 2008-07-14 | 2011-03-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Storage nitride encapsulation for non-planar sonos NAND flash charge retention |
US8440517B2 (en) | 2010-10-13 | 2013-05-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET and method of fabricating the same |
US8497528B2 (en) | 2010-05-06 | 2013-07-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for fabricating a strained structure |
US9245805B2 (en) | 2009-09-24 | 2016-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Germanium FinFETs with metal gates and stressors |
US8362575B2 (en) | 2009-09-29 | 2013-01-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Controlling the shape of source/drain regions in FinFETs |
DE102009043628B4 (de) * | 2009-09-30 | 2011-12-01 | Globalfoundries Dresden Module One Llc & Co. Kg | Verbesserte Füllbedingungen in einem Austauschgateverfahren durch Ausführen eines Polierprozesses auf der Grundlage eines Opferfüllmaterials |
US8610240B2 (en) | 2009-10-16 | 2013-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit with multi recessed shallow trench isolation |
US8436404B2 (en) | 2009-12-30 | 2013-05-07 | Intel Corporation | Self-aligned contacts |
US8310013B2 (en) | 2010-02-11 | 2012-11-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating a FinFET device |
US8399931B2 (en) | 2010-06-30 | 2013-03-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Layout for multiple-fin SRAM cell |
US8729627B2 (en) | 2010-05-14 | 2014-05-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained channel integrated circuit devices |
US8796759B2 (en) | 2010-07-15 | 2014-08-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin-like field effect transistor (FinFET) device and method of manufacturing same |
US8367498B2 (en) | 2010-10-18 | 2013-02-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin-like field effect transistor (FinFET) device and method of manufacturing same |
US8816444B2 (en) | 2011-04-29 | 2014-08-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and methods for converting planar design to FinFET design |
US8962400B2 (en) | 2011-07-07 | 2015-02-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | In-situ doping of arsenic for source and drain epitaxy |
US8841701B2 (en) | 2011-08-30 | 2014-09-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device having a channel defined in a diamond-like shape semiconductor structure |
US8466027B2 (en) | 2011-09-08 | 2013-06-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Silicide formation and associated devices |
US8723272B2 (en) | 2011-10-04 | 2014-05-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device and method of manufacturing same |
US8723236B2 (en) | 2011-10-13 | 2014-05-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device and method of manufacturing same |
US8377779B1 (en) | 2012-01-03 | 2013-02-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of manufacturing semiconductor devices and transistors |
US8735993B2 (en) | 2012-01-31 | 2014-05-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET body contact and method of making same |
US8847293B2 (en) | 2012-03-02 | 2014-09-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gate structure for semiconductor device |
US8785285B2 (en) | 2012-03-08 | 2014-07-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and methods of manufacture thereof |
US8836016B2 (en) | 2012-03-08 | 2014-09-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structures and methods with high mobility and high energy bandgap materials |
US8716765B2 (en) | 2012-03-23 | 2014-05-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact structure of semiconductor device |
US8860148B2 (en) | 2012-04-11 | 2014-10-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for FinFET integrated with capacitor |
US8680576B2 (en) | 2012-05-16 | 2014-03-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | CMOS device and method of forming the same |
US8729634B2 (en) | 2012-06-15 | 2014-05-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET with high mobility and strain channel |
US8736056B2 (en) | 2012-07-31 | 2014-05-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Device for reducing contact resistance of a metal |
US8823065B2 (en) | 2012-11-08 | 2014-09-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact structure of semiconductor device |
US8772109B2 (en) | 2012-10-24 | 2014-07-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Apparatus and method for forming semiconductor contacts |
US8809139B2 (en) | 2012-11-29 | 2014-08-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin-last FinFET and methods of forming same |
US9236300B2 (en) | 2012-11-30 | 2016-01-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact plugs in SRAM cells and the method of forming the same |
US8853025B2 (en) | 2013-02-08 | 2014-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET/tri-gate channel doping for multiple threshold voltage tuning |
US9093514B2 (en) | 2013-03-06 | 2015-07-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Strained and uniform doping technique for FINFETs |
US9590109B2 (en) * | 2013-08-30 | 2017-03-07 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
US9337195B2 (en) * | 2013-12-18 | 2016-05-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and methods of manufacture thereof |
US10134861B2 (en) * | 2014-10-08 | 2018-11-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure and method for forming the same |
-
2015
- 2015-04-15 US US14/687,447 patent/US9876114B2/en active Active
- 2015-05-11 DE DE102015107272.6A patent/DE102015107272B4/de active Active
- 2015-07-23 TW TW104123910A patent/TWI594303B/zh active
- 2015-07-24 KR KR1020150104858A patent/KR101887255B1/ko active IP Right Grant
- 2015-11-13 CN CN201510777147.6A patent/CN105742343B/zh active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1638130A (zh) * | 2004-01-05 | 2005-07-13 | 三星电子株式会社 | 半导体存储器及其制造方法 |
JP2007080955A (ja) * | 2005-09-12 | 2007-03-29 | Nec Corp | 半導体装置及びその製造方法 |
US20130273729A1 (en) * | 2009-10-30 | 2013-10-17 | Globalfoundries Inc. | High-k metal gate electrode structures formed by separate removal of placeholder materials in transistors of different conductivity type |
US20130260549A1 (en) * | 2012-03-27 | 2013-10-03 | International Business Machines Corporation | Replacement gate with reduced gate leakage current |
US20130328111A1 (en) * | 2012-06-08 | 2013-12-12 | International Business Machine Corporations | Recessing and capping of gate structures with varying metal compositions |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109309123A (zh) * | 2017-07-28 | 2019-02-05 | 联华电子股份有限公司 | 半导体元件及其制作方法 |
CN109309123B (zh) * | 2017-07-28 | 2020-11-10 | 联华电子股份有限公司 | 半导体元件及其制作方法 |
CN110943160A (zh) * | 2018-09-21 | 2020-03-31 | 台湾积体电路制造股份有限公司 | 集成芯片及其形成方法 |
CN110943160B (zh) * | 2018-09-21 | 2024-02-02 | 台湾积体电路制造股份有限公司 | 集成芯片及其形成方法 |
Also Published As
Publication number | Publication date |
---|---|
US9876114B2 (en) | 2018-01-23 |
KR20160082346A (ko) | 2016-07-08 |
US20160190305A1 (en) | 2016-06-30 |
TW201624548A (zh) | 2016-07-01 |
CN105742343B (zh) | 2019-06-14 |
DE102015107272B4 (de) | 2024-02-15 |
DE102015107272A1 (de) | 2016-06-30 |
KR101887255B1 (ko) | 2018-08-09 |
TWI594303B (zh) | 2017-08-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN105742343B (zh) | 用于3d finfet金属栅极的结构和方法 | |
TWI731284B (zh) | 半導體結構及形成積體電路結構的方法 | |
US11749720B2 (en) | Integrated circuit structure and method with solid phase diffusion | |
US10734519B2 (en) | Structure and method for FinFET device with asymmetric contact | |
TWI570915B (zh) | 半導體裝置以及製造鰭式場效電晶體裝置的方法 | |
KR101799636B1 (ko) | 핀 구조 전계 효과 트랜지스터 소자용 구조체 및 방법 | |
US8466027B2 (en) | Silicide formation and associated devices | |
US9337195B2 (en) | Semiconductor devices and methods of manufacture thereof | |
CN105280700A (zh) | 用于mosfet器件的结构和方法 | |
CN104681615A (zh) | 用于具有掩埋SiGe氧化物的FinFET器件的结构和方法 | |
TW202029358A (zh) | 具有波狀接觸窗輪廓的半導體裝置 | |
US11735594B2 (en) | Integrated circuit structure and method with hybrid orientation for FinFET | |
US20220293792A1 (en) | Structure and Method for FinFET Device with Asymmetric Contact | |
TW202004989A (zh) | 半導體結構及形成積體電路結構的方法 | |
TWI783302B (zh) | 半導體裝置及其形成方法 | |
KR102524729B1 (ko) | 후면 전력 레일을 갖는 트랜지스터를 위한 구조물 및 방법 | |
US20230411399A1 (en) | Integrated Circuit Structure and Method with Hybrid Orientation for FinFET | |
TWI521709B (zh) | 半導體結構及積體電路之製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |